)]}'
{
  "commit": "014406b510faae91b801c8c6fd408a7609f6de0b",
  "tree": "266f04a3f2b64fb055a29d0c54b8e5ba849ca4a1",
  "parents": [
    "0ff644a786aa041a8616ce449382806d8e29d04c"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Apr 15 19:18:45 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Apr 17 21:34:05 2014 +0100"
  },
  "message": "target-arm: Implement AArch64 view of CONTEXTIDR\n\nImplement AArch64 view of the CONTEXTIDR register.\nWe tighten up the condition when we flush the TLB on a CONTEXTIDR\nwrite to avoid needlessly flushing the TLB every time on a 64\nbit system (and also on a 32 bit system using LPAE, as a bonus).\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ec0306b7a3b664a176a02815654b5f608a903260",
      "old_mode": 33188,
      "old_path": "target-arm/cpu.h",
      "new_id": "d0f42fd72af2e8d3243e1203fbc017e64ca049d1",
      "new_mode": 33188,
      "new_path": "target-arm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "655c5abed60d191b6a4f8ae43e4620138a357b7d",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "10300aa331c7f30529432bcc5f66991449ef6203",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}