)]}'
{
  "commit": "02bccc7796fec8b39dca9affc8bff8edebe0a867",
  "tree": "f49a334715be30e48149f569071410c9b4abca79",
  "parents": [
    "a427338b222b43197c2776cbc996936df0302f51"
  ],
  "author": {
    "name": "Paul Burton",
    "email": "paul.burton@imgtec.com",
    "time": "Fri Jun 14 08:30:45 2013 +0100"
  },
  "committer": {
    "name": "Aurelien Jarno",
    "email": "aurelien@aurel32.net",
    "time": "Sun Jul 28 19:59:22 2013 +0200"
  },
  "message": "mips_malta: generate SPD EEPROM data at runtime\n\nThe SPD EEPROM specifies the amount of memory present in the system and\nthus its correct contents can only be known at runtime. Calculating\nparts of the data on init allows the data to accurately reflect the\namount of target memory present and allow YAMON to boot with an\narbitrary amount of SDRAM.\n\nWhere possible the SPD data will favor indicating 2 banks of SDRAM\nrather than 1. For example the default 128MB of target memory will be\nrepresented as 2x64MB banks rather than 1x128MB bank. This allows\nversions of MIPS BIOS code (such as YAMON 2.22 and older) to boot\ndespite a bug preventing them from handling a single bank of SDRAM with\nthe Galileo GT64120 system controller emulated by QEMU.\n\nSigned-off-by: Paul Burton \u003cpaul.burton@imgtec.com\u003e\nSigned-off-by: Leon Alrae \u003cleon.alrae@imgtec.com\u003e\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2edc8e16f51ab9ed4342a0d3dc0751bf0964dec2",
      "old_mode": 33188,
      "old_path": "hw/mips/mips_malta.c",
      "new_id": "e06e19d2df5609f336c978d0e31f02677d4bd3ba",
      "new_mode": 33188,
      "new_path": "hw/mips/mips_malta.c"
    }
  ]
}