)]}'
{
  "commit": "02d4eae4b0be19d84996105cf6e0cc33f41e3833",
  "tree": "b5b3001e2a4e9c3e19d0176cba88832a1bc9fc29",
  "parents": [
    "74b41e5676568e6560474267bbf1a5a32d3e2c41"
  ],
  "author": {
    "name": "David Gibson",
    "email": "david@gibson.dropbear.id.au",
    "time": "Sun Oct 30 15:51:24 2011 +0000"
  },
  "committer": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Mon Oct 31 02:57:56 2011 +0100"
  },
  "message": "ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate\n\nThe CPU state contains two bitmaps, initialized from the CPU spec\nwhich describes which instructions are implemented on the CPU.  A\ncouple of bits are defined which cover instructions (VSX and DFP)\nwhich are not currently implemented in TCG.  So far, these are only\nused to handle the case of -cpu host because a KVM guest can use\nthe instructions when the host CPU supports them.\n\nHowever, it\u0027s a mild layering violation to simply not include those\nbits in the CPU descriptions for those CPUs that do support them,\njust because we can\u0027t handle them in TCG.  This patch corrects the\nsituation, so that the instruction bits _are_ shown correctly in the\ncpu spec table, but are masked out from the cpu state in the non-KVM\ncase.\n\nSigned-off-by: David Gibson \u003cdavid@gibson.dropbear.id.au\u003e\nSigned-off-by: Alexander Graf \u003cagraf@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3ef4eba836ffb60fc87c6d9117405ce47fa60b5d",
      "old_mode": 33188,
      "old_path": "target-ppc/cpu.h",
      "new_id": "e84108c49a1a2bbbb3f81d4c6c96fa35a552bc15",
      "new_mode": 33188,
      "new_path": "target-ppc/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "4dfd7f3bfb846c7d3055ced70b1038ddf23f2304",
      "old_mode": 33188,
      "old_path": "target-ppc/translate_init.c",
      "new_id": "8a7233fc820ce3e2f1b050d5c9c9679276b3c516",
      "new_mode": 33188,
      "new_path": "target-ppc/translate_init.c"
    }
  ]
}