tree b080513d06e331b97f9a8d38101e4e5bc0e03c3c
parent 6e270446d0e107b5227d8c51d2f85546f8811e99
author Ben Herrenschmidt <benh@kernel.crashing.org> 1301631332 +1100
committer Alexander Graf <agraf@suse.de> 1301675697 +0200

Add a PAPR TCE-bypass mechanism for the pSeries machine

Usually, PAPR virtual IO devices use a virtual IOMMU mechanism, TCEs,
to mediate all DMA transfers.  While this is necessary for some sorts of
operation, it can be complex to program and slow for others.

This patch implements a mechanism for bypassing TCE translation, treating
"IO" addresses as plain (guest) physical memory addresses.  This has two
main uses:
 * Simple, but 64-bit aware programs like firmwares can use the VIO devices
without the complexity of TCE setup.
 * The guest OS can optionally use the TCE bypass to improve performance in
suitable situations.

The mechanism used is a per-device flag which disables TCE translation.
The flag is toggled with some (hypervisor-implemented) RTAS methods.

Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>