target-mips & softmmu: Misaligned Memory Accesses for R6/MSA
This patch is the last one in a series of 3 patches that optimize the
Misaligned Memory Access overhead for MIPS R6 + MSA where these accesses
should be handled in hardware.
The patch integrates 3 commits from Qemu ToT. They are required to
enable support for unaligned accesses for R6 and MSA. Also, one of
those commits adds probe_write() function in order to probe for
whether the specified guest write access is permitted or not.
If it is not permitted then an exception will be taken in the same
way as if this were a real write access (and we will not return).
Otherwise the function will return, and there will be a valid
entry in the TLB for this access.
List of squashed commits from Qemu ToT:
adc370a target-mips: Misaligned memory accesses for MSA
3b4afc9 softmmu: Add probe_write()
be3a8c5 target-mips: Misaligned memory accesses for R6
Change-Id: I00d745a0a6ba45f7e56666b25f732f6faf0e5080
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
6 files changed
