Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-peter' into staging
QOM infrastructure fixes and device conversions
* Changes to name string ownership for alias properties
* Improvements around enum properties
* Cleanups around -object handling
* New helper functions
* Cleanups of qdev init helper functions
* Add path argument to qom-tree script
* QTest cleanup to use new qtest_add_data_func() consistently
# gpg: Signature made Fri Jun 19 18:14:38 2015 BST using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <afaerber@suse.de>"
# gpg: aka "Andreas Färber <afaerber@suse.com>"
* remotes/afaerber/tags/qom-devices-for-peter:
qdev: Un-deprecate qdev_init_nofail()
qdev: Deprecated qdev_init() is finally unused, drop
qom: Don't pass string table to object_get_enum() function
qom: Add an object_property_add_enum() helper function
qom: Make enum string tables const-correct
qom: Add object_new_with_props() / object_new_withpropv() helpers
qom: Add helper function for getting user objects root
vl: Create (most) objects before creating chardev backends
doc: Document user creatable object types in help text
backends: Fix typename of 'policy' enum property in hostmem obj
scripts: Add support for path as argument of qom-tree
tests: Use qtest_add_data_func() consistently
qdev: Free property names after registering gpio aliases
qom: strdup() target property name on object_property_add_alias()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f801e0..106e2e4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -702,6 +702,7 @@
M: Michael S. Tsirkin <mst@redhat.com>
S: Supported
F: hw/*/virtio*
+F: net/vhost-user.c
virtio-9p
M: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
diff --git a/Makefile b/Makefile
index 3f97904..e7c5c3a 100644
--- a/Makefile
+++ b/Makefile
@@ -74,7 +74,7 @@
configure: ;
.PHONY: all clean cscope distclean dvi html info install install-doc \
- pdf recurse-all speed test dist
+ pdf recurse-all speed test dist msi
$(call set-vpath, $(SRC_PATH))
@@ -287,10 +287,32 @@
qemu-ga$(EXESUF): $(qga-obj-y) libqemuutil.a libqemustub.a
$(call LINK, $^)
+ifdef QEMU_GA_MSI_ENABLED
+QEMU_GA_MSI=qemu-ga-$(ARCH).msi
+
+msi: ${QEMU_GA_MSI}
+
+$(QEMU_GA_MSI): qemu-ga.exe
+
+ifdef QEMU_GA_MSI_WITH_VSS
+$(QEMU_GA_MSI): qga/vss-win32/qga-vss.dll
+endif
+
+$(QEMU_GA_MSI): config-host.mak
+
+$(QEMU_GA_MSI): qga/installer/qemu-ga.wxs
+ $(call quiet-command,QEMU_GA_VERSION="$(QEMU_GA_VERSION)" QEMU_GA_MANUFACTURER="$(QEMU_GA_MANUFACTURER)" QEMU_GA_DISTRO="$(QEMU_GA_DISTRO)" \
+ wixl -o $@ $(QEMU_GA_MSI_ARCH) $(QEMU_GA_MSI_WITH_VSS) $(QEMU_GA_MSI_MINGW_DLL_PATH) $<, " WIXL $@")
+else
+msi:
+ @echo MSI build not configured or dependency resolution failed (reconfigure with --enable-guest-agent-msi option)
+endif
+
clean:
# avoid old build problems by removing potentially incorrect old files
rm -f config.mak op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h
rm -f qemu-options.def
+ rm -f *.msi
find . \( -name '*.l[oa]' -o -name '*.so' -o -name '*.dll' -o -name '*.mo' -o -name '*.[oda]' \) -type f -exec rm {} +
rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) qemu-ga TAGS cscope.* *.pod *~ */*~
rm -f fsdev/*.pod
diff --git a/configure b/configure
index 222694f..6fed07b 100755
--- a/configure
+++ b/configure
@@ -315,6 +315,7 @@
bzip2=""
guest_agent=""
guest_agent_with_vss="no"
+guest_agent_msi=""
vss_win32_sdk=""
win_sdk="no"
want_tools="yes"
@@ -1078,6 +1079,10 @@
;;
--disable-guest-agent) guest_agent="no"
;;
+ --enable-guest-agent-msi) guest_agent_msi="yes"
+ ;;
+ --disable-guest-agent-msi) guest_agent_msi="no"
+ ;;
--with-vss-sdk) vss_win32_sdk=""
;;
--with-vss-sdk=*) vss_win32_sdk="$optarg"
@@ -1394,6 +1399,8 @@
reading bzip2-compressed dmg images)
--disable-guest-agent disable building of the QEMU Guest Agent
--enable-guest-agent enable building of the QEMU Guest Agent
+ --enable-guest-agent-msi enable building guest agent Windows MSI installation package
+ --disable-guest-agent-msi disable building guest agent Windows MSI installation
--with-vss-sdk=SDK-path enable Windows VSS support in QEMU Guest Agent
--with-win-sdk=SDK-path path to Windows Platform SDK (to build VSS .tlb)
--disable-seccomp disable seccomp support
@@ -3862,6 +3869,56 @@
fi
##########################################
+# Guest agent Window MSI package
+
+if test "$guest_agent" != yes; then
+ if test "$guest_agent_msi" = yes; then
+ error_exit "MSI guest agent package requires guest agent enabled"
+ fi
+ guest_agent_msi=no
+elif test "$mingw32" != "yes"; then
+ if test "$guest_agent_msi" = "yes"; then
+ error_exit "MSI guest agent package is available only for MinGW Windows cross-compilation"
+ fi
+ guest_agent_msi=no
+elif ! has wixl; then
+ if test "$guest_agent_msi" = "yes"; then
+ error_exit "MSI guest agent package requires wixl tool installed ( usually from msitools package )"
+ fi
+ guest_agent_msi=no
+fi
+
+if test "$guest_agent_msi" != "no"; then
+ if test "$guest_agent_with_vss" = "yes"; then
+ QEMU_GA_MSI_WITH_VSS="-D InstallVss"
+ fi
+
+ if test "$QEMU_GA_MANUFACTURER" = ""; then
+ QEMU_GA_MANUFACTURER=QEMU
+ fi
+
+ if test "$QEMU_GA_DISTRO" = ""; then
+ QEMU_GA_DISTRO=Linux
+ fi
+
+ if test "$QEMU_GA_VERSION" = ""; then
+ QEMU_GA_VERSION=`cat $source_path/VERSION`
+ fi
+
+ QEMU_GA_MSI_MINGW_DLL_PATH="-D Mingw_dlls=`$pkg_config --variable=prefix glib-2.0`/bin"
+
+ case "$cpu" in
+ x86_64)
+ QEMU_GA_MSI_ARCH="-a x64 -D Arch=64"
+ ;;
+ i386)
+ QEMU_GA_MSI_ARCH="-D Arch=32"
+ ;;
+ *)
+ error_exit "CPU $cpu not supported for building installation package"
+ ;;
+ esac
+fi
##########################################
# check if we have fdatasync
@@ -4558,6 +4615,15 @@
echo "CONFIG_QGA_VSS=y" >> $config_host_mak
echo "WIN_SDK=\"$win_sdk\"" >> $config_host_mak
fi
+ if test "$guest_agent_msi" != "no"; then
+ echo "QEMU_GA_MSI_ENABLED=yes" >> $config_host_mak
+ echo "QEMU_GA_MSI_MINGW_DLL_PATH=${QEMU_GA_MSI_MINGW_DLL_PATH}" >> $config_host_mak
+ echo "QEMU_GA_MSI_WITH_VSS=${QEMU_GA_MSI_WITH_VSS}" >> $config_host_mak
+ echo "QEMU_GA_MSI_ARCH=${QEMU_GA_MSI_ARCH}" >> $config_host_mak
+ echo "QEMU_GA_MANUFACTURER=${QEMU_GA_MANUFACTURER}" >> $config_host_mak
+ echo "QEMU_GA_DISTRO=${QEMU_GA_DISTRO}" >> $config_host_mak
+ echo "QEMU_GA_VERSION=${QEMU_GA_VERSION}" >> $config_host_mak
+ fi
else
echo "CONFIG_POSIX=y" >> $config_host_mak
fi
diff --git a/exec.c b/exec.c
index 76bfc4a..f7883d2 100644
--- a/exec.c
+++ b/exec.c
@@ -341,6 +341,7 @@
hwaddr *plen, bool resolve_subpage)
{
MemoryRegionSection *section;
+ MemoryRegion *mr;
Int128 diff;
section = address_space_lookup_region(d, addr, resolve_subpage);
@@ -350,8 +351,11 @@
/* Compute offset within MemoryRegion */
*xlat = addr + section->offset_within_region;
- diff = int128_sub(section->mr->size, int128_make64(addr));
- *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
+ mr = section->mr;
+ if (memory_region_is_ram(mr)) {
+ diff = int128_sub(section->size, int128_make64(addr));
+ *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
+ }
return section;
}
diff --git a/gdbstub.c b/gdbstub.c
index 75563db..cea2a84 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -40,6 +40,7 @@
#include "cpu.h"
#include "qemu/sockets.h"
#include "sysemu/kvm.h"
+#include "exec/semihost.h"
#ifdef CONFIG_USER_ONLY
#define GDB_ATTACHED "0"
@@ -323,8 +324,6 @@
bool gdb_has_xml;
-int semihosting_target = SEMIHOSTING_TARGET_AUTO;
-
#ifdef CONFIG_USER_ONLY
/* XXX: This is not thread safe. Do we care? */
static int gdbserver_fd = -1;
@@ -362,10 +361,11 @@
/* Decide if either remote gdb syscalls or native file IO should be used. */
int use_gdb_syscalls(void)
{
- if (semihosting_target == SEMIHOSTING_TARGET_NATIVE) {
+ SemihostingTarget target = semihosting_get_target();
+ if (target == SEMIHOSTING_TARGET_NATIVE) {
/* -semihosting-config target=native */
return false;
- } else if (semihosting_target == SEMIHOSTING_TARGET_GDB) {
+ } else if (target == SEMIHOSTING_TARGET_GDB) {
/* -semihosting-config target=gdb */
return true;
}
diff --git a/hw/arm/sysbus-fdt.c b/hw/arm/sysbus-fdt.c
index 3038b94..9d28797 100644
--- a/hw/arm/sysbus-fdt.c
+++ b/hw/arm/sysbus-fdt.c
@@ -26,6 +26,9 @@
#include "sysemu/device_tree.h"
#include "hw/platform-bus.h"
#include "sysemu/sysemu.h"
+#include "hw/vfio/vfio-platform.h"
+#include "hw/vfio/vfio-calxeda-xgmac.h"
+#include "hw/arm/fdt.h"
/*
* internal struct that contains the information to create dynamic
@@ -53,11 +56,81 @@
int (*add_fdt_node_fn)(SysBusDevice *sbdev, void *opaque);
} NodeCreationPair;
+/* Device Specific Code */
+
+/**
+ * add_calxeda_midway_xgmac_fdt_node
+ *
+ * Generates a simple node with following properties:
+ * compatible string, regs, interrupts, dma-coherent
+ */
+static int add_calxeda_midway_xgmac_fdt_node(SysBusDevice *sbdev, void *opaque)
+{
+ PlatformBusFDTData *data = opaque;
+ PlatformBusDevice *pbus = data->pbus;
+ void *fdt = data->fdt;
+ const char *parent_node = data->pbus_node_name;
+ int compat_str_len, i, ret = -1;
+ char *nodename;
+ uint32_t *irq_attr, *reg_attr;
+ uint64_t mmio_base, irq_number;
+ VFIOPlatformDevice *vdev = VFIO_PLATFORM_DEVICE(sbdev);
+ VFIODevice *vbasedev = &vdev->vbasedev;
+
+ mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
+ nodename = g_strdup_printf("%s/%s@%" PRIx64, parent_node,
+ vbasedev->name, mmio_base);
+ qemu_fdt_add_subnode(fdt, nodename);
+
+ compat_str_len = strlen(vdev->compat) + 1;
+ qemu_fdt_setprop(fdt, nodename, "compatible",
+ vdev->compat, compat_str_len);
+
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", "", 0);
+
+ reg_attr = g_new(uint32_t, vbasedev->num_regions * 2);
+ for (i = 0; i < vbasedev->num_regions; i++) {
+ mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i);
+ reg_attr[2 * i] = cpu_to_be32(mmio_base);
+ reg_attr[2 * i + 1] = cpu_to_be32(
+ memory_region_size(&vdev->regions[i]->mem));
+ }
+ ret = qemu_fdt_setprop(fdt, nodename, "reg", reg_attr,
+ vbasedev->num_regions * 2 * sizeof(uint32_t));
+ if (ret) {
+ error_report("could not set reg property of node %s", nodename);
+ goto fail_reg;
+ }
+
+ irq_attr = g_new(uint32_t, vbasedev->num_irqs * 3);
+ for (i = 0; i < vbasedev->num_irqs; i++) {
+ irq_number = platform_bus_get_irqn(pbus, sbdev , i)
+ + data->irq_start;
+ irq_attr[3 * i] = cpu_to_be32(GIC_FDT_IRQ_TYPE_SPI);
+ irq_attr[3 * i + 1] = cpu_to_be32(irq_number);
+ irq_attr[3 * i + 2] = cpu_to_be32(GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ }
+ ret = qemu_fdt_setprop(fdt, nodename, "interrupts",
+ irq_attr, vbasedev->num_irqs * 3 * sizeof(uint32_t));
+ if (ret) {
+ error_report("could not set interrupts property of node %s",
+ nodename);
+ }
+ g_free(irq_attr);
+fail_reg:
+ g_free(reg_attr);
+ g_free(nodename);
+ return ret;
+}
+
/* list of supported dynamic sysbus devices */
static const NodeCreationPair add_fdt_node_functions[] = {
+ {TYPE_VFIO_CALXEDA_XGMAC, add_calxeda_midway_xgmac_fdt_node},
{"", NULL}, /* last element */
};
+/* Generic Code */
+
/**
* add_fdt_node - add the device tree node of a dynamic sysbus device
*
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f1e85c8..4e78083a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -47,21 +47,11 @@
#include "hw/arm/virt-acpi-build.h"
#include "hw/arm/sysbus-fdt.h"
#include "hw/platform-bus.h"
+#include "hw/arm/fdt.h"
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 256
-#define GIC_FDT_IRQ_TYPE_SPI 0
-#define GIC_FDT_IRQ_TYPE_PPI 1
-
-#define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
-#define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
-#define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
-#define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
-
-#define GIC_FDT_IRQ_PPI_CPU_START 8
-#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
-
#define PLATFORM_BUS_NUM_IRQS 64
static ARMPlatformBusSystemParams platform_bus_params;
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index b924f5e..f94da86 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -65,7 +65,7 @@
xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
xlnx_ep108_binfo.loader_start = 0;
- arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo);
+ arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo);
}
static QEMUMachine xlnx_ep108_machine = {
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 6b01965..5e72078 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -64,10 +64,17 @@
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
int i;
- for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
- object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+ object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
"cortex-a53-" TYPE_ARM_CPU);
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
+ object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
+ &error_abort);
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
+ object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
+ "cortex-r5-" TYPE_ARM_CPU);
+ object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
&error_abort);
}
@@ -90,12 +97,13 @@
XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
MemoryRegion *system_memory = get_system_memory();
uint8_t i;
+ const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
qemu_irq gic_spi[GIC_NUM_SPI_INTR];
Error *err = NULL;
qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
- qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err) {
error_propagate((errp), (err));
@@ -121,38 +129,77 @@
}
}
- for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
qemu_irq irq;
+ char *name;
- object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
+ object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
- if (i > 0) {
+
+ name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
+ if (strcmp(name, boot_cpu)) {
/* Secondary CPUs start in PSCI powered-down state */
- object_property_set_bool(OBJECT(&s->cpu[i]), true,
+ object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
"start-powered-off", &error_abort);
+ } else {
+ s->boot_cpu_ptr = &s->apu_cpu[i];
}
- object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR,
+ object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
"reset-cbar", &err);
if (err) {
error_propagate((errp), (err));
return;
}
- object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+ object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
+ &err);
if (err) {
error_propagate((errp), (err));
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
- qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
+ ARM_CPU_IRQ));
irq = qdev_get_gpio_in(DEVICE(&s->gic),
arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
- qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->gic),
arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
- qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
+ char *name;
+
+ name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
+ if (strcmp(name, boot_cpu)) {
+ /* Secondary CPUs start in PSCI powered-down state */
+ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
+ "start-powered-off", &error_abort);
+ } else {
+ s->boot_cpu_ptr = &s->rpu_cpu[i];
+ }
+
+ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
+ &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
+ &err);
+ if (err) {
+ error_propagate((errp), (err));
+ return;
+ }
+ }
+
+ if (!s->boot_cpu_ptr) {
+ error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu);
+ return;
}
for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
@@ -188,10 +235,16 @@
}
}
+static Property xlnx_zynqmp_props[] = {
+ DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ dc->props = xlnx_zynqmp_props;
dc->realize = xlnx_zynqmp_realize;
}
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
index b53c351..92eced9 100644
--- a/hw/core/sysbus.c
+++ b/hw/core/sysbus.c
@@ -281,19 +281,15 @@
static char *sysbus_get_fw_dev_path(DeviceState *dev)
{
SysBusDevice *s = SYS_BUS_DEVICE(dev);
- char path[40];
- int off;
-
- off = snprintf(path, sizeof(path), "%s", qdev_fw_name(dev));
if (s->num_mmio) {
- snprintf(path + off, sizeof(path) - off, "@"TARGET_FMT_plx,
- s->mmio[0].addr);
- } else if (s->num_pio) {
- snprintf(path + off, sizeof(path) - off, "@i%04x", s->pio[0]);
+ return g_strdup_printf("%s@" TARGET_FMT_plx, qdev_fw_name(dev),
+ s->mmio[0].addr);
}
-
- return g_strdup(path);
+ if (s->num_pio) {
+ return g_strdup_printf("%s@i%04x", qdev_fw_name(dev), s->pio[0]);
+ }
+ return g_strdup(qdev_fw_name(dev));
}
void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index b68263d..082cd93 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -403,6 +403,7 @@
static void pc_q35_2_3_machine_options(MachineClass *m)
{
pc_q35_2_4_machine_options(m);
+ m->no_floppy = 0;
m->alias = NULL;
SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
}
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 48c264b..ed84a37 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -64,20 +64,6 @@
#define SPI_IRQ 4
#define UART16550_IRQ 5
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
- CPUMBState *env = &cpu->env;
-
- env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
- /* setup pvr to match kernel setting */
- env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
- env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI;
- env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
- env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK;
- env->pvr.regs[4] = 0xc56b8000;
- env->pvr.regs[5] = 0xc56be000;
-}
-
static void
petalogix_ml605_init(MachineState *machine)
{
@@ -95,6 +81,13 @@
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ /* Use FPU but don't use floating point conversion and square
+ * root instructions
+ */
+ object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
+ object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
+ &error_abort);
+ object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
@@ -201,10 +194,15 @@
}
}
+ /* setup PVR to match kernel settings */
+ cpu->env.pvr.regs[4] = 0xc56b8000;
+ cpu->env.pvr.regs[5] = 0xc56be000;
+ cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
+
microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
- machine_cpu_reset);
+ NULL);
}
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index 84f6e74..0c2140c 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -51,18 +51,10 @@
#define ETHLITE_IRQ 1
#define UARTLITE_IRQ 3
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
- CPUMBState *env = &cpu->env;
-
- env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
-}
-
static void
petalogix_s3adsp1800_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
- const char *cpu_model = machine->cpu_model;
DeviceState *dev;
MicroBlazeCPU *cpu;
DriveInfo *dinfo;
@@ -73,11 +65,8 @@
qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory();
- /* init CPUs */
- if (cpu_model == NULL) {
- cpu_model = "microblaze";
- }
- cpu = cpu_mb_init(cpu_model);
+ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
+ object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL,
@@ -132,7 +121,7 @@
microblaze_load_kernel(cpu, ddr_base, ram_size,
machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
- machine_cpu_reset);
+ NULL);
}
static QEMUMachine petalogix_s3adsp1800_machine = {
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 5d272c8..231c35f 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -698,7 +698,6 @@
uint32_t val, int len)
{
pci_default_write_config(pci_dev, address, val, len);
- msix_write_config(pci_dev, address, val, len);
}
static int pci_ivshmem_init(PCIDevice *dev)
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index 1c55517..9bd360b 100644
--- a/hw/net/vhost_net.c
+++ b/hw/net/vhost_net.c
@@ -38,6 +38,7 @@
#include "standard-headers/linux/virtio_ring.h"
#include "hw/virtio/vhost.h"
#include "hw/virtio/virtio-bus.h"
+#include "hw/virtio/virtio-access.h"
struct vhost_net {
struct vhost_dev dev;
@@ -162,7 +163,7 @@
net->dev.vq_index = net->nc->queue_index;
r = vhost_dev_init(&net->dev, options->opaque,
- options->backend_type, options->force);
+ options->backend_type);
if (r < 0) {
goto fail;
}
@@ -187,16 +188,32 @@
return NULL;
}
-bool vhost_net_query(VHostNetState *net, VirtIODevice *dev)
-{
- return vhost_dev_query(&net->dev, dev);
-}
-
static void vhost_net_set_vq_index(struct vhost_net *net, int vq_index)
{
net->dev.vq_index = vq_index;
}
+static int vhost_net_set_vnet_endian(VirtIODevice *dev, NetClientState *peer,
+ bool set)
+{
+ int r = 0;
+
+ if (virtio_has_feature(dev, VIRTIO_F_VERSION_1) ||
+ (virtio_legacy_is_cross_endian(dev) && !virtio_is_big_endian(dev))) {
+ r = qemu_set_vnet_le(peer, set);
+ if (r) {
+ error_report("backend does not support LE vnet headers");
+ }
+ } else if (virtio_legacy_is_cross_endian(dev)) {
+ r = qemu_set_vnet_be(peer, set);
+ if (r) {
+ error_report("backend does not support BE vnet headers");
+ }
+ }
+
+ return r;
+}
+
static int vhost_net_start_one(struct vhost_net *net,
VirtIODevice *dev)
{
@@ -281,19 +298,6 @@
vhost_dev_disable_notifiers(&net->dev, dev);
}
-static bool vhost_net_device_endian_ok(VirtIODevice *vdev)
-{
-#ifdef TARGET_IS_BIENDIAN
-#ifdef HOST_WORDS_BIGENDIAN
- return virtio_is_big_endian(vdev);
-#else
- return !virtio_is_big_endian(vdev);
-#endif
-#else
- return true;
-#endif
-}
-
int vhost_net_start(VirtIODevice *dev, NetClientState *ncs,
int total_queues)
{
@@ -302,15 +306,14 @@
VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(vbus);
int r, e, i;
- if (!vhost_net_device_endian_ok(dev)) {
- error_report("vhost-net does not support cross-endian");
+ if (!k->set_guest_notifiers) {
+ error_report("binding does not support guest notifiers");
r = -ENOSYS;
goto err;
}
- if (!k->set_guest_notifiers) {
- error_report("binding does not support guest notifiers");
- r = -ENOSYS;
+ r = vhost_net_set_vnet_endian(dev, ncs[0].peer, true);
+ if (r < 0) {
goto err;
}
@@ -321,7 +324,7 @@
r = k->set_guest_notifiers(qbus->parent, total_queues * 2, true);
if (r < 0) {
error_report("Error binding guest notifier: %d", -r);
- goto err;
+ goto err_endian;
}
for (i = 0; i < total_queues; i++) {
@@ -343,6 +346,8 @@
fprintf(stderr, "vhost guest notifier cleanup failed: %d\n", e);
fflush(stderr);
}
+err_endian:
+ vhost_net_set_vnet_endian(dev, ncs[0].peer, false);
err:
return r;
}
@@ -365,6 +370,8 @@
fflush(stderr);
}
assert(r >= 0);
+
+ assert(vhost_net_set_vnet_endian(dev, ncs[0].peer, false) >= 0);
}
void vhost_net_cleanup(struct vhost_net *net)
@@ -412,11 +419,6 @@
return NULL;
}
-bool vhost_net_query(VHostNetState *net, VirtIODevice *dev)
-{
- return false;
-}
-
int vhost_net_start(VirtIODevice *dev,
NetClientState *ncs,
int total_queues)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 9281aa1..d728233 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -128,10 +128,6 @@
if (!n->vhost_started) {
int r, i;
- if (!vhost_net_query(get_vhost_net(nc->peer), vdev)) {
- return;
- }
-
/* Any packets outstanding? Purge them to avoid touching rings
* when vhost is running.
*/
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 8bcdf3e..104a0f5 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -2477,14 +2477,6 @@
}
};
-static void
-vmxnet3_write_config(PCIDevice *pci_dev, uint32_t addr, uint32_t val, int len)
-{
- pci_default_write_config(pci_dev, addr, val, len);
- msix_write_config(pci_dev, addr, val, len);
- msi_write_config(pci_dev, addr, val, len);
-}
-
static Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
DEFINE_PROP_END_OF_LIST(),
@@ -2503,7 +2495,6 @@
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
- c->config_write = vmxnet3_write_config,
dc->desc = "VMWare Paravirtualized Ethernet v3";
dc->reset = vmxnet3_qdev_reset;
dc->vmsd = &vmstate_vmxnet3;
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 91a5d97..51ba9e0 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -2407,13 +2407,6 @@
}
}
-static void
-megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
-{
- pci_default_write_config(pci, addr, val, len);
- msi_write_config(pci, addr, val, len);
-}
-
static Property megasas_properties_gen1[] = {
DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
MEGASAS_DEFAULT_SGE),
@@ -2516,7 +2509,6 @@
dc->vmsd = info->vmsd;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
dc->desc = info->desc;
- pc->config_write = megasas_write_config;
}
static const TypeInfo megasas_info = {
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 1941aa1..1c389c4 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -246,7 +246,7 @@
s->dev.backend_features = 0;
ret = vhost_dev_init(&s->dev, (void *)(uintptr_t)vhostfd,
- VHOST_BACKEND_TYPE_KERNEL, true);
+ VHOST_BACKEND_TYPE_KERNEL);
if (ret < 0) {
error_setg(errp, "vhost-scsi: vhost initialization failed: %s",
strerror(-ret));
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index c6148d3..9c71f31 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -1174,13 +1174,6 @@
}
};
-static void
-pvscsi_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
-{
- pci_default_write_config(pci, addr, val, len);
- msi_write_config(pci, addr, val, len);
-}
-
static Property pvscsi_properties[] = {
DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
DEFINE_PROP_END_OF_LIST(),
@@ -1202,7 +1195,6 @@
dc->vmsd = &vmstate_pvscsi;
dc->props = pvscsi_properties;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- k->config_write = pvscsi_write_config;
hc->unplug = pvscsi_hot_unplug;
hc->plug = pvscsi_hotplug;
}
diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c
index 3450c98..9b65a33 100644
--- a/hw/timer/i8254.c
+++ b/hw/timer/i8254.c
@@ -196,6 +196,12 @@
PITChannelState *s;
addr &= 3;
+
+ if (addr == 3) {
+ /* Mode/Command register is write only, read is ignored */
+ return 0;
+ }
+
s = &pit->channels[addr];
if (s->status_latched) {
s->status_latched = 0;
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 3204825..2e3ffc8 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -723,6 +723,12 @@
check_update_timer(s);
}
+ uint64_t now = qemu_clock_get_ns(rtc_clock);
+ if (now < s->next_periodic_time ||
+ now > (s->next_periodic_time + get_max_clock_jump())) {
+ periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
+ }
+
#ifdef TARGET_I386
if (version_id >= 2) {
if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 2d6c27a..a6dcc79 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -17,9 +17,11 @@
#include "hw/hw.h"
#include "qemu/atomic.h"
#include "qemu/range.h"
+#include "qemu/error-report.h"
#include <linux/vhost.h>
#include "exec/address-spaces.h"
#include "hw/virtio/virtio-bus.h"
+#include "hw/virtio/virtio-access.h"
#include "migration/migration.h"
static struct vhost_log *vhost_log;
@@ -689,6 +691,27 @@
/* FIXME: implement */
}
+static int vhost_virtqueue_set_vring_endian_legacy(struct vhost_dev *dev,
+ bool is_big_endian,
+ int vhost_vq_index)
+{
+ struct vhost_vring_state s = {
+ .index = vhost_vq_index,
+ .num = is_big_endian
+ };
+
+ if (!dev->vhost_ops->vhost_call(dev, VHOST_SET_VRING_ENDIAN, &s)) {
+ return 0;
+ }
+
+ if (errno == ENOTTY) {
+ error_report("vhost does not support cross-endian");
+ return -ENOSYS;
+ }
+
+ return -errno;
+}
+
static int vhost_virtqueue_start(struct vhost_dev *dev,
struct VirtIODevice *vdev,
struct vhost_virtqueue *vq,
@@ -719,6 +742,16 @@
return -errno;
}
+ if (!virtio_has_feature(vdev, VIRTIO_F_VERSION_1) &&
+ virtio_legacy_is_cross_endian(vdev)) {
+ r = vhost_virtqueue_set_vring_endian_legacy(dev,
+ virtio_is_big_endian(vdev),
+ vhost_vq_index);
+ if (r) {
+ return -errno;
+ }
+ }
+
s = l = virtio_queue_get_desc_size(vdev, idx);
a = virtio_queue_get_desc_addr(vdev, idx);
vq->desc = cpu_physical_memory_map(a, &l, 0);
@@ -789,8 +822,9 @@
struct vhost_virtqueue *vq,
unsigned idx)
{
+ int vhost_vq_index = idx - dev->vq_index;
struct vhost_vring_state state = {
- .index = idx - dev->vq_index
+ .index = vhost_vq_index,
};
int r;
assert(idx >= dev->vq_index && idx < dev->vq_index + dev->nvqs);
@@ -801,6 +835,20 @@
}
virtio_queue_set_last_avail_idx(vdev, idx, state.num);
virtio_queue_invalidate_signalled_used(vdev, idx);
+
+ /* In the cross-endian case, we need to reset the vring endianness to
+ * native as legacy devices expect so by default.
+ */
+ if (!virtio_has_feature(vdev, VIRTIO_F_VERSION_1) &&
+ virtio_legacy_is_cross_endian(vdev)) {
+ r = vhost_virtqueue_set_vring_endian_legacy(dev,
+ !virtio_is_big_endian(vdev),
+ vhost_vq_index);
+ if (r < 0) {
+ error_report("failed to reset vring endianness");
+ }
+ }
+
assert (r >= 0);
cpu_physical_memory_unmap(vq->ring, virtio_queue_get_ring_size(vdev, idx),
0, virtio_queue_get_ring_size(vdev, idx));
@@ -853,7 +901,7 @@
}
int vhost_dev_init(struct vhost_dev *hdev, void *opaque,
- VhostBackendType backend_type, bool force)
+ VhostBackendType backend_type)
{
uint64_t features;
int i, r;
@@ -916,7 +964,6 @@
hdev->started = false;
hdev->memory_changed = false;
memory_listener_register(&hdev->memory_listener, &address_space_memory);
- hdev->force = force;
return 0;
fail_vq:
while (--i >= 0) {
@@ -944,17 +991,6 @@
hdev->vhost_ops->vhost_backend_cleanup(hdev);
}
-bool vhost_dev_query(struct vhost_dev *hdev, VirtIODevice *vdev)
-{
- BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
- VirtioBusState *vbus = VIRTIO_BUS(qbus);
- VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(vbus);
-
- return !k->query_guest_notifiers ||
- k->query_guest_notifiers(qbus->parent) ||
- hdev->force;
-}
-
/* Stop processing guest IO notifications in qemu.
* Start processing them in vhost in kernel.
*/
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index c633248..a608a26 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -95,10 +95,4 @@
/* in gdbstub-xml.c, generated by scripts/feature_to_c.sh */
extern const char *const xml_builtin[][2];
-/* Command line option defining whether semihosting should go via gdb or not */
-extern int semihosting_target;
-#define SEMIHOSTING_TARGET_AUTO 0
-#define SEMIHOSTING_TARGET_NATIVE 1
-#define SEMIHOSTING_TARGET_GDB 2
-
#endif
diff --git a/include/exec/semihost.h b/include/exec/semihost.h
new file mode 100644
index 0000000..5980939
--- /dev/null
+++ b/include/exec/semihost.h
@@ -0,0 +1,62 @@
+/*
+ * Semihosting support
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SEMIHOST_H
+#define SEMIHOST_H
+
+typedef enum SemihostingTarget {
+ SEMIHOSTING_TARGET_AUTO = 0,
+ SEMIHOSTING_TARGET_NATIVE,
+ SEMIHOSTING_TARGET_GDB
+} SemihostingTarget;
+
+#ifdef CONFIG_USER_ONLY
+static inline bool semihosting_enabled(void)
+{
+ return true;
+}
+
+static inline SemihostingTarget semihosting_get_target(void)
+{
+ return SEMIHOSTING_TARGET_AUTO;
+}
+
+static inline const char *semihosting_get_arg(int i)
+{
+ return NULL;
+}
+
+static inline int semihosting_get_argc(void)
+{
+ return 0;
+}
+
+static inline const char *semihosting_get_cmdline(void)
+{
+ return NULL;
+}
+#else
+bool semihosting_enabled(void);
+SemihostingTarget semihosting_get_target(void);
+const char *semihosting_get_arg(int i);
+int semihosting_get_argc(void);
+const char *semihosting_get_cmdline(void);
+#endif
+
+#endif
diff --git a/include/hw/arm/fdt.h b/include/hw/arm/fdt.h
new file mode 100644
index 0000000..c3d5015
--- /dev/null
+++ b/include/hw/arm/fdt.h
@@ -0,0 +1,34 @@
+/*
+ *
+ * Copyright (c) 2015 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Define macros useful when building ARM device tree nodes
+ */
+
+#ifndef QEMU_ARM_FDT_H
+#define QEMU_ARM_FDT_H
+
+#define GIC_FDT_IRQ_TYPE_SPI 0
+#define GIC_FDT_IRQ_TYPE_PPI 1
+
+#define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
+#define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
+#define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
+#define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
+
+#define GIC_FDT_IRQ_PPI_CPU_START 8
+#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
+
+#endif
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 79c2b0b..c379632 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -27,7 +27,8 @@
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
TYPE_XLNX_ZYNQMP)
-#define XLNX_ZYNQMP_NUM_CPUS 4
+#define XLNX_ZYNQMP_NUM_APU_CPUS 4
+#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
#define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_NUM_UARTS 2
@@ -47,11 +48,15 @@
DeviceState parent_obj;
/*< public >*/
- ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
+ ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
+ ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+
+ char *boot_cpu;
+ ARMCPU *boot_cpu_ptr;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index 84f170e..dd51050 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -51,7 +51,6 @@
bool log_enabled;
unsigned long long log_size;
Error *migration_blocker;
- bool force;
bool memory_changed;
hwaddr mem_changed_start_addr;
hwaddr mem_changed_end_addr;
@@ -61,7 +60,7 @@
};
int vhost_dev_init(struct vhost_dev *hdev, void *opaque,
- VhostBackendType backend_type, bool force);
+ VhostBackendType backend_type);
void vhost_dev_cleanup(struct vhost_dev *hdev);
bool vhost_dev_query(struct vhost_dev *hdev, VirtIODevice *vdev);
int vhost_dev_start(struct vhost_dev *hdev, VirtIODevice *vdev);
diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h
index ee28c21..cee5dd7 100644
--- a/include/hw/virtio/virtio-access.h
+++ b/include/hw/virtio/virtio-access.h
@@ -32,6 +32,19 @@
#endif
}
+static inline bool virtio_legacy_is_cross_endian(VirtIODevice *vdev)
+{
+#ifdef TARGET_IS_BIENDIAN
+#ifdef HOST_WORDS_BIGENDIAN
+ return !virtio_is_big_endian(vdev);
+#else
+ return virtio_is_big_endian(vdev);
+#endif
+#else
+ return false;
+#endif
+}
+
static inline uint16_t virtio_lduw_phys(VirtIODevice *vdev, hwaddr pa)
{
if (virtio_access_is_big_endian(vdev)) {
diff --git a/include/net/net.h b/include/net/net.h
index e66ca03..4306252 100644
--- a/include/net/net.h
+++ b/include/net/net.h
@@ -55,6 +55,8 @@
typedef void (UsingVnetHdr)(NetClientState *, bool);
typedef void (SetOffload)(NetClientState *, int, int, int, int, int);
typedef void (SetVnetHdrLen)(NetClientState *, int);
+typedef int (SetVnetLE)(NetClientState *, bool);
+typedef int (SetVnetBE)(NetClientState *, bool);
typedef struct NetClientInfo {
NetClientOptionsKind type;
@@ -73,6 +75,8 @@
UsingVnetHdr *using_vnet_hdr;
SetOffload *set_offload;
SetVnetHdrLen *set_vnet_hdr_len;
+ SetVnetLE *set_vnet_le;
+ SetVnetBE *set_vnet_be;
} NetClientInfo;
struct NetClientState {
@@ -139,6 +143,8 @@
void qemu_set_offload(NetClientState *nc, int csum, int tso4, int tso6,
int ecn, int ufo);
void qemu_set_vnet_hdr_len(NetClientState *nc, int len);
+int qemu_set_vnet_le(NetClientState *nc, bool is_le);
+int qemu_set_vnet_be(NetClientState *nc, bool is_be);
void qemu_macaddr_default_if_unset(MACAddr *macaddr);
int qemu_show_nic_models(const char *arg, const char *const *models);
void qemu_check_nic_model(NICInfo *nd, const char *model);
diff --git a/include/net/vhost_net.h b/include/net/vhost_net.h
index 9eb493e..840d4b1 100644
--- a/include/net/vhost_net.h
+++ b/include/net/vhost_net.h
@@ -11,12 +11,10 @@
VhostBackendType backend_type;
NetClientState *net_backend;
void *opaque;
- bool force;
} VhostNetOptions;
struct vhost_net *vhost_net_init(VhostNetOptions *options);
-bool vhost_net_query(VHostNetState *net, VirtIODevice *dev);
int vhost_net_start(VirtIODevice *dev, NetClientState *ncs, int total_queues);
void vhost_net_stop(VirtIODevice *dev, NetClientState *ncs, int total_queues);
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index e5bd494..9e4f90f 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -787,6 +787,15 @@
return 1000000000LL;
}
+static inline int64_t get_max_clock_jump(void)
+{
+ /* This should be small enough to prevent excessive interrupts from being
+ * generated by the RTC on clock jumps, but large enough to avoid frequent
+ * unnecessary resets in idle VMs.
+ */
+ return 60 * get_ticks_per_sec();
+}
+
/*
* Low level clock functions
*/
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 0304aa7..df80951 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -126,7 +126,6 @@
extern int graphic_rotate;
extern int no_quit;
extern int no_shutdown;
-extern int semihosting_enabled;
extern int old_param;
extern int boot_menu;
extern bool boot_strict;
diff --git a/linux-headers/linux/vhost.h b/linux-headers/linux/vhost.h
index c656f61..ead86db 100644
--- a/linux-headers/linux/vhost.h
+++ b/linux-headers/linux/vhost.h
@@ -103,6 +103,20 @@
/* Get accessor: reads index, writes value in num */
#define VHOST_GET_VRING_BASE _IOWR(VHOST_VIRTIO, 0x12, struct vhost_vring_state)
+/* Set the vring byte order in num. Valid values are VHOST_VRING_LITTLE_ENDIAN
+ * or VHOST_VRING_BIG_ENDIAN (other values return -EINVAL).
+ * The byte order cannot be changed while the device is active: trying to do so
+ * returns -EBUSY.
+ * This is a legacy only API that is simply ignored when VIRTIO_F_VERSION_1 is
+ * set.
+ * Not all kernel configurations support this ioctl, but all configurations that
+ * support SET also support GET.
+ */
+#define VHOST_VRING_LITTLE_ENDIAN 0
+#define VHOST_VRING_BIG_ENDIAN 1
+#define VHOST_SET_VRING_ENDIAN _IOW(VHOST_VIRTIO, 0x13, struct vhost_vring_state)
+#define VHOST_GET_VRING_ENDIAN _IOW(VHOST_VIRTIO, 0x14, struct vhost_vring_state)
+
/* The following ioctls use eventfd file descriptors to signal and poll
* for events. */
diff --git a/net/net.c b/net/net.c
index 25c2ef3..6dbd61a 100644
--- a/net/net.c
+++ b/net/net.c
@@ -510,6 +510,24 @@
nc->info->set_vnet_hdr_len(nc, len);
}
+int qemu_set_vnet_le(NetClientState *nc, bool is_le)
+{
+ if (!nc || !nc->info->set_vnet_le) {
+ return -ENOSYS;
+ }
+
+ return nc->info->set_vnet_le(nc, is_le);
+}
+
+int qemu_set_vnet_be(NetClientState *nc, bool is_be)
+{
+ if (!nc || !nc->info->set_vnet_be) {
+ return -ENOSYS;
+ }
+
+ return nc->info->set_vnet_be(nc, is_be);
+}
+
int qemu_can_send_packet(NetClientState *sender)
{
int vm_running = runstate_is_running();
diff --git a/net/tap-aix.c b/net/tap-aix.c
index 18fdbf3..e84fc39 100644
--- a/net/tap-aix.c
+++ b/net/tap-aix.c
@@ -55,6 +55,16 @@
{
}
+int tap_fd_set_vnet_le(int fd, int is_le)
+{
+ return -EINVAL;
+}
+
+int tap_fd_set_vnet_be(int fd, int is_be)
+{
+ return -EINVAL;
+}
+
void tap_fd_set_offload(int fd, int csum, int tso4,
int tso6, int ecn, int ufo)
{
diff --git a/net/tap-bsd.c b/net/tap-bsd.c
index 5889920..7028d9b 100644
--- a/net/tap-bsd.c
+++ b/net/tap-bsd.c
@@ -196,6 +196,16 @@
{
}
+int tap_fd_set_vnet_le(int fd, int is_le)
+{
+ return -EINVAL;
+}
+
+int tap_fd_set_vnet_be(int fd, int is_be)
+{
+ return -EINVAL;
+}
+
void tap_fd_set_offload(int fd, int csum, int tso4,
int tso6, int ecn, int ufo)
{
diff --git a/net/tap-haiku.c b/net/tap-haiku.c
index d18590c..2e738ec 100644
--- a/net/tap-haiku.c
+++ b/net/tap-haiku.c
@@ -55,6 +55,16 @@
{
}
+int tap_fd_set_vnet_le(int fd, int is_le)
+{
+ return -EINVAL;
+}
+
+int tap_fd_set_vnet_be(int fd, int is_be)
+{
+ return -EINVAL;
+}
+
void tap_fd_set_offload(int fd, int csum, int tso4,
int tso6, int ecn, int ufo)
{
diff --git a/net/tap-linux.c b/net/tap-linux.c
index 6c3caef..394f2a6 100644
--- a/net/tap-linux.c
+++ b/net/tap-linux.c
@@ -198,6 +198,40 @@
}
}
+int tap_fd_set_vnet_le(int fd, int is_le)
+{
+ int arg = is_le ? 1 : 0;
+
+ if (!ioctl(fd, TUNSETVNETLE, &arg)) {
+ return 0;
+ }
+
+ /* Check if our kernel supports TUNSETVNETLE */
+ if (errno == EINVAL) {
+ return -errno;
+ }
+
+ error_report("TUNSETVNETLE ioctl() failed: %s.\n", strerror(errno));
+ abort();
+}
+
+int tap_fd_set_vnet_be(int fd, int is_be)
+{
+ int arg = is_be ? 1 : 0;
+
+ if (!ioctl(fd, TUNSETVNETBE, &arg)) {
+ return 0;
+ }
+
+ /* Check if our kernel supports TUNSETVNETBE */
+ if (errno == EINVAL) {
+ return -errno;
+ }
+
+ error_report("TUNSETVNETBE ioctl() failed: %s.\n", strerror(errno));
+ abort();
+}
+
void tap_fd_set_offload(int fd, int csum, int tso4,
int tso6, int ecn, int ufo)
{
diff --git a/net/tap-linux.h b/net/tap-linux.h
index 1cf35d4..01dc6f8 100644
--- a/net/tap-linux.h
+++ b/net/tap-linux.h
@@ -30,6 +30,8 @@
#define TUNGETVNETHDRSZ _IOR('T', 215, int)
#define TUNSETVNETHDRSZ _IOW('T', 216, int)
#define TUNSETQUEUE _IOW('T', 217, int)
+#define TUNSETVNETLE _IOW('T', 220, int)
+#define TUNSETVNETBE _IOW('T', 222, int)
#endif
diff --git a/net/tap-solaris.c b/net/tap-solaris.c
index 90b2fd1..0f60f78 100644
--- a/net/tap-solaris.c
+++ b/net/tap-solaris.c
@@ -223,6 +223,16 @@
{
}
+int tap_fd_set_vnet_le(int fd, int is_le)
+{
+ return -EINVAL;
+}
+
+int tap_fd_set_vnet_be(int fd, int is_be)
+{
+ return -EINVAL;
+}
+
void tap_fd_set_offload(int fd, int csum, int tso4,
int tso6, int ecn, int ufo)
{
diff --git a/net/tap-win32.c b/net/tap-win32.c
index f6fc961..625d53c 100644
--- a/net/tap-win32.c
+++ b/net/tap-win32.c
@@ -688,6 +688,16 @@
{
}
+int tap_fd_set_vnet_le(int fd, int is_le)
+{
+ return -EINVAL;
+}
+
+int tap_fd_set_vnet_be(int fd, int is_be)
+{
+ return -EINVAL;
+}
+
static void tap_using_vnet_hdr(NetClientState *nc, bool using_vnet_hdr)
{
}
diff --git a/net/tap.c b/net/tap.c
index aa8b3f5..bd01590 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -266,6 +266,20 @@
s->using_vnet_hdr = using_vnet_hdr;
}
+static int tap_set_vnet_le(NetClientState *nc, bool is_le)
+{
+ TAPState *s = DO_UPCAST(TAPState, nc, nc);
+
+ return tap_fd_set_vnet_le(s->fd, is_le);
+}
+
+static int tap_set_vnet_be(NetClientState *nc, bool is_be)
+{
+ TAPState *s = DO_UPCAST(TAPState, nc, nc);
+
+ return tap_fd_set_vnet_be(s->fd, is_be);
+}
+
static void tap_set_offload(NetClientState *nc, int csum, int tso4,
int tso6, int ecn, int ufo)
{
@@ -332,6 +346,8 @@
.using_vnet_hdr = tap_using_vnet_hdr,
.set_offload = tap_set_offload,
.set_vnet_hdr_len = tap_set_vnet_hdr_len,
+ .set_vnet_le = tap_set_vnet_le,
+ .set_vnet_be = tap_set_vnet_be,
};
static TAPState *net_tap_fd_init(NetClientState *peer,
@@ -646,7 +662,6 @@
options.backend_type = VHOST_BACKEND_TYPE_KERNEL;
options.net_backend = &s->nc;
- options.force = tap->has_vhostforce && tap->vhostforce;
if (tap->has_vhostfd || tap->has_vhostfds) {
vhostfd = monitor_fd_param(cur_mon, vhostfdname, &err);
diff --git a/net/tap_int.h b/net/tap_int.h
index d12a409..2378021 100644
--- a/net/tap_int.h
+++ b/net/tap_int.h
@@ -40,6 +40,8 @@
int tap_probe_has_ufo(int fd);
void tap_fd_set_offload(int fd, int csum, int tso4, int tso6, int ecn, int ufo);
void tap_fd_set_vnet_hdr_len(int fd, int len);
+int tap_fd_set_vnet_le(int fd, int vnet_is_le);
+int tap_fd_set_vnet_be(int fd, int vnet_is_be);
int tap_fd_enable(int fd);
int tap_fd_disable(int fd);
int tap_fd_get_ifname(int fd, char *ifname);
diff --git a/net/vhost-user.c b/net/vhost-user.c
index 3930741..b51bc04 100644
--- a/net/vhost-user.c
+++ b/net/vhost-user.c
@@ -50,7 +50,6 @@
options.backend_type = VHOST_BACKEND_TYPE_USER;
options.net_backend = &s->nc;
options.opaque = s->chr;
- options.force = true;
s->vhost_net = vhost_net_init(&options);
diff --git a/qemu-options.hx b/qemu-options.hx
index 39304d7..d1712f5 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -3351,14 +3351,25 @@
Enable semihosting mode (ARM, M68K, Xtensa only).
ETEXI
DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semihosting_config,
- "-semihosting-config [enable=on|off,]target=native|gdb|auto semihosting configuration\n",
+ "-semihosting-config [enable=on|off][,target=native|gdb|auto][,arg=str[,...]]\n" \
+ " semihosting configuration\n",
QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32)
STEXI
-@item -semihosting-config [enable=on|off,]target=native|gdb|auto
+@item -semihosting-config [enable=on|off][,target=native|gdb|auto][,arg=str[,...]]
@findex -semihosting-config
-Enable semihosting and define where the semihosting calls will be addressed,
-to QEMU (@code{native}) or to GDB (@code{gdb}). The default is @code{auto}, which means
-@code{gdb} during debug sessions and @code{native} otherwise (ARM, M68K, Xtensa only).
+Enable and configure semihosting (ARM, M68K, Xtensa only).
+@table @option
+@item target=@code{native|gdb|auto}
+Defines where the semihosting calls will be addressed, to QEMU (@code{native})
+or to GDB (@code{gdb}). The default is @code{auto}, which means @code{gdb}
+during debug sessions and @code{native} otherwise.
+@item arg=@var{str1},arg=@var{str2},...
+Allows the user to pass input arguments, and can be used multiple times to build
+up a list. The old-style @code{-kernel}/@code{-append} method of passing a
+command line is still supported for backward compatibility. If both the
+@code{--semihosting-config arg} and the @code{-kernel}/@code{-append} are
+specified, the former is passed to semihosting as it always takes precedence.
+@end table
ETEXI
DEF("old-param", 0, QEMU_OPTION_old_param,
"-old-param old param mode\n", QEMU_ARCH_ARM)
diff --git a/qemu-timer.c b/qemu-timer.c
index 5741f0d..aa6757e 100644
--- a/qemu-timer.c
+++ b/qemu-timer.c
@@ -573,7 +573,7 @@
now = get_clock_realtime();
last = clock->last;
clock->last = now;
- if (now < last) {
+ if (now < last || now > (last + get_max_clock_jump())) {
notifier_list_notify(&clock->reset_notifiers, &now);
}
return now;
diff --git a/qga/channel-win32.c b/qga/channel-win32.c
index 0d5e5f5..04fa5e4 100644
--- a/qga/channel-win32.c
+++ b/qga/channel-win32.c
@@ -306,7 +306,7 @@
OPEN_EXISTING,
FILE_FLAG_NO_BUFFERING | FILE_FLAG_OVERLAPPED, NULL);
if (c->handle == INVALID_HANDLE_VALUE) {
- g_critical("error opening path");
+ g_critical("error opening path %s", newpath);
return false;
}
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
index 3ef0549..d0aaec7 100644
--- a/qga/commands-win32.c
+++ b/qga/commands-win32.c
@@ -721,6 +721,7 @@
}
if (!vss_init(true)) {
+ g_debug("vss_init failed, vss commands are going to be disabled");
const char *list[] = {
"guest-get-fsinfo", "guest-fsfreeze-status",
"guest-fsfreeze-freeze", "guest-fsfreeze-thaw", NULL};
diff --git a/qga/installer/qemu-ga.wxs b/qga/installer/qemu-ga.wxs
new file mode 100644
index 0000000..2c43f1b
--- /dev/null
+++ b/qga/installer/qemu-ga.wxs
@@ -0,0 +1,145 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Wix xmlns="http://schemas.microsoft.com/wix/2006/wi">
+ <?ifndef env.QEMU_GA_VERSION ?>
+ <?error Environment variable QEMU_GA_VERSION undefined?>
+ <?endif?>
+
+ <?ifndef env.QEMU_GA_DISTRO ?>
+ <?error Environment variable QEMU_GA_DISTRO undefined?>
+ <?endif?>
+
+ <?ifndef env.QEMU_GA_MANUFACTURER ?>
+ <?error Environment variable QEMU_GA_MANUFACTURER undefined?>
+ <?endif?>
+
+ <?ifndef var.Arch?>
+ <?error Define Arch to 32 or 64?>
+ <?endif?>
+
+ <?ifndef var.Mingw_bin?>
+ <?if $(var.Arch) = "64"?>
+ <?define Mingw_bin=/usr/x86_64-w64-mingw32/sys-root/mingw/bin ?>
+ <?endif?>
+ <?if $(var.Arch) = "32"?>
+ <?define Mingw_bin=/usr/i686-w64-mingw32/sys-root/mingw/bin ?>
+ <?endif?>
+ <?endif?>
+
+ <?if $(var.Arch) = "64"?>
+ <?define ArchLib=libgcc_s_seh-1.dll?>
+ <?define GaProgramFilesFolder="ProgramFiles64Folder" ?>
+ <?endif?>
+
+ <?if $(var.Arch) = "32"?>
+ <?define ArchLib=libgcc_s_sjlj-1.dll?>
+ <?define GaProgramFilesFolder="ProgramFilesFolder" ?>
+ <?endif?>
+
+ <?ifndef var.ArchLib ?>
+ <?error Unexpected Arch value $(var.Arch)?>
+ <?endif?>
+
+ <Product
+ Name="QEMU guest agent"
+ Id="*"
+ UpgradeCode="{EB6B8302-C06E-4bec-ADAC-932C68A3A98D}"
+ Manufacturer="$(env.QEMU_GA_MANUFACTURER)"
+ Version="$(env.QEMU_GA_VERSION)"
+ Language="1033">
+ <?if $(var.Arch) = 32 ?>
+ <Condition Message="Error: 32-bit version of Qemu GA can not be installed on 64-bit Windows.">NOT VersionNT64</Condition>
+ <?endif?>
+ <Package
+ Manufacturer="$(env.QEMU_GA_MANUFACTURER)"
+ InstallerVersion="200"
+ Languages="1033"
+ Compressed="yes"
+ InstallScope="perMachine"
+ />
+ <Media Id="1" Cabinet="qemu_ga.$(env.QEMU_GA_VERSION).cab" EmbedCab="yes" />
+ <Property Id="WHSLogo">1</Property>
+ <Property Id="PREVIOUSVERSIONSINSTALLED" />
+ <Upgrade Id="{EB6B8302-C06E-4bec-ADAC-932C68A3A98D}">
+ <UpgradeVersion
+ Minimum="1.0.0.0" Maximum="$(env.QEMU_GA_VERSION)"
+ Property="PREVIOUSVERSIONSINSTALLED"
+ IncludeMinimum="yes" IncludeMaximum="no" />
+ </Upgrade>
+
+ <Directory Id="TARGETDIR" Name="SourceDir">
+ <Directory Id="$(var.GaProgramFilesFolder)" Name="QEMU Guest Agent">
+ <Directory Id="qemu_ga_directory" Name="Qemu-ga">
+ <Component Id="qemu_ga" Guid="{908B7199-DE2A-4dc6-A8D0-27A5AE444FEA}">
+ <File Id="qemu_ga.exe" Name="qemu-ga.exe" Source="../../qemu-ga.exe" KeyPath="yes" DiskId="1"/>
+ <?ifdef var.InstallVss ?>
+ <File Id="qga_vss.dll" Name="qga-vss.dll" Source="../vss-win32/qga-vss.dll" KeyPath="no" DiskId="1"/>
+ <File Id="qga_vss.tlb" Name="qga-vss.tlb" Source="../vss-win32/qga-vss.tlb" KeyPath="no" DiskId="1"/>
+ <?endif?>
+ <File Id="iconv.dll" Name="iconv.dll" Source="$(var.Mingw_bin)/iconv.dll" KeyPath="no" DiskId="1"/>
+ <File Id="libgcc_arch_lib" Name="$(var.ArchLib)" Source="$(var.Mingw_bin)/$(var.ArchLib)" KeyPath="no" DiskId="1"/>
+ <File Id="libglib_2.0_0.dll" Name="libglib-2.0-0.dll" Source="$(var.Mingw_bin)/libglib-2.0-0.dll" KeyPath="no" DiskId="1"/>
+ <File Id="libintl_8.dll" Name="libintl-8.dll" Source="$(var.Mingw_bin)/libintl-8.dll" KeyPath="no" DiskId="1"/>
+ <File Id="libssp_0.dll" Name="libssp-0.dll" Source="$(var.Mingw_bin)/libssp-0.dll" KeyPath="no" DiskId="1"/>
+ <File Id="libwinpthread_1.dll" Name="libwinpthread-1.dll" Source="$(var.Mingw_bin)/libwinpthread-1.dll" KeyPath="no" DiskId="1"/>
+ <ServiceInstall
+ Id="ServiceInstaller"
+ Type="ownProcess"
+ Vital="yes"
+ Name="QEMU-GA"
+ DisplayName="QEMU Guest Agent"
+ Description="QEMU Guest Agent"
+ Start="auto"
+ Account="LocalSystem"
+ ErrorControl="ignore"
+ Interactive="no"
+ Arguments="-d"
+ >
+ </ServiceInstall>
+ <ServiceControl Id="StartService" Start="install" Stop="both" Remove="uninstall" Name="QEMU-GA" Wait="no" />
+ </Component>
+
+ <Component Id="registry_entries" Guid="d075d109-51ca-11e3-9f8b-000c29858960">
+ <RegistryKey Root="HKLM"
+ Key="Software\$(env.QEMU_GA_MANUFACTURER)\$(env.QEMU_GA_DISTRO)\Tools\QemuGA">
+ <RegistryValue Type="string" Name="ProductID" Value="fb0a0d66-c7fb-4e2e-a16b-c4a3bfe8d13b" />
+ <RegistryValue Type="string" Name="Version" Value="$(env.QEMU_GA_VERSION)" />
+ </RegistryKey>
+ </Component>
+ </Directory>
+ </Directory>
+ </Directory>
+
+ <Property Id="cmd" Value="cmd.exe"/>
+
+ <?ifdef var.InstallVss ?>
+ <CustomAction Id="RegisterCom"
+ ExeCommand='/c "[qemu_ga_directory]qemu-ga.exe" -s vss-install'
+ Execute="deferred"
+ Property="cmd"
+ Impersonate="no"
+ Return="check"
+ >
+ </CustomAction>
+ <CustomAction Id="UnRegisterCom"
+ ExeCommand='/c "[qemu_ga_directory]qemu-ga.exe" -s vss-uninstall'
+ Execute="deferred"
+ Property="cmd"
+ Impersonate="no"
+ Return="check"
+ ></CustomAction>
+ <?endif?>
+
+ <Feature Id="QEMUFeature" Title="QEMU Guest Agent" Level="1">
+ <ComponentRef Id="qemu_ga" />
+ <ComponentRef Id="registry_entries" />
+ </Feature>
+
+ <InstallExecuteSequence>
+ <RemoveExistingProducts Before="InstallInitialize" />
+ <?ifdef var.InstallVss ?>
+ <Custom Action="RegisterCom" After="InstallServices">NOT Installed</Custom>
+ <Custom Action="UnRegisterCom" After="StopServices">Installed</Custom>
+ <?endif?>
+ </InstallExecuteSequence>
+ </Product>
+</Wix>
diff --git a/qga/main.c b/qga/main.c
index 9939a2b..7e1e438 100644
--- a/qga/main.c
+++ b/qga/main.c
@@ -211,7 +211,7 @@
" -V, --version print version information and exit\n"
" -d, --daemonize become a daemon\n"
#ifdef _WIN32
-" -s, --service service commands: install, uninstall\n"
+" -s, --service service commands: install, uninstall, vss-install, vss-uninstall\n"
#endif
" -b, --blacklist comma-separated list of RPCs to disable (no spaces, \"?\"\n"
" to list available RPCs)\n"
@@ -1036,6 +1036,14 @@
} else if (strcmp(service, "uninstall") == 0) {
ga_uninstall_vss_provider();
return ga_uninstall_service();
+ } else if (strcmp(service, "vss-install") == 0) {
+ if (ga_install_vss_provider()) {
+ return EXIT_FAILURE;
+ }
+ return EXIT_SUCCESS;
+ } else if (strcmp(service, "vss-uninstall") == 0) {
+ ga_uninstall_vss_provider();
+ return EXIT_SUCCESS;
} else {
printf("Unknown service command.\n");
return EXIT_FAILURE;
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index a8b83e6..74a67e9 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -27,6 +27,7 @@
#include <time.h>
#include "cpu.h"
+#include "exec/semihost.h"
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
@@ -440,10 +441,7 @@
input_size = arg1;
/* Compute the size of the output string. */
#if !defined(CONFIG_USER_ONLY)
- output_size = strlen(ts->boot_info->kernel_filename)
- + 1 /* Separating space. */
- + strlen(ts->boot_info->kernel_cmdline)
- + 1; /* Terminating null byte. */
+ output_size = strlen(semihosting_get_cmdline()) + 1;
#else
unsigned int i;
@@ -474,9 +472,7 @@
/* Copy the command-line arguments. */
#if !defined(CONFIG_USER_ONLY)
- pstrcpy(output_buffer, output_size, ts->boot_info->kernel_filename);
- pstrcat(output_buffer, output_size, " ");
- pstrcat(output_buffer, output_size, ts->boot_info->kernel_cmdline);
+ pstrcpy(output_buffer, output_size, semihosting_get_cmdline());
#else
if (output_size == 1) {
/* Empty command-line. */
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 072aa9b..3cbc4a0 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -105,6 +105,8 @@
/* CPU has memory protection unit */
bool has_mpu;
+ /* PMSAv7 MPU number of supported regions */
+ uint32_t pmsav7_dregion;
/* PSCI conduit used to invoke PSCI methods
* 0 - disabled, 1 - smc, 2 - hvc
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7496983..b3d07ac 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -55,7 +55,7 @@
ARMCPRegInfo *ri = value;
ARMCPU *cpu = opaque;
- if (ri->type & ARM_CP_SPECIAL) {
+ if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
return;
}
@@ -457,6 +457,9 @@
static Property arm_cpu_has_mpu_property =
DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
+static Property arm_cpu_pmsav7_dregion_property =
+ DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
+
static void arm_cpu_post_init(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -488,6 +491,11 @@
if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
&error_abort);
+ if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+ qdev_property_add_static(DEVICE(obj),
+ &arm_cpu_pmsav7_dregion_property,
+ &error_abort);
+ }
}
}
@@ -580,6 +588,22 @@
unset_feature(env, ARM_FEATURE_MPU);
}
+ if (arm_feature(env, ARM_FEATURE_MPU) &&
+ arm_feature(env, ARM_FEATURE_V7)) {
+ uint32_t nr = cpu->pmsav7_dregion;
+
+ if (nr > 0xff) {
+ error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
+ return;
+ }
+
+ if (nr) {
+ env->pmsav7.drbar = g_new0(uint32_t, nr);
+ env->pmsav7.drsr = g_new0(uint32_t, nr);
+ env->pmsav7.dracr = g_new0(uint32_t, nr);
+ }
+ }
+
register_cp_regs_for_features(cpu);
arm_cpu_register_gdb_regs_for_features(cpu);
@@ -812,6 +836,15 @@
cpu->midr = 0x410fc231;
}
+static void cortex_m4_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fc240; /* r0p0 */
+}
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
@@ -823,6 +856,43 @@
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
}
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
+ /* Dummy the TCM region regs for the moment */
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ REGINFO_SENTINEL
+};
+
+static void cortex_r5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
+ set_feature(&cpu->env, ARM_FEATURE_MPU);
+ cpu->midr = 0x411fc153; /* r1p3 */
+ cpu->id_pfr0 = 0x0131;
+ cpu->id_pfr1 = 0x001;
+ cpu->id_dfr0 = 0x010400;
+ cpu->id_afr0 = 0x0;
+ cpu->id_mmfr0 = 0x0210030;
+ cpu->id_mmfr1 = 0x00000000;
+ cpu->id_mmfr2 = 0x01200000;
+ cpu->id_mmfr3 = 0x0211;
+ cpu->id_isar0 = 0x2101111;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232141;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x0010142;
+ cpu->id_isar5 = 0x0;
+ cpu->mp_is_up = true;
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
+}
+
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -1214,6 +1284,9 @@
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c9d2330..80297b3 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -284,6 +284,9 @@
};
uint64_t par_el[4];
};
+
+ uint32_t c6_rgnr;
+
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
uint64_t c9_pmcr; /* performance monitor control register */
@@ -482,6 +485,13 @@
/* Internal CPU feature flags. */
uint64_t features;
+ /* PMSAv7 MPU */
+ struct {
+ uint32_t *drbar;
+ uint32_t *drsr;
+ uint32_t *dracr;
+ } pmsav7;
+
void *nvic;
const struct arm_boot_info *boot_info;
} CPUARMState;
@@ -550,6 +560,7 @@
#define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
#define SCTLR_nTWI (1U << 16) /* v8 onward */
#define SCTLR_HA (1U << 17)
+#define SCTLR_BR (1U << 17) /* PMSA only */
#define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
#define SCTLR_nTWE (1U << 18) /* v8 onward */
#define SCTLR_WXN (1U << 19)
@@ -1116,8 +1127,8 @@
* old must have the OVERRIDE bit set.
* ALIAS indicates that this register is an alias view of some underlying
* state which is also visible via another register, and that the other
- * register is handling migration; registers marked ALIAS will not be migrated
- * but may have their state set by syncing of register state from KVM.
+ * register is handling migration and reset; registers marked ALIAS will not be
+ * migrated but may have their state set by syncing of register state from KVM.
* NO_RAW indicates that this register has no underlying state and does not
* support raw access for state saving/loading; it will not be used for either
* migration or KVM state synchronization. (Typically this is for "registers"
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00509b1..aa34159 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,6 +10,7 @@
#include "exec/cpu_ldst.h"
#include "arm_ldst.h"
#include <zlib.h> /* For crc32 */
+#include "exec/semihost.h"
#ifndef CONFIG_USER_ONLY
static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
@@ -984,7 +985,7 @@
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
- .resetvalue = 0, .writefn = pmintenclr_write, },
+ .writefn = pmintenclr_write, },
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
@@ -1323,7 +1324,6 @@
.type = ARM_CP_ALIAS,
.access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
.fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
- .resetfn = arm_cp_reset_ignore,
},
{ .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
@@ -1344,7 +1344,6 @@
.accessfn = gt_ptimer_access,
.fieldoffset = offsetoflow32(CPUARMState,
cp15.c14_timer[GTIMER_PHYS].ctl),
- .resetfn = arm_cp_reset_ignore,
.writefn = gt_ctl_write, .raw_writefn = raw_write,
},
{ .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
@@ -1360,7 +1359,6 @@
.accessfn = gt_vtimer_access,
.fieldoffset = offsetoflow32(CPUARMState,
cp15.c14_timer[GTIMER_VIRT].ctl),
- .resetfn = arm_cp_reset_ignore,
.writefn = gt_ctl_write, .raw_writefn = raw_write,
},
{ .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
@@ -1422,7 +1420,7 @@
.access = PL1_RW | PL0_R,
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
- .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
+ .accessfn = gt_ptimer_access,
.writefn = gt_cval_write, .raw_writefn = raw_write,
},
{ .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
@@ -1437,7 +1435,7 @@
.access = PL1_RW | PL0_R,
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
- .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
+ .accessfn = gt_vtimer_access,
.writefn = gt_cval_write, .raw_writefn = raw_write,
},
{ .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
@@ -1710,16 +1708,89 @@
return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
}
+static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
+
+ if (!u32p) {
+ return 0;
+ }
+
+ u32p += env->cp15.c6_rgnr;
+ return *u32p;
+}
+
+static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
+
+ if (!u32p) {
+ return;
+ }
+
+ u32p += env->cp15.c6_rgnr;
+ tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
+ *u32p = value;
+}
+
+static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
+
+ if (!u32p) {
+ return;
+ }
+
+ memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
+}
+
+static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ uint32_t nrgs = cpu->pmsav7_dregion;
+
+ if (value >= nrgs) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "PMSAv7 RGNR write >= # supported regions, %" PRIu32
+ " > %" PRIu32 "\n", (uint32_t)value, nrgs);
+ return;
+ }
+
+ raw_write(env, ri, value);
+}
+
+static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
+ { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
+ .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
+ .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
+ { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
+ .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
+ .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
+ { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
+ .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
+ .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
+ { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
+ .writefn = pmsav7_rgnr_write },
+ REGINFO_SENTINEL
+};
+
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
{ .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
- .resetvalue = 0,
.readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
{ .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
- .resetvalue = 0,
.readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
{ .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW,
@@ -1851,8 +1922,7 @@
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_ALIAS,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
- offsetoflow32(CPUARMState, cp15.dfsr_ns) },
- .resetfn = arm_cp_reset_ignore, },
+ offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .resetvalue = 0,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
@@ -1890,7 +1960,7 @@
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
- .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
+ .raw_writefn = vmsa_ttbcr_raw_write,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
REGINFO_SENTINEL
@@ -2109,12 +2179,12 @@
.access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
offsetof(CPUARMState, cp15.ttbr0_ns) },
- .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
+ .writefn = vmsa_ttbr_write, },
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
.access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
offsetof(CPUARMState, cp15.ttbr1_ns) },
- .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
+ .writefn = vmsa_ttbr_write, },
REGINFO_SENTINEL
};
@@ -2641,7 +2711,6 @@
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
- .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
@@ -2666,7 +2735,7 @@
{ .name = "SCR", .type = ARM_CP_ALIAS,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
- .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
+ .writefn = scr_write },
{ .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL3_RW, .resetvalue = 0,
@@ -2761,8 +2830,7 @@
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
.type = ARM_CP_ALIAS,
.access = PL1_R,
- .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
- .resetfn = arm_cp_reset_ignore },
+ .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
@@ -3345,13 +3413,14 @@
define_one_arm_cp_reg(cpu, &rvbar);
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
- /* These are the MPU registers prior to PMSAv6. Any new
- * PMSA core later than the ARM946 will require that we
- * implement the PMSAv6 or PMSAv7 registers, which are
- * completely different.
- */
- assert(!arm_feature(env, ARM_FEATURE_V6));
- define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
+ if (arm_feature(env, ARM_FEATURE_V6)) {
+ /* PMSAv6 not implemented */
+ assert(arm_feature(env, ARM_FEATURE_V7));
+ define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
+ define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
+ } else {
+ define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
+ }
} else {
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
@@ -3465,6 +3534,13 @@
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
};
+ /* MPUIR is specific to PMSA V6+ */
+ ARMCPRegInfo id_mpuir_reginfo = {
+ .name = "MPUIR",
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
+ .access = PL1_R, .type = ARM_CP_CONST,
+ .resetvalue = cpu->pmsav7_dregion << 8
+ };
ARMCPRegInfo crn0_wi_reginfo = {
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
@@ -3487,6 +3563,7 @@
r->access = PL1_RW;
}
id_tlbtr_reginfo.access = PL1_RW;
+ id_tlbtr_reginfo.access = PL1_RW;
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
@@ -3496,6 +3573,8 @@
define_arm_cp_regs(cpu, id_cp_reginfo);
if (!arm_feature(env, ARM_FEATURE_MPU)) {
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
+ } else if (arm_feature(env, ARM_FEATURE_V7)) {
+ define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
}
}
@@ -3721,14 +3800,12 @@
if ((r->state == ARM_CP_STATE_BOTH && ns) ||
(arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
r2->type |= ARM_CP_ALIAS;
- r2->resetfn = arm_cp_reset_ignore;
}
} else if ((secstate != r->secure) && !ns) {
/* The register is not banked so we only want to allow migration of
* the non-secure instance.
*/
r2->type |= ARM_CP_ALIAS;
- r2->resetfn = arm_cp_reset_ignore;
}
if (r->state == ARM_CP_STATE_BOTH) {
@@ -4478,7 +4555,7 @@
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
return;
case EXCP_BKPT:
- if (semihosting_enabled) {
+ if (semihosting_enabled()) {
int nr;
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (nr == 0xab) {
@@ -4790,7 +4867,7 @@
offset = 4;
break;
case EXCP_SWI:
- if (semihosting_enabled) {
+ if (semihosting_enabled()) {
/* Check for semihosting interrupt. */
if (env->thumb) {
mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
@@ -4817,7 +4894,7 @@
break;
case EXCP_BKPT:
/* See if this is a semihosting syscall. */
- if (env->thumb && semihosting_enabled) {
+ if (env->thumb && semihosting_enabled()) {
mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (mask == 0xab
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
@@ -5759,6 +5836,167 @@
return true;
}
+static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
+ ARMMMUIdx mmu_idx,
+ int32_t address, int *prot)
+{
+ *prot = PAGE_READ | PAGE_WRITE;
+ switch (address) {
+ case 0xF0000000 ... 0xFFFFFFFF:
+ if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
+ *prot |= PAGE_EXEC;
+ }
+ break;
+ case 0x00000000 ... 0x7FFFFFFF:
+ *prot |= PAGE_EXEC;
+ break;
+ }
+
+}
+
+static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
+ int access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, int *prot, uint32_t *fsr)
+{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ int n;
+ bool is_user = regime_is_user(env, mmu_idx);
+
+ *phys_ptr = address;
+ *prot = 0;
+
+ if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
+ } else { /* MPU enabled */
+ for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
+ /* region search */
+ uint32_t base = env->pmsav7.drbar[n];
+ uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
+ uint32_t rmask;
+ bool srdis = false;
+
+ if (!(env->pmsav7.drsr[n] & 0x1)) {
+ continue;
+ }
+
+ if (!rsize) {
+ qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
+ continue;
+ }
+ rsize++;
+ rmask = (1ull << rsize) - 1;
+
+ if (base & rmask) {
+ qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
+ "to DRSR region size, mask = %" PRIx32,
+ base, rmask);
+ continue;
+ }
+
+ if (address < base || address > base + rmask) {
+ continue;
+ }
+
+ /* Region matched */
+
+ if (rsize >= 8) { /* no subregions for regions < 256 bytes */
+ int i, snd;
+ uint32_t srdis_mask;
+
+ rsize -= 3; /* sub region size (power of 2) */
+ snd = ((address - base) >> rsize) & 0x7;
+ srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
+
+ srdis_mask = srdis ? 0x3 : 0x0;
+ for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
+ /* This will check in groups of 2, 4 and then 8, whether
+ * the subregion bits are consistent. rsize is incremented
+ * back up to give the region size, considering consistent
+ * adjacent subregions as one region. Stop testing if rsize
+ * is already big enough for an entire QEMU page.
+ */
+ int snd_rounded = snd & ~(i - 1);
+ uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
+ snd_rounded + 8, i);
+ if (srdis_mask ^ srdis_multi) {
+ break;
+ }
+ srdis_mask = (srdis_mask << i) | srdis_mask;
+ rsize++;
+ }
+ }
+ if (rsize < TARGET_PAGE_BITS) {
+ qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
+ "alignment of %" PRIu32 " bits. Minimum is %d\n",
+ rsize, TARGET_PAGE_BITS);
+ continue;
+ }
+ if (srdis) {
+ continue;
+ }
+ break;
+ }
+
+ if (n == -1) { /* no hits */
+ if (cpu->pmsav7_dregion &&
+ (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
+ /* background fault */
+ *fsr = 0;
+ return true;
+ }
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
+ } else { /* a MPU hit! */
+ uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
+
+ if (is_user) { /* User mode AP bit decoding */
+ switch (ap) {
+ case 0:
+ case 1:
+ case 5:
+ break; /* no access */
+ case 3:
+ *prot |= PAGE_WRITE;
+ /* fall through */
+ case 2:
+ case 6:
+ *prot |= PAGE_READ | PAGE_EXEC;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Bad value for AP bits in DRACR %"
+ PRIx32 "\n", ap);
+ }
+ } else { /* Priv. mode AP bits decoding */
+ switch (ap) {
+ case 0:
+ break; /* no access */
+ case 1:
+ case 2:
+ case 3:
+ *prot |= PAGE_WRITE;
+ /* fall through */
+ case 5:
+ case 6:
+ *prot |= PAGE_READ | PAGE_EXEC;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Bad value for AP bits in DRACR %"
+ PRIx32 "\n", ap);
+ }
+ }
+
+ /* execute never */
+ if (env->pmsav7.dracr[n] & (1 << 12)) {
+ *prot &= ~PAGE_EXEC;
+ }
+ }
+ }
+
+ *fsr = 0x00d; /* Permission fault */
+ return !(*prot & (1 << access_type));
+}
+
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
@@ -5844,7 +6082,7 @@
* DFSR/IFSR fault register, with the following caveats:
* * we honour the short vs long DFSR format differences.
* * the WnR bit is never set (the caller must do this).
- * * for MPU based systems we don't bother to return a full FSR format
+ * * for PSMAv5 based systems we don't bother to return a full FSR format
* value.
*
* @env: CPUARMState
@@ -5892,6 +6130,16 @@
}
}
+ /* pmsav7 has special handling for when MPU is disabled so call it before
+ * the common MMU/MPU disabled check below.
+ */
+ if (arm_feature(env, ARM_FEATURE_MPU) &&
+ arm_feature(env, ARM_FEATURE_V7)) {
+ *page_size = TARGET_PAGE_SIZE;
+ return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
+ phys_ptr, prot, fsr);
+ }
+
if (regime_translation_disabled(env, mmu_idx)) {
/* MMU/MPU disabled. */
*phys_ptr = address;
@@ -5901,6 +6149,7 @@
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
+ /* Pre-v7 MPU */
*page_size = TARGET_PAGE_SIZE;
return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
phys_ptr, prot, fsr);
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 36365a5..9eb51df 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -125,6 +125,39 @@
}
};
+static bool pmsav7_needed(void *opaque)
+{
+ ARMCPU *cpu = opaque;
+ CPUARMState *env = &cpu->env;
+
+ return arm_feature(env, ARM_FEATURE_MPU) &&
+ arm_feature(env, ARM_FEATURE_V7);
+}
+
+static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
+{
+ ARMCPU *cpu = opaque;
+
+ return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
+}
+
+static const VMStateDescription vmstate_pmsav7 = {
+ .name = "cpu/pmsav7",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pmsav7_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
@@ -291,6 +324,7 @@
&vmstate_iwmmxt,
&vmstate_m,
&vmstate_thumb2ee,
+ &vmstate_pmsav7,
NULL
}
};
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 7a41f29..a88aa5a 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -20,6 +20,7 @@
#include "cpu.h"
#include "qemu/host-utils.h"
#include "sysemu/sysemu.h"
+#include "exec/semihost.h"
int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
@@ -162,7 +163,7 @@
switch (cs->exception_index) {
case EXCP_SYSTEMCALL:
- if (unlikely(semihosting_enabled)) {
+ if (unlikely(semihosting_enabled())) {
/* do_semicall() returns true if call was handled. Otherwise
* do the normal exception handling. */
if (lm32_cpu_do_semihosting(cs)) {
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 06661f5..4f8fabb 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -19,6 +19,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
+#include "exec/semihost.h"
#if defined(CONFIG_USER_ONLY)
@@ -33,8 +34,6 @@
#else
-extern int semihosting_enabled;
-
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
@@ -85,7 +84,7 @@
do_rte(env);
return;
case EXCP_HALT_INSN:
- if (semihosting_enabled
+ if (semihosting_enabled()
&& (env->sr & SR_S) != 0
&& (env->pc & 3) == 0
&& cpu_lduw_code(env, env->pc - 4) == 0x4e71
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index e3e0701..34f6273 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -56,9 +56,21 @@
typedef struct MicroBlazeCPU {
/*< private >*/
CPUState parent_obj;
- uint32_t base_vectors;
+
/*< public >*/
+ /* Microblaze Configuration Settings */
+ struct {
+ bool stackprot;
+ uint32_t base_vectors;
+ uint8_t use_fpu;
+ bool use_mmu;
+ bool dcache_writeback;
+ bool endi;
+ char *version;
+ uint8_t pvr;
+ } cfg;
+
CPUMBState env;
} MicroBlazeCPU;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 67e3182..c592bf7 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -26,6 +26,43 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
+static const struct {
+ const char *name;
+ uint8_t version_id;
+} mb_cpu_lookup[] = {
+ /* These key value are as per MBV field in PVR0 */
+ {"5.00.a", 0x01},
+ {"5.00.b", 0x02},
+ {"5.00.c", 0x03},
+ {"6.00.a", 0x04},
+ {"6.00.b", 0x06},
+ {"7.00.a", 0x05},
+ {"7.00.b", 0x07},
+ {"7.10.a", 0x08},
+ {"7.10.b", 0x09},
+ {"7.10.c", 0x0a},
+ {"7.10.d", 0x0b},
+ {"7.20.a", 0x0c},
+ {"7.20.b", 0x0d},
+ {"7.20.c", 0x0e},
+ {"7.20.d", 0x0f},
+ {"7.30.a", 0x10},
+ {"7.30.b", 0x11},
+ {"8.00.a", 0x12},
+ {"8.00.b", 0x13},
+ {"8.10.a", 0x14},
+ {"8.20.a", 0x15},
+ {"8.20.b", 0x16},
+ {"8.30.a", 0x17},
+ {"8.40.a", 0x18},
+ {"8.40.b", 0x19},
+ {"8.50.a", 0x1A},
+ {"9.0", 0x1B},
+ {"9.1", 0x1D},
+ {"9.2", 0x1F},
+ {"9.3", 0x20},
+ {NULL, 0},
+};
static void mb_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -63,45 +100,16 @@
mcc->parent_reset(s);
- memset(env, 0, sizeof(CPUMBState));
+ memset(env, 0, offsetof(CPUMBState, pvr));
env->res_addr = RES_ADDR_NONE;
tlb_flush(s, 1);
/* Disable stack protector. */
env->shr = ~0;
- env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
- | PVR0_USE_BARREL_MASK \
- | PVR0_USE_DIV_MASK \
- | PVR0_USE_HW_MUL_MASK \
- | PVR0_USE_EXC_MASK \
- | PVR0_USE_ICACHE_MASK \
- | PVR0_USE_DCACHE_MASK \
- | PVR0_USE_MMU \
- | (0xb << 8);
- env->pvr.regs[2] = PVR2_D_OPB_MASK \
- | PVR2_D_LMB_MASK \
- | PVR2_I_OPB_MASK \
- | PVR2_I_LMB_MASK \
- | PVR2_USE_MSR_INSTR \
- | PVR2_USE_PCMP_INSTR \
- | PVR2_USE_BARREL_MASK \
- | PVR2_USE_DIV_MASK \
- | PVR2_USE_HW_MUL_MASK \
- | PVR2_USE_MUL64_MASK \
- | PVR2_USE_FPU_MASK \
- | PVR2_USE_FPU2_MASK \
- | PVR2_FPU_EXC_MASK \
- | 0;
- env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
- env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
-
- env->sregs[SR_PC] = cpu->base_vectors;
-
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
- env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
#else
env->sregs[SR_MSR] = 0;
mmu_init(&env->mmu);
@@ -115,10 +123,62 @@
{
CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+ uint8_t version_code = 0;
+ int i = 0;
- cpu_reset(cs);
qemu_init_vcpu(cs);
+ env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
+ | PVR0_USE_DIV_MASK \
+ | PVR0_USE_HW_MUL_MASK \
+ | PVR0_USE_EXC_MASK \
+ | PVR0_USE_ICACHE_MASK \
+ | PVR0_USE_DCACHE_MASK \
+ | (0xb << 8);
+ env->pvr.regs[2] = PVR2_D_OPB_MASK \
+ | PVR2_D_LMB_MASK \
+ | PVR2_I_OPB_MASK \
+ | PVR2_I_LMB_MASK \
+ | PVR2_USE_MSR_INSTR \
+ | PVR2_USE_PCMP_INSTR \
+ | PVR2_USE_BARREL_MASK \
+ | PVR2_USE_DIV_MASK \
+ | PVR2_USE_HW_MUL_MASK \
+ | PVR2_USE_MUL64_MASK \
+ | PVR2_FPU_EXC_MASK \
+ | 0;
+
+ for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
+ if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
+ version_code = mb_cpu_lookup[i].version_id;
+ break;
+ }
+ }
+
+ if (!version_code) {
+ qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
+ }
+
+ env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
+ (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
+ (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
+ (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+ (version_code << 16) |
+ (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
+
+ env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
+ (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
+
+ env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
+ PVR5_DCACHE_WRITEBACK_MASK : 0;
+
+ env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
+ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
+
+ env->sregs[SR_PC] = cpu->cfg.base_vectors;
+
mcc->parent_realize(dev, errp);
}
@@ -151,7 +211,20 @@
};
static Property mb_properties[] = {
- DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
+ DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
+ DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
+ false),
+ /* If use-fpu > 0 - FPU is enabled
+ * If use-fpu = 2 - Floating point conversion and square root instructions
+ * are enabled
+ */
+ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
+ DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
+ DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
+ false),
+ DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
+ DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
+ DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index d73e1c7..0dd164f 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -122,12 +122,13 @@
#define PVR0_USE_EXC_MASK 0x04000000
#define PVR0_USE_ICACHE_MASK 0x02000000
#define PVR0_USE_DCACHE_MASK 0x01000000
-#define PVR0_USE_MMU 0x00800000 /* new */
+#define PVR0_USE_MMU_MASK 0x00800000
#define PVR0_USE_BTC 0x00400000
-#define PVR0_ENDI 0x00200000
+#define PVR0_ENDI_MASK 0x00200000
#define PVR0_FAULT 0x00100000
#define PVR0_VERSION_MASK 0x0000FF00
#define PVR0_USER1_MASK 0x000000FF
+#define PVR0_SPROT_MASK 0x00000001
/* User 2 PVR mask */
#define PVR1_USER2_MASK 0xFFFFFFFF
@@ -211,7 +212,9 @@
/* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
-
+#define C_PVR_NONE 0
+#define C_PVR_BASIC 1
+#define C_PVR_FULL 2
/* CPU flags. */
@@ -260,16 +263,18 @@
#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
uint32_t iflags;
- struct {
- uint32_t regs[16];
- } pvr;
-
#if !defined(CONFIG_USER_ONLY)
/* Unified MMU. */
struct microblaze_mmu mmu;
#endif
CPU_COMMON
+
+ /* These fields are preserved on reset. */
+
+ struct {
+ uint32_t regs[16];
+ } pvr;
};
#include "cpu-qom.h"
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 32896f4..8257b0e 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -56,10 +56,10 @@
int prot;
mmu_available = 0;
- if (env->pvr.regs[0] & PVR0_USE_MMU) {
+ if (cpu->cfg.use_mmu) {
mmu_available = 1;
- if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
- && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+ if ((cpu->cfg.pvr == C_PVR_FULL) &&
+ (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
mmu_available = 0;
}
}
@@ -154,7 +154,7 @@
env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
- env->sregs[SR_PC] = cpu->base_vectors + 0x20;
+ env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
break;
case EXCP_MMU:
@@ -194,7 +194,7 @@
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
- env->sregs[SR_PC] = cpu->base_vectors + 0x20;
+ env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
break;
case EXCP_IRQ:
@@ -235,7 +235,7 @@
env->sregs[SR_MSR] |= t;
env->regs[14] = env->sregs[SR_PC];
- env->sregs[SR_PC] = cpu->base_vectors + 0x10;
+ env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
@@ -254,7 +254,7 @@
if (cs->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC];
env->sregs[SR_MSR] |= MSR_BIP;
- env->sregs[SR_PC] = cpu->base_vectors + 0x18;
+ env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
} else
env->sregs[SR_PC] = env->btarget;
break;
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index a4c8f04..d2b3624 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -468,11 +468,11 @@
void helper_stackprot(CPUMBState *env, uint32_t addr)
{
if (addr < env->slr || addr > env->shr) {
- qemu_log("Stack protector violation at %x %x %x\n",
- addr, env->slr, env->shr);
- env->sregs[SR_EAR] = addr;
- env->sregs[SR_ESR] = ESR_EC_STACKPROT;
- helper_raise_exception(env, EXCP_HW_EXCP);
+ qemu_log("Stack protector violation at %x %x %x\n",
+ addr, env->slr, env->shr);
+ env->sregs[SR_EAR] = addr;
+ env->sregs[SR_ESR] = ESR_EC_STACKPROT;
+ helper_raise_exception(env, EXCP_HW_EXCP);
}
}
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 4068946..1f5fe9a 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -862,7 +862,7 @@
int stackprot = 0;
/* All load/stores use ra. */
- if (dc->ra == 1) {
+ if (dc->ra == 1 && dc->cpu->cfg.stackprot) {
stackprot = 1;
}
@@ -875,7 +875,7 @@
return &cpu_R[dc->ra];
}
- if (dc->rb == 1) {
+ if (dc->rb == 1 && dc->cpu->cfg.stackprot) {
stackprot = 1;
}
@@ -1411,15 +1411,11 @@
static int dec_check_fpuv2(DisasContext *dc)
{
- int r;
-
- r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK;
-
- if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
+ if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
- return r;
+ return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
}
static void dec_fpu(DisasContext *dc)
@@ -1428,7 +1424,7 @@
if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) {
+ && (dc->cpu->cfg.use_fpu != 1)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 6e5096c..3d52079 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -37,6 +37,7 @@
#include "qemu/log.h"
#include "sysemu/sysemu.h"
#include "exec/cpu_ldst.h"
+#include "exec/semihost.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
@@ -1216,7 +1217,7 @@
break;
case 1: /*SIMCALL*/
- if (semihosting_enabled) {
+ if (semihosting_enabled()) {
if (gen_check_privilege(dc)) {
gen_helper_simcall(cpu_env);
}
diff --git a/tests/Makefile b/tests/Makefile
index af22fd9..eff5e11 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -374,7 +374,7 @@
tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y)
tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y)
tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y)
-tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o
+tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y)
tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o
tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o
tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o
diff --git a/tests/libqos/malloc.c b/tests/libqos/malloc.c
index 8276130..82b9df5 100644
--- a/tests/libqos/malloc.c
+++ b/tests/libqos/malloc.c
@@ -285,6 +285,9 @@
void guest_free(QGuestAllocator *allocator, uint64_t addr)
{
+ if (!addr) {
+ return;
+ }
mlist_free(allocator, addr);
if (allocator->opts & ALLOC_PARANOID) {
mlist_check(allocator);
diff --git a/tests/libqos/virtio.h b/tests/libqos/virtio.h
index 2449fee..0101278 100644
--- a/tests/libqos/virtio.h
+++ b/tests/libqos/virtio.h
@@ -19,8 +19,14 @@
#define QVIRTIO_DRIVER 0x2
#define QVIRTIO_DRIVER_OK 0x4
-#define QVIRTIO_NET_DEVICE_ID 0x1
-#define QVIRTIO_BLK_DEVICE_ID 0x2
+#define QVIRTIO_NET_DEVICE_ID 0x1
+#define QVIRTIO_BLK_DEVICE_ID 0x2
+#define QVIRTIO_CONSOLE_DEVICE_ID 0x3
+#define QVIRTIO_RNG_DEVICE_ID 0x4
+#define QVIRTIO_BALLOON_DEVICE_ID 0x5
+#define QVIRTIO_RPMSG_DEVICE_ID 0x7
+#define QVIRTIO_SCSI_DEVICE_ID 0x8
+#define QVIRTIO_9P_DEVICE_ID 0x9
#define QVIRTIO_F_NOTIFY_ON_EMPTY 0x01000000
#define QVIRTIO_F_ANY_LAYOUT 0x08000000
diff --git a/tests/virtio-scsi-test.c b/tests/virtio-scsi-test.c
index 989f825..11ccdd6 100644
--- a/tests/virtio-scsi-test.c
+++ b/tests/virtio-scsi-test.c
@@ -2,6 +2,7 @@
* QTest testcase for VirtIO SCSI
*
* Copyright (c) 2014 SUSE LINUX Products GmbH
+ * Copyright (c) 2015 Red Hat Inc.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -11,16 +12,187 @@
#include <string.h>
#include "libqtest.h"
#include "qemu/osdep.h"
+#include <stdio.h>
+#include "libqos/virtio.h"
+#include "libqos/virtio-pci.h"
+#include "libqos/pci-pc.h"
+#include "libqos/malloc.h"
+#include "libqos/malloc-pc.h"
+#include "libqos/malloc-generic.h"
+
+#define PCI_SLOT 0x02
+#define PCI_FN 0x00
+#define QVIRTIO_SCSI_TIMEOUT_US (1 * 1000 * 1000)
+#define CDB_SIZE 32
+
+#define MAX_NUM_QUEUES 64
+
+typedef struct {
+ QVirtioDevice *dev;
+ QGuestAllocator *alloc;
+ QPCIBus *bus;
+ int num_queues;
+ QVirtQueue *vq[MAX_NUM_QUEUES + 2];
+} QVirtIOSCSI;
+
+typedef struct {
+ uint8_t lun[8];
+ int64_t tag;
+ uint8_t task_attr;
+ uint8_t prio;
+ uint8_t crn;
+ uint8_t cdb[CDB_SIZE];
+} QEMU_PACKED QVirtIOSCSICmdReq;
+
+typedef struct {
+ uint32_t sense_len;
+ uint32_t resid;
+ uint16_t status_qualifier;
+ uint8_t status;
+ uint8_t response;
+ uint8_t sense[96];
+} QEMU_PACKED QVirtIOSCSICmdResp;
+
+static void qvirtio_scsi_start(const char *extra_opts)
+{
+ char *cmdline;
+
+ cmdline = g_strdup_printf(
+ "-drive id=drv0,if=none,file=/dev/null,format=raw "
+ "-device virtio-scsi-pci,id=vs0 "
+ "-device scsi-hd,bus=vs0.0,drive=drv0 %s",
+ extra_opts ? : "");
+ qtest_start(cmdline);
+ g_free(cmdline);
+}
+
+static void qvirtio_scsi_stop(void)
+{
+ qtest_end();
+}
+
+static QVirtIOSCSI *qvirtio_scsi_pci_init(int slot)
+{
+ QVirtIOSCSI *vs;
+ QVirtioPCIDevice *dev;
+ void *addr;
+ int i;
+
+ vs = g_new0(QVirtIOSCSI, 1);
+ vs->alloc = pc_alloc_init();
+ vs->bus = qpci_init_pc();
+
+ dev = qvirtio_pci_device_find(vs->bus, QVIRTIO_SCSI_DEVICE_ID);
+ vs->dev = (QVirtioDevice *)dev;
+ g_assert(dev != NULL);
+ g_assert_cmphex(vs->dev->device_type, ==, QVIRTIO_SCSI_DEVICE_ID);
+
+ qvirtio_pci_device_enable(dev);
+ qvirtio_reset(&qvirtio_pci, vs->dev);
+ qvirtio_set_acknowledge(&qvirtio_pci, vs->dev);
+ qvirtio_set_driver(&qvirtio_pci, vs->dev);
+
+ addr = dev->addr + QVIRTIO_PCI_DEVICE_SPECIFIC_NO_MSIX;
+ vs->num_queues = qvirtio_config_readl(&qvirtio_pci, vs->dev,
+ (uint64_t)(uintptr_t)addr);
+
+ g_assert_cmpint(vs->num_queues, <, MAX_NUM_QUEUES);
+
+ for (i = 0; i < vs->num_queues + 2; i++) {
+ vs->vq[i] = qvirtqueue_setup(&qvirtio_pci, vs->dev, vs->alloc, i);
+ }
+
+ return vs;
+}
+
+static void qvirtio_scsi_pci_free(QVirtIOSCSI *vs)
+{
+ int i;
+
+ for (i = 0; i < vs->num_queues + 2; i++) {
+ guest_free(vs->alloc, vs->vq[i]->desc);
+ }
+ pc_alloc_uninit(vs->alloc);
+ qvirtio_pci_device_disable(container_of(vs->dev, QVirtioPCIDevice, vdev));
+ g_free(vs->dev);
+ qpci_free_pc(vs->bus);
+}
+
+static uint64_t qvirtio_scsi_alloc(QVirtIOSCSI *vs, size_t alloc_size,
+ const void *data)
+{
+ uint64_t addr;
+
+ addr = guest_alloc(vs->alloc, alloc_size);
+ if (data) {
+ memwrite(addr, data, alloc_size);
+ }
+
+ return addr;
+}
+
+static uint8_t virtio_scsi_do_command(QVirtIOSCSI *vs, const uint8_t *cdb,
+ const uint8_t *data_in,
+ size_t data_in_len,
+ uint8_t *data_out, size_t data_out_len)
+{
+ QVirtQueue *vq;
+ QVirtIOSCSICmdReq req = { { 0 } };
+ QVirtIOSCSICmdResp resp = { .response = 0xff, .status = 0xff };
+ uint64_t req_addr, resp_addr, data_in_addr = 0, data_out_addr = 0;
+ uint8_t response;
+ uint32_t free_head;
+
+ vq = vs->vq[2];
+
+ req.lun[0] = 1; /* Select LUN */
+ req.lun[1] = 1; /* Select target 1 */
+ memcpy(req.cdb, cdb, CDB_SIZE);
+
+ /* XXX: Fix endian if any multi-byte field in req/resp is used */
+
+ /* Add request header */
+ req_addr = qvirtio_scsi_alloc(vs, sizeof(req), &req);
+ free_head = qvirtqueue_add(vq, req_addr, sizeof(req), false, true);
+
+ if (data_out_len) {
+ data_out_addr = qvirtio_scsi_alloc(vs, data_out_len, data_out);
+ qvirtqueue_add(vq, data_out_addr, data_out_len, false, true);
+ }
+
+ /* Add response header */
+ resp_addr = qvirtio_scsi_alloc(vs, sizeof(resp), &resp);
+ qvirtqueue_add(vq, resp_addr, sizeof(resp), true, !!data_in_len);
+
+ if (data_in_len) {
+ data_in_addr = qvirtio_scsi_alloc(vs, data_in_len, data_in);
+ qvirtqueue_add(vq, data_in_addr, data_in_len, true, false);
+ }
+
+ qvirtqueue_kick(&qvirtio_pci, vs->dev, vq, free_head);
+ qvirtio_wait_queue_isr(&qvirtio_pci, vs->dev, vq, QVIRTIO_SCSI_TIMEOUT_US);
+
+ response = readb(resp_addr + offsetof(QVirtIOSCSICmdResp, response));
+
+ guest_free(vs->alloc, req_addr);
+ guest_free(vs->alloc, resp_addr);
+ guest_free(vs->alloc, data_in_addr);
+ guest_free(vs->alloc, data_out_addr);
+ return response;
+}
/* Tests only initialization so far. TODO: Replace with functional tests */
static void pci_nop(void)
{
+ qvirtio_scsi_start(NULL);
+ qvirtio_scsi_stop();
}
static void hotplug(void)
{
QDict *response;
+ qvirtio_scsi_start("-drive id=drv1,if=none,file=/dev/null,format=raw");
response = qmp("{\"execute\": \"device_add\","
" \"arguments\": {"
" \"driver\": \"scsi-hd\","
@@ -42,6 +214,27 @@
g_assert(qdict_haskey(response, "event"));
g_assert(!strcmp(qdict_get_str(response, "event"), "DEVICE_DELETED"));
QDECREF(response);
+ qvirtio_scsi_stop();
+}
+
+/* Test WRITE SAME with the lba not aligned */
+static void test_unaligned_write_same(void)
+{
+ QVirtIOSCSI *vs;
+ uint8_t buf[512] = { 0 };
+ const uint8_t write_same_cdb[CDB_SIZE] = { 0x41, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x02, 0x00 };
+
+ qvirtio_scsi_start("-drive file=blkdebug::null-co://,if=none,id=dr1"
+ ",format=raw,file.align=4k "
+ "-device scsi-disk,drive=dr1,lun=0,scsi-id=1");
+ vs = qvirtio_scsi_pci_init(PCI_SLOT);
+
+ g_assert_cmphex(0, ==,
+ virtio_scsi_do_command(vs, write_same_cdb, NULL, 0, buf, 512));
+
+ qvirtio_scsi_pci_free(vs);
+ qvirtio_scsi_stop();
}
int main(int argc, char **argv)
@@ -51,14 +244,10 @@
g_test_init(&argc, &argv, NULL);
qtest_add_func("/virtio/scsi/pci/nop", pci_nop);
qtest_add_func("/virtio/scsi/pci/hotplug", hotplug);
+ qtest_add_func("/virtio/scsi/pci/scsi-disk/unaligned-write-same",
+ test_unaligned_write_same);
- qtest_start("-drive id=drv0,if=none,file=/dev/null,format=raw "
- "-drive id=drv1,if=none,file=/dev/null,format=raw "
- "-device virtio-scsi-pci,id=vscsi0 "
- "-device scsi-hd,bus=vscsi0.0,drive=drv0");
ret = g_test_run();
- qtest_end();
-
return ret;
}
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 85cb24c..334e6f6 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -29,6 +29,8 @@
#include "ui/console.h"
#include "ui/input.h"
#include "sysemu/sysemu.h"
+#include "qmp-commands.h"
+#include "sysemu/blockdev.h"
#ifndef MAC_OS_X_VERSION_10_5
#define MAC_OS_X_VERSION_10_5 1050
@@ -65,6 +67,8 @@
int gArgc;
char **gArgv;
bool stretch_video;
+NSTextField *pauseLabel;
+NSArray * supportedImageFileTypes;
// keymap conversion
int keymap[] =
@@ -240,7 +244,24 @@
return keymap[keycode];
}
+/* Displays an alert dialog box with the specified message */
+static void QEMU_Alert(NSString *message)
+{
+ NSAlert *alert;
+ alert = [NSAlert new];
+ [alert setMessageText: message];
+ [alert runModal];
+}
+/* Handles any errors that happen with a device transaction */
+static void handleAnyDeviceErrors(Error * err)
+{
+ if (err) {
+ QEMU_Alert([NSString stringWithCString: error_get_pretty(err)
+ encoding: NSASCIIStringEncoding]);
+ error_free(err);
+ }
+}
/*
------------------------------------------------------
@@ -800,6 +821,14 @@
- (void)showQEMUTec:(id)sender;
- (void)zoomToFit:(id) sender;
- (void)displayConsole:(id)sender;
+- (void)pauseQEMU:(id)sender;
+- (void)resumeQEMU:(id)sender;
+- (void)displayPause;
+- (void)removePause;
+- (void)restartQEMU:(id)sender;
+- (void)powerDownQEMU:(id)sender;
+- (void)ejectDeviceMedia:(id)sender;
+- (void)changeDeviceMedia:(id)sender;
@end
@implementation QemuCocoaAppController
@@ -834,6 +863,22 @@
[normalWindow makeKeyAndOrderFront:self];
[normalWindow center];
stretch_video = false;
+
+ /* Used for displaying pause on the screen */
+ pauseLabel = [NSTextField new];
+ [pauseLabel setBezeled:YES];
+ [pauseLabel setDrawsBackground:YES];
+ [pauseLabel setBackgroundColor: [NSColor whiteColor]];
+ [pauseLabel setEditable:NO];
+ [pauseLabel setSelectable:NO];
+ [pauseLabel setStringValue: @"Paused"];
+ [pauseLabel setFont: [NSFont fontWithName: @"Helvetica" size: 90]];
+ [pauseLabel setTextColor: [NSColor blackColor]];
+ [pauseLabel sizeToFit];
+
+ // set the supported image file types that can be opened
+ supportedImageFileTypes = [NSArray arrayWithObjects: @"img", @"iso", @"dmg",
+ @"qcow", @"qcow2", @"cloop", @"vmdk", nil];
}
return self;
}
@@ -857,10 +902,8 @@
NSOpenPanel *op = [[NSOpenPanel alloc] init];
[op setPrompt:@"Boot image"];
[op setMessage:@"Select the disk image you want to boot.\n\nHit the \"Cancel\" button to quit"];
- NSArray *filetypes = [NSArray arrayWithObjects:@"img", @"iso", @"dmg",
- @"qcow", @"qcow2", @"cloop", @"vmdk", nil];
#if (MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_X_VERSION_10_6)
- [op setAllowedFileTypes:filetypes];
+ [op setAllowedFileTypes:supportedImageFileTypes];
[op beginSheetModalForWindow:normalWindow
completionHandler:^(NSInteger returnCode)
{ [self openPanelDidEnd:op
@@ -977,6 +1020,111 @@
{
console_select([sender tag]);
}
+
+/* Pause the guest */
+- (void)pauseQEMU:(id)sender
+{
+ qmp_stop(NULL);
+ [sender setEnabled: NO];
+ [[[sender menu] itemWithTitle: @"Resume"] setEnabled: YES];
+ [self displayPause];
+}
+
+/* Resume running the guest operating system */
+- (void)resumeQEMU:(id) sender
+{
+ qmp_cont(NULL);
+ [sender setEnabled: NO];
+ [[[sender menu] itemWithTitle: @"Pause"] setEnabled: YES];
+ [self removePause];
+}
+
+/* Displays the word pause on the screen */
+- (void)displayPause
+{
+ /* Coordinates have to be calculated each time because the window can change its size */
+ int xCoord, yCoord, width, height;
+ xCoord = ([normalWindow frame].size.width - [pauseLabel frame].size.width)/2;
+ yCoord = [normalWindow frame].size.height - [pauseLabel frame].size.height - ([pauseLabel frame].size.height * .5);
+ width = [pauseLabel frame].size.width;
+ height = [pauseLabel frame].size.height;
+ [pauseLabel setFrame: NSMakeRect(xCoord, yCoord, width, height)];
+ [cocoaView addSubview: pauseLabel];
+}
+
+/* Removes the word pause from the screen */
+- (void)removePause
+{
+ [pauseLabel removeFromSuperview];
+}
+
+/* Restarts QEMU */
+- (void)restartQEMU:(id)sender
+{
+ qmp_system_reset(NULL);
+}
+
+/* Powers down QEMU */
+- (void)powerDownQEMU:(id)sender
+{
+ qmp_system_powerdown(NULL);
+}
+
+/* Ejects the media.
+ * Uses sender's tag to figure out the device to eject.
+ */
+- (void)ejectDeviceMedia:(id)sender
+{
+ NSString * drive;
+ drive = [sender representedObject];
+ if(drive == nil) {
+ NSBeep();
+ QEMU_Alert(@"Failed to find drive to eject!");
+ return;
+ }
+
+ Error *err = NULL;
+ qmp_eject([drive cStringUsingEncoding: NSASCIIStringEncoding], false, false, &err);
+ handleAnyDeviceErrors(err);
+}
+
+/* Displays a dialog box asking the user to select an image file to load.
+ * Uses sender's represented object value to figure out which drive to use.
+ */
+- (void)changeDeviceMedia:(id)sender
+{
+ /* Find the drive name */
+ NSString * drive;
+ drive = [sender representedObject];
+ if(drive == nil) {
+ NSBeep();
+ QEMU_Alert(@"Could not find drive!");
+ return;
+ }
+
+ /* Display the file open dialog */
+ NSOpenPanel * openPanel;
+ openPanel = [NSOpenPanel openPanel];
+ [openPanel setCanChooseFiles: YES];
+ [openPanel setAllowsMultipleSelection: NO];
+ [openPanel setAllowedFileTypes: supportedImageFileTypes];
+ if([openPanel runModal] == NSFileHandlingPanelOKButton) {
+ NSString * file = [[[openPanel URLs] objectAtIndex: 0] path];
+ if(file == nil) {
+ NSBeep();
+ QEMU_Alert(@"Failed to convert URL to file path!");
+ return;
+ }
+
+ Error *err = NULL;
+ qmp_change_blockdev([drive cStringUsingEncoding: NSASCIIStringEncoding],
+ [file cStringUsingEncoding: NSASCIIStringEncoding],
+ "raw",
+ &err);
+ handleAnyDeviceErrors(err);
+ }
+}
+
@end
@@ -1036,6 +1184,20 @@
[[NSApp mainMenu] addItem:menuItem];
[NSApp performSelector:@selector(setAppleMenu:) withObject:menu]; // Workaround (this method is private since 10.4+)
+ // Machine menu
+ menu = [[NSMenu alloc] initWithTitle: @"Machine"];
+ [menu setAutoenablesItems: NO];
+ [menu addItem: [[[NSMenuItem alloc] initWithTitle: @"Pause" action: @selector(pauseQEMU:) keyEquivalent: @""] autorelease]];
+ menuItem = [[[NSMenuItem alloc] initWithTitle: @"Resume" action: @selector(resumeQEMU:) keyEquivalent: @""] autorelease];
+ [menu addItem: menuItem];
+ [menuItem setEnabled: NO];
+ [menu addItem: [NSMenuItem separatorItem]];
+ [menu addItem: [[[NSMenuItem alloc] initWithTitle: @"Reset" action: @selector(restartQEMU:) keyEquivalent: @""] autorelease]];
+ [menu addItem: [[[NSMenuItem alloc] initWithTitle: @"Power Down" action: @selector(powerDownQEMU:) keyEquivalent: @""] autorelease]];
+ menuItem = [[[NSMenuItem alloc] initWithTitle: @"Machine" action:nil keyEquivalent:@""] autorelease];
+ [menuItem setSubmenu:menu];
+ [[NSApp mainMenu] addItem:menuItem];
+
// View menu
menu = [[NSMenu alloc] initWithTitle:@"View"];
[menu addItem: [[[NSMenuItem alloc] initWithTitle:@"Enter Fullscreen" action:@selector(doToggleFullScreen:) keyEquivalent:@"f"] autorelease]]; // Fullscreen
@@ -1176,6 +1338,72 @@
}
}
+/* Make menu items for all removable devices.
+ * Each device is given an 'Eject' and 'Change' menu item.
+ */
+static void addRemovableDevicesMenuItems()
+{
+ NSMenu *menu;
+ NSMenuItem *menuItem;
+ BlockInfoList *currentDevice, *pointerToFree;
+ NSString *deviceName;
+
+ currentDevice = qmp_query_block(NULL);
+ pointerToFree = currentDevice;
+ if(currentDevice == NULL) {
+ NSBeep();
+ QEMU_Alert(@"Failed to query for block devices!");
+ return;
+ }
+
+ menu = [[[NSApp mainMenu] itemWithTitle:@"Machine"] submenu];
+
+ // Add a separator between related groups of menu items
+ [menu addItem:[NSMenuItem separatorItem]];
+
+ // Set the attributes to the "Removable Media" menu item
+ NSString *titleString = @"Removable Media";
+ NSMutableAttributedString *attString=[[NSMutableAttributedString alloc] initWithString:titleString];
+ NSColor *newColor = [NSColor blackColor];
+ NSFontManager *fontManager = [NSFontManager sharedFontManager];
+ NSFont *font = [fontManager fontWithFamily:@"Helvetica"
+ traits:NSBoldFontMask|NSItalicFontMask
+ weight:0
+ size:14];
+ [attString addAttribute:NSFontAttributeName value:font range:NSMakeRange(0, [titleString length])];
+ [attString addAttribute:NSForegroundColorAttributeName value:newColor range:NSMakeRange(0, [titleString length])];
+ [attString addAttribute:NSUnderlineStyleAttributeName value:[NSNumber numberWithInt: 1] range:NSMakeRange(0, [titleString length])];
+
+ // Add the "Removable Media" menu item
+ menuItem = [NSMenuItem new];
+ [menuItem setAttributedTitle: attString];
+ [menuItem setEnabled: NO];
+ [menu addItem: menuItem];
+
+ /* Loop thru all the block devices in the emulator */
+ while (currentDevice) {
+ deviceName = [[NSString stringWithFormat: @"%s", currentDevice->value->device] retain];
+
+ if(currentDevice->value->removable) {
+ menuItem = [[NSMenuItem alloc] initWithTitle: [NSString stringWithFormat: @"Change %s...", currentDevice->value->device]
+ action: @selector(changeDeviceMedia:)
+ keyEquivalent: @""];
+ [menu addItem: menuItem];
+ [menuItem setRepresentedObject: deviceName];
+ [menuItem autorelease];
+
+ menuItem = [[NSMenuItem alloc] initWithTitle: [NSString stringWithFormat: @"Eject %s", currentDevice->value->device]
+ action: @selector(ejectDeviceMedia:)
+ keyEquivalent: @""];
+ [menu addItem: menuItem];
+ [menuItem setRepresentedObject: deviceName];
+ [menuItem autorelease];
+ }
+ currentDevice = currentDevice->next;
+ }
+ qapi_free_BlockInfoList(pointerToFree);
+}
+
void cocoa_display_init(DisplayState *ds, int full_screen)
{
COCOA_DEBUG("qemu_cocoa: cocoa_display_init\n");
@@ -1199,4 +1427,10 @@
* menu entries for them.
*/
add_console_menu_entries();
+
+ /* Give all removable devices a menu item.
+ * Has to be called after QEMU has started to
+ * find out what removable devices it has.
+ */
+ addRemovableDevicesMenuItems();
}
diff --git a/vl.c b/vl.c
index c839071..0c2208f 100644
--- a/vl.c
+++ b/vl.c
@@ -119,6 +119,7 @@
#include "qapi/opts-visitor.h"
#include "qom/object_interfaces.h"
#include "qapi-event.h"
+#include "exec/semihost.h"
#define MAX_VIRTIO_CONSOLES 1
#define MAX_SCLP_CONSOLES 1
@@ -169,7 +170,6 @@
const char *watchdog;
QEMUOptionRom option_rom[MAX_OPTION_ROMS];
int nb_option_roms;
-int semihosting_enabled = 0;
int old_param = 0;
const char *qemu_name;
int alt_grab = 0;
@@ -488,6 +488,9 @@
}, {
.name = "target",
.type = QEMU_OPT_STRING,
+ }, {
+ .name = "arg",
+ .type = QEMU_OPT_STRING,
},
{ /* end of list */ }
},
@@ -1246,6 +1249,81 @@
}
/***********************************************************/
+/* Semihosting */
+
+typedef struct SemihostingConfig {
+ bool enabled;
+ SemihostingTarget target;
+ const char **argv;
+ int argc;
+ const char *cmdline; /* concatenated argv */
+} SemihostingConfig;
+
+static SemihostingConfig semihosting;
+
+bool semihosting_enabled(void)
+{
+ return semihosting.enabled;
+}
+
+SemihostingTarget semihosting_get_target(void)
+{
+ return semihosting.target;
+}
+
+const char *semihosting_get_arg(int i)
+{
+ if (i >= semihosting.argc) {
+ return NULL;
+ }
+ return semihosting.argv[i];
+}
+
+int semihosting_get_argc(void)
+{
+ return semihosting.argc;
+}
+
+const char *semihosting_get_cmdline(void)
+{
+ if (semihosting.cmdline == NULL && semihosting.argc > 0) {
+ semihosting.cmdline = g_strjoinv(" ", (gchar **)semihosting.argv);
+ }
+ return semihosting.cmdline;
+}
+
+static int add_semihosting_arg(void *opaque,
+ const char *name, const char *val,
+ Error **errp)
+{
+ SemihostingConfig *s = opaque;
+ if (strcmp(name, "arg") == 0) {
+ s->argc++;
+ /* one extra element as g_strjoinv() expects NULL-terminated array */
+ s->argv = g_realloc(s->argv, (s->argc + 1) * sizeof(void *));
+ s->argv[s->argc - 1] = val;
+ s->argv[s->argc] = NULL;
+ }
+ return 0;
+}
+
+/* Use strings passed via -kernel/-append to initialize semihosting.argv[] */
+static inline void semihosting_arg_fallback(const char *file, const char *cmd)
+{
+ char *cmd_token;
+
+ /* argv[0] */
+ add_semihosting_arg(&semihosting, "arg", file, NULL);
+
+ /* split -append and initialize argv[1..n] */
+ cmd_token = strtok(g_strdup(cmd), " ");
+ while (cmd_token) {
+ add_semihosting_arg(&semihosting, "arg", cmd_token, NULL);
+ cmd_token = strtok(NULL, " ");
+ }
+}
+
+/***********************************************************/
/* USB devices */
static int usb_device_add(const char *devname)
@@ -3653,24 +3731,24 @@
nb_option_roms++;
break;
case QEMU_OPTION_semihosting:
- semihosting_enabled = 1;
- semihosting_target = SEMIHOSTING_TARGET_AUTO;
+ semihosting.enabled = true;
+ semihosting.target = SEMIHOSTING_TARGET_AUTO;
break;
case QEMU_OPTION_semihosting_config:
- semihosting_enabled = 1;
+ semihosting.enabled = true;
opts = qemu_opts_parse(qemu_find_opts("semihosting-config"),
optarg, 0);
if (opts != NULL) {
- semihosting_enabled = qemu_opt_get_bool(opts, "enable",
+ semihosting.enabled = qemu_opt_get_bool(opts, "enable",
true);
const char *target = qemu_opt_get(opts, "target");
if (target != NULL) {
if (strcmp("native", target) == 0) {
- semihosting_target = SEMIHOSTING_TARGET_NATIVE;
+ semihosting.target = SEMIHOSTING_TARGET_NATIVE;
} else if (strcmp("gdb", target) == 0) {
- semihosting_target = SEMIHOSTING_TARGET_GDB;
+ semihosting.target = SEMIHOSTING_TARGET_GDB;
} else if (strcmp("auto", target) == 0) {
- semihosting_target = SEMIHOSTING_TARGET_AUTO;
+ semihosting.target = SEMIHOSTING_TARGET_AUTO;
} else {
fprintf(stderr, "Unsupported semihosting-config"
" %s\n",
@@ -3678,8 +3756,11 @@
exit(1);
}
} else {
- semihosting_target = SEMIHOSTING_TARGET_AUTO;
+ semihosting.target = SEMIHOSTING_TARGET_AUTO;
}
+ /* Set semihosting argument count and vector */
+ qemu_opt_foreach(opts, add_semihosting_arg,
+ &semihosting, NULL);
} else {
fprintf(stderr, "Unsupported semihosting-config %s\n",
optarg);
@@ -3947,17 +4028,14 @@
exit(0);
}
- /* Open the logfile at this point, if necessary. We can't open the logfile
- * when encountering either of the logging options (-d or -D) because the
- * other one may be encountered later on the command line, changing the
- * location or level of logging.
+ /* Open the logfile at this point and set the log mask if necessary.
*/
+ if (log_file) {
+ qemu_set_log_filename(log_file);
+ }
+
if (log_mask) {
int mask;
- if (log_file) {
- qemu_set_log_filename(log_file);
- }
-
mask = qemu_str_to_log_mask(log_mask);
if (!mask) {
qemu_print_log_usage(stdout);
@@ -4255,6 +4333,11 @@
exit(1);
}
+ if (semihosting_enabled() && !semihosting_get_argc() && kernel_filename) {
+ /* fall back to the -kernel/-append */
+ semihosting_arg_fallback(kernel_filename, kernel_cmdline);
+ }
+
os_set_line_buffering();
#ifdef CONFIG_SPICE
