commit 0b4232f10895e863b1759a93ba0d0a1b3380dc31
author Richard Henderson <rth@twiddle.net> Wed Sep 23 10:19:44 2015 -0700
committer Richard Henderson <rth@twiddle.net> Wed Oct 07 20:03:14 2015 +1100
tree 5b3263e26735aebe8754a70df72378454b3ab34c
parent ba1fc78f65fdea9d4b14d6449514c1351ad64fa4

target-tilegx: Implement table index instructions

Signed-off-by: Richard Henderson <rth@twiddle.net>

target-tilegx/translate.c

diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 3e5a8ea..9f86fd3 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -627,12 +627,27 @@
         break;
     case OE_RR_X0(TBLIDXB0):
     case OE_RR_Y0(TBLIDXB0):
+        tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tsrca, 2, 8);
+        mnemonic = "tblidxb0";
+        break;
     case OE_RR_X0(TBLIDXB1):
     case OE_RR_Y0(TBLIDXB1):
+        tcg_gen_shri_tl(tdest, tsrca, 8);
+        tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
+        mnemonic = "tblidxb1";
+        break;
     case OE_RR_X0(TBLIDXB2):
     case OE_RR_Y0(TBLIDXB2):
+        tcg_gen_shri_tl(tdest, tsrca, 16);
+        tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
+        mnemonic = "tblidxb2";
+        break;
     case OE_RR_X0(TBLIDXB3):
     case OE_RR_Y0(TBLIDXB3):
+        tcg_gen_shri_tl(tdest, tsrca, 24);
+        tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
+        mnemonic = "tblidxb3";
+        break;
     default:
         return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
     }