)]}'
{
  "commit": "105a060188dc6fdd4551571a966514d1a5f6815a",
  "tree": "cd81d4bb0a23d8db9e47171e293d4160b509d7a8",
  "parents": [
    "3e890c77cf038d8c2de66ed7996fe77a6f94787c",
    "2ea5a2ca1f1dc302652d2ad5035e0b209ccaa177"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Feb 21 15:04:57 2014 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Feb 21 15:04:58 2014 +0000"
  },
  "message": "Merge remote-tracking branch \u0027remotes/pmaydell/tags/pull-target-arm-20140220\u0027 into staging\n\ntarget-arm queue:\n * Fix a bug causing an assertion in the NVIC on ARMv7M models\n * More A64 Neon instructions\n * Refactor cpreg API to separate out access check functions, as\n   groundwork for AArch64 system mode\n * Fix bug in linux-user A64 store-exclusive of XZR\n\n# gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n\n* remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits)\n  linux-user: AArch64: Fix exclusive store of the zero register\n  target-arm: A64: Implement unprivileged load/store\n  target-arm: A64: Implement narrowing three-reg-diff operations\n  target-arm: A64: Implement the wide 3-reg-different operations\n  target-arm: A64: Add most remaining three-reg-diff widening ops\n  target-arm: A64: Add opcode comments to disas_simd_three_reg_diff\n  target-arm: A64: Implement store-exclusive for system mode\n  target-arm: Fix incorrect type for value argument to write_raw_cp_reg\n  target-arm: Remove failure status return from read/write_raw_cp_reg\n  target-arm: Remove unnecessary code now read/write fns can\u0027t fail\n  target-arm: Drop success/fail return from cpreg read and write functions\n  target-arm: Convert miscellaneous reginfo structs to accessfn\n  target-arm: Convert generic timer reginfo to accessfn\n  target-arm: Convert performance monitor reginfo to accessfn\n  target-arm: Split cpreg access checks out from read/write functions\n  target-arm: Stop underdecoding ARM946 PRBS registers\n  target-arm: Log bad system register accesses with LOG_UNIMP\n  target-arm: Remove unused ARMCPUState sr substruct\n  target-arm: Restrict check_ap() use of S and R bits to v6 and earlier\n  target-arm: Define names for SCTLR bits\n  ...\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}