tree 5418c048f1c669eee80221251d9466fb48575cc0
parent 95df61e6238c79c2dc14f2bffa76abb2bd3acba7
author Richard Henderson <rth@twiddle.net> 1443666772 +1000
committer Richard Henderson <rth@twiddle.net> 1444208596 +1100

target-tilegx: Handle nofault prefetch instructions

These are mapped onto some of the normal load instructions, when the
destination is the zero register.  Other load insns do fault even
when targeting the zero register.

Signed-off-by: Richard Henderson <rth@twiddle.net>