blob: b28e0521b46bc955d7e4064e5544117a6b8a04c6 [file] [log] [blame]
/*
* TI OMAP processors emulation.
*
* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "hw/hw.h"
#include "hw/arm/arm.h"
#include "hw/arm/omap.h"
#include "sysemu/sysemu.h"
#include "hw/arm/soc_dma.h"
#include "sysemu/blockdev.h"
#include "qemu/range.h"
#include "hw/sysbus.h"
/* Should signal the TCMI/GPMC */
uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
{
uint8_t ret;
OMAP_8B_REG(addr);
cpu_physical_memory_read(addr, &ret, 1);
return ret;
}
void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value)
{
uint8_t val8 = value;
OMAP_8B_REG(addr);
cpu_physical_memory_write(addr, &val8, 1);
}
uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
{
uint16_t ret;
OMAP_16B_REG(addr);
cpu_physical_memory_read(addr, &ret, 2);
return ret;
}
void omap_badwidth_write16(void *opaque, hwaddr addr,
uint32_t value)
{
uint16_t val16 = value;
OMAP_16B_REG(addr);
cpu_physical_memory_write(addr, &val16, 2);
}
uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
{
uint32_t ret;
OMAP_32B_REG(addr);
cpu_physical_memory_read(addr, &ret, 4);
return ret;
}
void omap_badwidth_write32(void *opaque, hwaddr addr,
uint32_t value)
{
OMAP_32B_REG(addr);
cpu_physical_memory_write(addr, &value, 4);
}
/* MPU OS timers */
struct omap_mpu_timer_s {
MemoryRegion iomem;
qemu_irq irq;
omap_clk clk;
uint32_t val;
int64_t time;
QEMUTimer *timer;
QEMUBH *tick;
int64_t rate;
int it_ena;
int enable;
int ptv;
int ar;
int st;
uint32_t reset_val;
};
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
{
uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
if (timer->st && timer->enable && timer->rate)
return timer->val - muldiv64(distance >> (timer->ptv + 1),
timer->rate, get_ticks_per_sec());
else
return timer->val;
}
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
{
timer->val = omap_timer_read(timer);
timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
{
int64_t expires;
if (timer->enable && timer->st && timer->rate) {
timer->val = timer->reset_val; /* Should skip this on clk enable */
expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
get_ticks_per_sec(), timer->rate);
/* If timer expiry would be sooner than in about 1 ms and
* auto-reload isn't set, then fire immediately. This is a hack
* to make systems like PalmOS run in acceptable time. PalmOS
* sets the interval to a very low value and polls the status bit
* in a busy loop when it wants to sleep just a couple of CPU
* ticks. */
if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
timer_mod(timer->timer, timer->time + expires);
else
qemu_bh_schedule(timer->tick);
} else
timer_del(timer->timer);
}
static void omap_timer_fire(void *opaque)
{
struct omap_mpu_timer_s *timer = opaque;
if (!timer->ar) {
timer->val = 0;
timer->st = 0;
}
if (timer->it_ena)
/* Edge-triggered irq */
qemu_irq_pulse(timer->irq);
}
static void omap_timer_tick(void *opaque)
{
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
omap_timer_sync(timer);
omap_timer_fire(timer);
omap_timer_update(timer);
}
static void omap_timer_clk_update(void *opaque, int line, int on)
{
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
omap_timer_sync(timer);
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
omap_timer_update(timer);
}
static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
{
omap_clk_adduser(timer->clk,
qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
timer->rate = omap_clk_getrate(timer->clk);
}
static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
case 0x04: /* LOAD_TIM */
break;
case 0x08: /* READ_TIM */
return omap_timer_read(s);
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_mpu_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(s);
s->enable = (value >> 5) & 1;
s->ptv = (value >> 2) & 7;
s->ar = (value >> 1) & 1;
s->st = value & 1;
omap_timer_update(s);
return;
case 0x04: /* LOAD_TIM */
s->reset_val = value;
return;
case 0x08: /* READ_TIM */
OMAP_RO_REG(addr);
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_mpu_timer_ops = {
.read = omap_mpu_timer_read,
.write = omap_mpu_timer_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
{
timer_del(s->timer);
s->enable = 0;
s->reset_val = 31337;
s->val = 0;
s->ptv = 0;
s->ar = 0;
s->st = 0;
s->it_ena = 1;
}
static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
g_malloc0(sizeof(struct omap_mpu_timer_s));
s->irq = irq;
s->clk = clk;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
s->tick = qemu_bh_new(omap_timer_fire, s);
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
"omap-mpu-timer", 0x100);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
/* Watchdog timer */
struct omap_watchdog_timer_s {
struct omap_mpu_timer_s timer;
MemoryRegion iomem;
uint8_t last_wr;
int mode;
int free;
int reset;
};
static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->timer.ptv << 9) | (s->timer.ar << 8) |
(s->timer.st << 7) | (s->free << 1);
case 0x04: /* READ_TIMER */
return omap_timer_read(&s->timer);
case 0x08: /* TIMER_MODE */
return s->mode << 15;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_wd_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(&s->timer);
s->timer.ptv = (value >> 9) & 7;
s->timer.ar = (value >> 8) & 1;
s->timer.st = (value >> 7) & 1;
s->free = (value >> 1) & 1;
omap_timer_update(&s->timer);
break;
case 0x04: /* LOAD_TIMER */
s->timer.reset_val = value & 0xffff;
break;
case 0x08: /* TIMER_MODE */
if (!s->mode && ((value >> 15) & 1))
omap_clk_get(s->timer.clk);
s->mode |= (value >> 15) & 1;
if (s->last_wr == 0xf5) {
if ((value & 0xff) == 0xa0) {
if (s->mode) {
s->mode = 0;
omap_clk_put(s->timer.clk);
}
} else {
/* XXX: on T|E hardware somehow this has no effect,
* on Zire 71 it works as specified. */
s->reset = 1;
qemu_system_reset_request();
}
}
s->last_wr = value & 0xff;
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_wd_timer_ops = {
.read = omap_wd_timer_read,
.write = omap_wd_timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
{
timer_del(s->timer.timer);
if (!s->mode)
omap_clk_get(s->timer.clk);
s->mode = 1;
s->free = 1;
s->reset = 0;
s->timer.enable = 1;
s->timer.it_ena = 1;
s->timer.reset_val = 0xffff;
s->timer.val = 0;
s->timer.st = 0;
s->timer.ptv = 0;
s->timer.ar = 0;
omap_timer_update(&s->timer);
}
static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
g_malloc0(sizeof(struct omap_watchdog_timer_s));
s->timer.irq = irq;
s->timer.clk = clk;
s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
"omap-wd-timer", 0x100);
memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* 32-kHz timer */
struct omap_32khz_timer_s {
struct omap_mpu_timer_s timer;
MemoryRegion iomem;
};
static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (offset) {
case 0x00: /* TVR */
return s->timer.reset_val;
case 0x04: /* TCR */
return omap_timer_read(&s->timer);
case 0x08: /* CR */
return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
default:
break;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_os_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (offset) {
case 0x00: /* TVR */
s->timer.reset_val = value & 0x00ffffff;
break;
case 0x04: /* TCR */
OMAP_RO_REG(addr);
break;
case 0x08: /* CR */
s->timer.ar = (value >> 3) & 1;
s->timer.it_ena = (value >> 2) & 1;
if (s->timer.st != (value & 1) || (value & 2)) {
omap_timer_sync(&s->timer);
s->timer.enable = value & 1;
s->timer.st = value & 1;
omap_timer_update(&s->timer);
}
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_os_timer_ops = {
.read = omap_os_timer_read,
.write = omap_os_timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
{
timer_del(s->timer.timer);
s->timer.enable = 0;
s->timer.it_ena = 0;
s->timer.reset_val = 0x00ffffff;
s->timer.val = 0;
s->timer.st = 0;
s->timer.ptv = 0;
s->timer.ar = 1;
}
static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
g_malloc0(sizeof(struct omap_32khz_timer_s));
s->timer.irq = irq;
s->timer.clk = clk;
s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
"omap-os-timer", 0x800);
memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* Ultra Low-Power Device Module */
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
s->ulpd_pm_regs[addr >> 2] = 0;
qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
return ret;
case 0x18: /* Reserved */
case 0x1c: /* Reserved */
case 0x20: /* Reserved */
case 0x28: /* Reserved */
case 0x2c: /* Reserved */
OMAP_BAD_REG(addr);
/* fall through */
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
case 0x10: /* GAUGING_CTRL */
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
case 0x30: /* CLOCK_CTRL */
case 0x34: /* SOFT_REQ */
case 0x38: /* COUNTER_32_FIQ */
case 0x3c: /* DPLL_CTRL */
case 0x40: /* STATUS_REQ */
/* XXX: check clk::usecount state for every clock */
case 0x48: /* LOCL_TIME */
case 0x4c: /* APLL_CTRL */
case 0x50: /* POWER_CTRL */
return s->ulpd_pm_regs[addr >> 2];
}
OMAP_BAD_REG(addr);
return 0;
}
static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
if (diff & (1 << 4)) /* USB_MCLK_EN */
omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
}
static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
if (diff & (1 << 1)) /* SOFT_COM_REQ */
omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
if (diff & (1 << 2)) /* SOFT_SDW_REQ */
omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
if (diff & (1 << 3)) /* SOFT_USB_REQ */
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int64_t now, ticks;
int div, mult;
static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
case 0x08: /* COUNTER_HIGH_FREQ_LSB */
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
case 0x14: /* IT_STATUS */
case 0x40: /* STATUS_REQ */
OMAP_RO_REG(addr);
break;
case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & 1)
s->ulpd_gauge_start = now;
else {
now -= s->ulpd_gauge_start;
/* 32-kHz ticks */
ticks = muldiv64(now, 32768, get_ticks_per_sec());
s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_32K */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
/* High frequency ticks */
ticks = muldiv64(now, 12000000, get_ticks_per_sec());
s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
if (ticks >> 32) /* OVERFLOW_HI_FREQ */
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
}
}
s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x18: /* Reserved */
case 0x1c: /* Reserved */
case 0x20: /* Reserved */
case 0x28: /* Reserved */
case 0x2c: /* Reserved */
OMAP_BAD_REG(addr);
/* fall through */
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
case 0x38: /* COUNTER_32_FIQ */
case 0x48: /* LOCL_TIME */
case 0x50: /* POWER_CTRL */
s->ulpd_pm_regs[addr >> 2] = value;
break;
case 0x30: /* CLOCK_CTRL */
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
omap_ulpd_clk_update(s, diff, value);
break;
case 0x34: /* SOFT_REQ */
diff = s->ulpd_pm_regs[addr >> 2] ^ value;
s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
omap_ulpd_req_update(s, diff, value);
break;
case 0x3c: /* DPLL_CTRL */
/* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
* omitted altogether, probably a typo. */
/* This register has identical semantics with DPLL(1:3) control
* registers, see omap_dpll_write() */
diff = s->ulpd_pm_regs[addr >> 2] & value;
s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
if (diff & (0x3ff << 2)) {
if (value & (1 << 4)) { /* PLL_ENABLE */
div = ((value >> 5) & 3) + 1; /* PLL_DIV */
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
} else {
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
mult = 1;
}
omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
}
/* Enter the desired mode. */
s->ulpd_pm_regs[addr >> 2] =
(s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
/* Act as if the lock is restored. */
s->ulpd_pm_regs[addr >> 2] |= 2;
break;
case 0x4c: /* APLL_CTRL */
diff = s->ulpd_pm_regs[addr >> 2] & value;
s->ulpd_pm_regs[addr >> 2] = value & 0xf;
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
(value & (1 << 0)) ? "apll" : "dpll4"));
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_ulpd_pm_ops = {
.read = omap_ulpd_pm_read,
.write = omap_ulpd_pm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
{
mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
}
static void omap_ulpd_pm_init(MemoryRegion *system_memory,
hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
"omap-ulpd-pm", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
omap_ulpd_pm_reset(mpu);
}
/* OMAP Pin Configuration */
static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
case 0x04: /* FUNC_MUX_CTRL_1 */
case 0x08: /* FUNC_MUX_CTRL_2 */
return s->func_mux_ctrl[addr >> 2];
case 0x0c: /* COMP_MODE_CTRL_0 */
return s->comp_mode_ctrl[0];
case 0x10: /* FUNC_MUX_CTRL_3 */
case 0x14: /* FUNC_MUX_CTRL_4 */
case 0x18: /* FUNC_MUX_CTRL_5 */
case 0x1c: /* FUNC_MUX_CTRL_6 */
case 0x20: /* FUNC_MUX_CTRL_7 */
case 0x24: /* FUNC_MUX_CTRL_8 */
case 0x28: /* FUNC_MUX_CTRL_9 */
case 0x2c: /* FUNC_MUX_CTRL_A */
case 0x30: /* FUNC_MUX_CTRL_B */
case 0x34: /* FUNC_MUX_CTRL_C */
case 0x38: /* FUNC_MUX_CTRL_D */
return s->func_mux_ctrl[(addr >> 2) - 1];
case 0x40: /* PULL_DWN_CTRL_0 */
case 0x44: /* PULL_DWN_CTRL_1 */
case 0x48: /* PULL_DWN_CTRL_2 */
case 0x4c: /* PULL_DWN_CTRL_3 */
return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
case 0x50: /* GATE_INH_CTRL_0 */
return s->gate_inh_ctrl[0];
case 0x60: /* VOLTAGE_CTRL_0 */
return s->voltage_ctrl[0];
case 0x70: /* TEST_DBG_CTRL_0 */
return s->test_dbg_ctrl[0];
case 0x80: /* MOD_CONF_CTRL_0 */
return s->mod_conf_ctrl[0];
}
OMAP_BAD_REG(addr);
return 0;
}
static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
uint32_t diff, uint32_t value)
{
if (s->compat1509) {
if (diff & (1 << 9)) /* BLUETOOTH */
omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
(~value >> 9) & 1);
if (diff & (1 << 7)) /* USB.CLKO */
omap_clk_onoff(omap_findclk(s, "usb.clko"),
(value >> 7) & 1);
}
}
static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
uint32_t diff, uint32_t value)
{
if (s->compat1509) {
if (diff & (1U << 31)) {
/* MCBSP3_CLK_HIZ_DI */
omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
}
if (diff & (1 << 1)) {
/* CLK32K */
omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
}
}
}
static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
uint32_t diff, uint32_t value)
{
if (diff & (1U << 31)) {
/* CONF_MOD_UART3_CLK_MODE_R */
omap_clk_reparent(omap_findclk(s, "uart3_ck"),
omap_findclk(s, ((value >> 31) & 1) ?
"ck_48m" : "armper_ck"));
}
if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
omap_clk_reparent(omap_findclk(s, "uart2_ck"),
omap_findclk(s, ((value >> 30) & 1) ?
"ck_48m" : "armper_ck"));
if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
omap_clk_reparent(omap_findclk(s, "uart1_ck"),
omap_findclk(s, ((value >> 29) & 1) ?
"ck_48m" : "armper_ck"));
if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
omap_clk_reparent(omap_findclk(s, "mmc_ck"),
omap_findclk(s, ((value >> 23) & 1) ?
"ck_48m" : "armper_ck"));
if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
omap_findclk(s, ((value >> 12) & 1) ?
"ck_48m" : "armper_ck"));
if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t diff;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
diff = s->func_mux_ctrl[addr >> 2] ^ value;
s->func_mux_ctrl[addr >> 2] = value;
omap_pin_funcmux0_update(s, diff, value);
return;
case 0x04: /* FUNC_MUX_CTRL_1 */
diff = s->func_mux_ctrl[addr >> 2] ^ value;
s->func_mux_ctrl[addr >> 2] = value;
omap_pin_funcmux1_update(s, diff, value);
return;
case 0x08: /* FUNC_MUX_CTRL_2 */
s->func_mux_ctrl[addr >> 2] = value;
return;
case 0x0c: /* COMP_MODE_CTRL_0 */
s->comp_mode_ctrl[0] = value;
s->compat1509 = (value != 0x0000eaef);
omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
return;
case 0x10: /* FUNC_MUX_CTRL_3 */
case 0x14: /* FUNC_MUX_CTRL_4 */
case 0x18: /* FUNC_MUX_CTRL_5 */
case 0x1c: /* FUNC_MUX_CTRL_6 */
case 0x20: /* FUNC_MUX_CTRL_7 */
case 0x24: /* FUNC_MUX_CTRL_8 */
case 0x28: /* FUNC_MUX_CTRL_9 */
case 0x2c: /* FUNC_MUX_CTRL_A */
case 0x30: /* FUNC_MUX_CTRL_B */
case 0x34: /* FUNC_MUX_CTRL_C */
case 0x38: /* FUNC_MUX_CTRL_D */
s->func_mux_ctrl[(addr >> 2) - 1] = value;
return;
case 0x40: /* PULL_DWN_CTRL_0 */
case 0x44: /* PULL_DWN_CTRL_1 */
case 0x48: /* PULL_DWN_CTRL_2 */
case 0x4c: /* PULL_DWN_CTRL_3 */
s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
return;
case 0x50: /* GATE_INH_CTRL_0 */
s->gate_inh_ctrl[0] = value;
return;
case 0x60: /* VOLTAGE_CTRL_0 */
s->voltage_ctrl[0] = value;
return;
case 0x70: /* TEST_DBG_CTRL_0 */
s->test_dbg_ctrl[0] = value;
return;
case 0x80: /* MOD_CONF_CTRL_0 */
diff = s->mod_conf_ctrl[0] ^ value;
s->mod_conf_ctrl[0] = value;
omap_pin_modconf1_update(s, diff, value);
return;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_pin_cfg_ops = {
.read = omap_pin_cfg_read,
.write = omap_pin_cfg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
{
/* Start in Compatibility Mode. */
mpu->compat1509 = 1;
omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
}
static void omap_pin_cfg_init(MemoryRegion *system_memory,
hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
"omap-pin-cfg", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
omap_pin_cfg_reset(mpu);
}
/* Device Identification, Die Identification */
static uint64_t omap_id_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0xfffe1800: /* DIE_ID_LSB */
return 0xc9581f0e;
case 0xfffe1804: /* DIE_ID_MSB */
return 0xa8858bfa;
case 0xfffe2000: /* PRODUCT_ID_LSB */
return 0x00aaaafc;
case 0xfffe2004: /* PRODUCT_ID_MSB */
return 0xcafeb574;
case 0xfffed400: /* JTAG_ID_LSB */
switch (s->mpu_model) {
case omap310:
return 0x03310315;
case omap1510:
return 0x03310115;
default:
hw_error("%s: bad mpu model\n", __FUNCTION__);
}
break;
case 0xfffed404: /* JTAG_ID_MSB */
switch (s->mpu_model) {
case omap310:
return 0xfb57402f;
case omap1510:
return 0xfb47002f;
default:
hw_error("%s: bad mpu model\n", __FUNCTION__);
}
break;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_id_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
OMAP_BAD_REG(addr);
}
static const MemoryRegionOps omap_id_ops = {
.read = omap_id_read,
.write = omap_id_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
"omap-id", 0x100000000ULL);
memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
0xfffe1800, 0x800);
memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
0xfffed400, 0x100);
memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
if (!cpu_is_omap15xx(mpu)) {
memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
&mpu->id_iomem, 0xfffe2000, 0x800);
memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
}
}
/* MPUI Control (Dummy) */
static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* CTRL */
return s->mpui_ctrl;
case 0x04: /* DEBUG_ADDR */
return 0x01ffffff;
case 0x08: /* DEBUG_DATA */
return 0xffffffff;
case 0x0c: /* DEBUG_FLAG */
return 0x00000800;
case 0x10: /* STATUS */
return 0x00000000;
/* Not in OMAP310 */
case 0x14: /* DSP_STATUS */
case 0x18: /* DSP_BOOT_CONFIG */
return 0x00000000;
case 0x1c: /* DSP_MPUI_CONFIG */
return 0x0000ffff;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_mpui_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* CTRL */
s->mpui_ctrl = value & 0x007fffff;
break;
case 0x04: /* DEBUG_ADDR */
case 0x08: /* DEBUG_DATA */
case 0x0c: /* DEBUG_FLAG */
case 0x10: /* STATUS */
/* Not in OMAP310 */
case 0x14: /* DSP_STATUS */
OMAP_RO_REG(addr);
break;
case 0x18: /* DSP_BOOT_CONFIG */
case 0x1c: /* DSP_MPUI_CONFIG */
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_mpui_ops = {
.read = omap_mpui_read,
.write = omap_mpui_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpui_reset(struct omap_mpu_state_s *s)
{
s->mpui_ctrl = 0x0003ff1b;
}
static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
"omap-mpui", 0x100);
memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
omap_mpui_reset(mpu);
}
/* TIPB Bridges */
struct omap_tipb_bridge_s {
qemu_irq abort;
MemoryRegion iomem;
int width_intr;
uint16_t control;
uint16_t alloc;
uint16_t buffer;
uint16_t enh_control;
};
static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
if (size < 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* TIPB_CNTL */
return s->control;
case 0x04: /* TIPB_BUS_ALLOC */
return s->alloc;
case 0x08: /* MPU_TIPB_CNTL */
return s->buffer;
case 0x0c: /* ENHANCED_TIPB_CNTL */
return s->enh_control;
case 0x10: /* ADDRESS_DBG */
case 0x14: /* DATA_DEBUG_LOW */
case 0x18: /* DATA_DEBUG_HIGH */
return 0xffff;
case 0x1c: /* DEBUG_CNTR_SIG */
return 0x00f8;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
if (size < 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x00: /* TIPB_CNTL */
s->control = value & 0xffff;
break;
case 0x04: /* TIPB_BUS_ALLOC */
s->alloc = value & 0x003f;
break;
case 0x08: /* MPU_TIPB_CNTL */
s->buffer = value & 0x0003;
break;
case 0x0c: /* ENHANCED_TIPB_CNTL */
s->width_intr = !(value & 2);
s->enh_control = value & 0x000f;
break;
case 0x10: /* ADDRESS_DBG */
case 0x14: /* DATA_DEBUG_LOW */
case 0x18: /* DATA_DEBUG_HIGH */
case 0x1c: /* DEBUG_CNTR_SIG */
OMAP_RO_REG(addr);
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_tipb_bridge_ops = {
.read = omap_tipb_bridge_read,
.write = omap_tipb_bridge_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
{
s->control = 0xffff;
s->alloc = 0x0009;
s->buffer = 0x0000;
s->enh_control = 0x000f;
}
static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
g_malloc0(sizeof(struct omap_tipb_bridge_s));
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
"omap-tipb-bridge", 0x100);
memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* Dummy Traffic Controller's Memory Interface */
static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t ret;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
case 0x08: /* EMIFF_PRIO */
case 0x0c: /* EMIFS_CONFIG */
case 0x10: /* EMIFS_CS0_CONFIG */
case 0x14: /* EMIFS_CS1_CONFIG */
case 0x18: /* EMIFS_CS2_CONFIG */
case 0x1c: /* EMIFS_CS3_CONFIG */
case 0x24: /* EMIFF_MRS */
case 0x28: /* TIMEOUT1 */
case 0x2c: /* TIMEOUT2 */
case 0x30: /* TIMEOUT3 */
case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
case 0x40: /* EMIFS_CFG_DYN_WAIT */
return s->tcmi_regs[addr >> 2];
case 0x20: /* EMIFF_SDRAM_CONFIG */
ret = s->tcmi_regs[addr >> 2];
s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
/* XXX: We can try using the VGA_DIRTY flag for this */
return ret;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_tcmi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
case 0x08: /* EMIFF_PRIO */
case 0x10: /* EMIFS_CS0_CONFIG */
case 0x14: /* EMIFS_CS1_CONFIG */
case 0x18: /* EMIFS_CS2_CONFIG */
case 0x1c: /* EMIFS_CS3_CONFIG */
case 0x20: /* EMIFF_SDRAM_CONFIG */
case 0x24: /* EMIFF_MRS */
case 0x28: /* TIMEOUT1 */
case 0x2c: /* TIMEOUT2 */
case 0x30: /* TIMEOUT3 */
case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
case 0x40: /* EMIFS_CFG_DYN_WAIT */
s->tcmi_regs[addr >> 2] = value;
break;
case 0x0c: /* EMIFS_CONFIG */
s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_tcmi_ops = {
.read = omap_tcmi_read,
.write = omap_tcmi_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
{
mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
"omap-tcmi", 0x100);
memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
omap_tcmi_reset(mpu);
}
/* Digital phase-locked loops control */
struct dpll_ctl_s {
MemoryRegion iomem;
uint16_t mode;
omap_clk dpll;
};
static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
if (addr == 0x00) /* CTL_REG */
return s->mode;
OMAP_BAD_REG(addr);
return 0;
}
static void omap_dpll_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
uint16_t diff;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
if (addr == 0x00) { /* CTL_REG */
/* See omap_ulpd_pm_write() too */
diff = s->mode & value;
s->mode = value & 0x2fff;
if (diff & (0x3ff << 2)) {
if (value & (1 << 4)) { /* PLL_ENABLE */
div = ((value >> 5) & 3) + 1; /* PLL_DIV */
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
} else {
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
mult = 1;
}
omap_clk_setrate(s->dpll, div, mult);
}
/* Enter the desired mode. */
s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
/* Act as if the lock is restored. */
s->mode |= 2;
} else {
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_dpll_ops = {
.read = omap_dpll_read,
.write = omap_dpll_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_dpll_reset(struct dpll_ctl_s *s)
{
s->mode = 0x2002;
omap_clk_setrate(s->dpll, 1, 1);
}
static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
hwaddr base, omap_clk clk)
{
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* MPU Clock/Reset/Power Mode Control */
static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x00: /* ARM_CKCTL */
return s->clkm.arm_ckctl;
case 0x04: /* ARM_IDLECT1 */
return s->clkm.arm_idlect1;
case 0x08: /* ARM_IDLECT2 */
return s->clkm.arm_idlect2;
case 0x0c: /* ARM_EWUPCT */
return s->clkm.arm_ewupct;
case 0x10: /* ARM_RSTCT1 */
return s->clkm.arm_rstct1;
case 0x14: /* ARM_RSTCT2 */
return s->clkm.arm_rstct2;
case 0x18: /* ARM_SYSST */
return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
case 0x1c: /* ARM_CKOUT1 */
return s->clkm.arm_ckout1;
case 0x20: /* ARM_CKOUT2 */
break;
}
OMAP_BAD_REG(addr);
return 0;
}
static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
omap_clk clk;
if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
if (value & (1 << 14))
/* Reserved */;
else {
clk = omap_findclk(s, "arminth_ck");
omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
}
}
if (diff & (1 << 12)) { /* ARM_TIMXO */
clk = omap_findclk(s, "armtim_ck");
if (value & (1 << 12))
omap_clk_reparent(clk, omap_findclk(s, "clkin"));
else
omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
}
/* XXX: en_dspck */
if (diff & (3 << 10)) { /* DSPMMUDIV */
clk = omap_findclk(s, "dspmmu_ck");
omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
}
if (diff & (3 << 8)) { /* TCDIV */
clk = omap_findclk(s, "tc_ck");
omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
}
if (diff & (3 << 6)) { /* DSPDIV */
clk = omap_findclk(s, "dsp_ck");
omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
}
if (diff & (3 << 4)) { /* ARMDIV */
clk = omap_findclk(s, "arm_ck");
omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
}
if (diff & (3 << 2)) { /* LCDDIV */
clk = omap_findclk(s, "lcd_ck");
omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
}
if (diff & (3 << 0)) { /* PERDIV */
clk = omap_findclk(s, "armper_ck");
omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
}
}
static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
omap_clk clk;
if (value & (1 << 11)) { /* SETARM_IDLE */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
}
if (!(value & (1 << 10))) /* WKUP_MODE */
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
#define SET_CANIDLE(clock, bit) \
if (diff & (1 << bit)) { \
clk = omap_findclk(s, clock); \
omap_clk_canidle(clk, (value >> bit) & 1); \
}
SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
}
static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
omap_clk clk;
#define SET_ONOFF(clock, bit) \
if (diff & (1 << bit)) { \
clk = omap_findclk(s, clock); \
omap_clk_onoff(clk, (value >> bit) & 1); \
}
SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
SET_ONOFF("lb_ck", 4) /* EN_LBCK */
SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
SET_ONOFF("mpui_ck", 6) /* EN_APICK */
SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
}
static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
omap_clk clk;
if (diff & (3 << 4)) { /* TCLKOUT */
clk = omap_findclk(s, "tclk_out");
switch ((value >> 4) & 3) {
case 1:
omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
omap_clk_onoff(clk, 1);
break;
case 2:
omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
omap_clk_onoff(clk, 1);
break;
default:
omap_clk_onoff(clk, 0);
}
}
if (diff & (3 << 2)) { /* DCLKOUT */
clk = omap_findclk(s, "dclk_out");
switch ((value >> 2) & 3) {
case 0:
omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
break;
case 1:
omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
break;
case 2:
omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
break;
case 3:
omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
break;
}
}
if (diff & (3 << 0)) { /* ACLKOUT */
clk = omap_findclk(s, "aclk_out");
switch ((value >> 0) & 3) {
case 1:
omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
omap_clk_onoff(clk, 1);
break;
case 2:
omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
omap_clk_onoff(clk, 1);
break;
case 3:
omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
omap_clk_onoff(clk, 1);
break;
default:
omap_clk_onoff(clk, 0);
}
}
}
static void omap_clkm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
omap_clk clk;
static const char *clkschemename[8] = {
"fully synchronous", "fully asynchronous", "synchronous scalable",
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
};
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x00: /* ARM_CKCTL */
diff = s->clkm.arm_ckctl ^ value;
s->clkm.arm_ckctl = value & 0x7fff;
omap_clkm_ckctl_update(s, diff, value);
return;
case 0x04: /* ARM_IDLECT1 */
diff = s->clkm.arm_idlect1 ^ value;
s->clkm.arm_idlect1 = value & 0x0fff;
omap_clkm_idlect1_update(s, diff, value);
return;
case 0x08: /* ARM_IDLECT2 */
diff = s->clkm.arm_idlect2 ^ value;
s->clkm.arm_idlect2 = value & 0x07ff;
omap_clkm_idlect2_update(s, diff, value);
return;
case 0x0c: /* ARM_EWUPCT */
s->clkm.arm_ewupct = value & 0x003f;
return;
case 0x10: /* ARM_RSTCT1 */
diff = s->clkm.arm_rstct1 ^ value;
s->clkm.arm_rstct1 = value & 0x0007;
if (value & 9) {
qemu_system_reset_request();
s->clkm.cold_start = 0xa;
}
if (diff & ~value & 4) { /* DSP_RST */
omap_mpui_reset(s);
omap_tipb_bridge_reset(s->private_tipb);
omap_tipb_bridge_reset(s->public_tipb);
}
if (diff & 2) { /* DSP_EN */
clk = omap_findclk(s, "dsp_ck");
omap_clk_canidle(clk, (~value >> 1) & 1);
}
return;
case 0x14: /* ARM_RSTCT2 */
s->clkm.arm_rstct2 = value & 0x0001;
return;
case 0x18: /* ARM_SYSST */
if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
s->clkm.clocking_scheme = (value >> 11) & 7;
printf("%s: clocking scheme set to %s\n", __FUNCTION__,
clkschemename[s->clkm.clocking_scheme]);
}
s->clkm.cold_start &= value & 0x3f;
return;
case 0x1c: /* ARM_CKOUT1 */
diff = s->clkm.arm_ckout1 ^ value;
s->clkm.arm_ckout1 = value & 0x003f;
omap_clkm_ckout1_update(s, diff, value);
return;
case 0x20: /* ARM_CKOUT2 */
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_clkm_ops = {
.read = omap_clkm_read,
.write = omap_clkm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
CPUState *cpu = CPU(s->cpu);
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
return s->clkm.dsp_idlect1;
case 0x08: /* DSP_IDLECT2 */
return s->clkm.dsp_idlect2;
case 0x14: /* DSP_RSTCT2 */
return s->clkm.dsp_rstct2;
case 0x18: /* DSP_SYSST */
cpu = CPU(s->cpu);
return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
(cpu->halted << 6); /* Quite useless... */
}
OMAP_BAD_REG(addr);
return 0;
}
static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
omap_clk clk;
SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
}
static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
uint16_t diff, uint16_t value)
{
omap_clk clk;
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
diff = s->clkm.dsp_idlect1 ^ value;
s->clkm.dsp_idlect1 = value & 0x01f7;
omap_clkdsp_idlect1_update(s, diff, value);
break;
case 0x08: /* DSP_IDLECT2 */
s->clkm.dsp_idlect2 = value & 0x0037;
diff = s->clkm.dsp_idlect1 ^ value;
omap_clkdsp_idlect2_update(s, diff, value);
break;
case 0x14: /* DSP_RSTCT2 */
s->clkm.dsp_rstct2 = value & 0x0001;
break;
case 0x18: /* DSP_SYSST */
s->clkm.cold_start &= value & 0x3f;
break;
default:
OMAP_BAD_REG(addr);
}
}
static const MemoryRegionOps omap_clkdsp_ops = {
.read = omap_clkdsp_read,
.write = omap_clkdsp_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_clkm_reset(struct omap_mpu_state_s *s)
{
if (s->wdt && s->wdt->reset)
s->clkm.cold_start = 0x6;
s->clkm.clocking_scheme = 0;
omap_clkm_ckctl_update(s, ~0, 0x3000);
s->clkm.arm_ckctl = 0x3000;
omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
s->clkm.arm_idlect1 = 0x0400;
omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
s->clkm.arm_idlect2 = 0x0100;
s->clkm.arm_ewupct = 0x003f;
s->clkm.arm_rstct1 = 0x0000;
s->clkm.arm_rstct2 = 0x0000;
s->clkm.arm_ckout1 = 0x0015;
s->clkm.dpll1_mode = 0x2002;
omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
s->clkm.dsp_idlect1 = 0x0040;
omap_clkdsp_idlect2_update(s, ~0, 0x0000);
s->clkm.dsp_idlect2 = 0x0000;
s->clkm.dsp_rstct2 = 0x0000;
}
static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
hwaddr dsp_base, struct omap_mpu_state_s *s)
{
memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
"omap-clkm", 0x100);
memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
"omap-clkdsp", 0x1000);
s->clkm.arm_idlect1 = 0x03ff;
s->clkm.arm_idlect2 = 0x0100;
s->clkm.dsp_idlect1 = 0x0002;
omap_clkm_reset(s);
s->clkm.cold_start = 0x3a;
memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
}
/* MPU I/O */
struct omap_mpuio_s {
qemu_irq irq;
qemu_irq kbd_irq;
qemu_irq *in;
qemu_irq handler[16];
qemu_irq wakeup;
MemoryRegion iomem;
uint16_t inputs;
uint16_t outputs;
uint16_t dir;
uint16_t edge;
uint16_t mask;
uint16_t ints;
uint16_t debounce;
uint16_t latch;
uint8_t event;
uint8_t buttons[5];
uint8_t row_latch;
uint8_t cols;
int kbd_mask;
int clk;
};
static void omap_mpuio_set(void *opaque, int line, int level)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
uint16_t prev = s->inputs;
if (level)
s->inputs |= 1 << line;
else
s->inputs &= ~(1 << line);
if (((1 << line) & s->dir & ~s->mask) && s->clk) {
if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
s->ints |= 1 << line;
qemu_irq_raise(s->irq);
/* TODO: wakeup */
}
if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
(s->event >> 1) == line) /* PIN_SELECT */
s->latch = s->inputs;
}
}
static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
{
int i;
uint8_t *row, rows = 0, cols = ~s->cols;
for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
if (*row & cols)
rows |= i;
qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
s->row_latch = ~rows;
}
static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (offset) {
case 0x00: /* INPUT_LATCH */
return s->inputs;
case 0x04: /* OUTPUT_REG */
return s->outputs;
case 0x08: /* IO_CNTL */
return s->dir;
case 0x10: /* KBR_LATCH */
return s->row_latch;
case 0x14: /* KBC_REG */
return s->cols;
case 0x18: /* GPIO_EVENT_MODE_REG */
return s->event;
case 0x1c: /* GPIO_INT_EDGE_REG */
return s->edge;
case 0x20: /* KBD_INT */
return (~s->row_latch & 0x1f) && !s->kbd_mask;
case 0x24: /* GPIO_INT */
ret = s->ints;
s->ints &= s->mask;
if (ret)
qemu_irq_lower(s->irq);
return ret;
case 0x28: /* KBD_MASKIT */
return s->kbd_mask;
case 0x2c: /* GPIO_MASKIT */
return s->mask;
case 0x30: /* GPIO_DEBOUNCING_REG */
return s->debounce;
case 0x34: /* GPIO_LATCH_REG */
return s->latch;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_mpuio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (offset) {
case 0x04: /* OUTPUT_REG */
diff = (s->outputs ^ value) & ~s->dir;
s->outputs = value;
while ((ln = ffs(diff))) {
ln --;
if (s->handler[ln])
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
diff &= ~(1 << ln);
}
break;
case 0x08: /* IO_CNTL */
diff = s->outputs & (s->dir ^ value);
s->dir = value;
value = s->outputs & ~s->dir;
while ((ln = ffs(diff))) {
ln --;
if (s->handler[ln])
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
diff &= ~(1 << ln);
}
break;
case 0x14: /* KBC_REG */
s->cols = value;
omap_mpuio_kbd_update(s);
break;
case 0x18: /* GPIO_EVENT_MODE_REG */
s->event = value & 0x1f;
break;
case 0x1c: /* GPIO_INT_EDGE_REG */
s->edge = value;
break;
case 0x28: /* KBD_MASKIT */
s->kbd_mask = value & 1;
omap_mpuio_kbd_update(s);
break;
case 0x2c: /* GPIO_MASKIT */
s->mask = value;
break;
case 0x30: /* GPIO_DEBOUNCING_REG */
s->debounce = value & 0x1ff;
break;
case 0x00: /* INPUT_LATCH */
case 0x10: /* KBR_LATCH */
case 0x20: /* KBD_INT */
case 0x24: /* GPIO_INT */
case 0x34: /* GPIO_LATCH_REG */
OMAP_RO_REG(addr);
return;
default:
OMAP_BAD_REG(addr);
return;
}
}
static const MemoryRegionOps omap_mpuio_ops = {
.read = omap_mpuio_read,
.write = omap_mpuio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpuio_reset(struct omap_mpuio_s *s)
{
s->inputs = 0;
s->outputs = 0;
s->dir = ~0;
s->event = 0;
s->edge = 0;
s->kbd_mask = 0;
s->mask = 0;
s->debounce = 0;
s->latch = 0;
s->ints = 0;
s->row_latch = 0x1f;
s->clk = 1;
}
static void omap_mpuio_onoff(void *opaque, int line, int on)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
s->clk = on;
if (on)
omap_mpuio_kbd_update(s);
}
static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
hwaddr base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *)
g_malloc0(sizeof(struct omap_mpuio_s));
s->irq = gpio_int;
s->kbd_irq = kbd_int;
s->wakeup = wakeup;
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
"omap-mpuio", 0x800);
memory_region_add_subregion(memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
return s;
}
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
{
return s->in;
}
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
{
if (line >= 16 || line < 0)
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
s->handler[line] = handler;
}
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
{
if (row >= 5 || row < 0)
hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
if (down)
s->buttons[row] |= 1 << col;
else
s->buttons[row] &= ~(1 << col);
omap_mpuio_kbd_update(s);
}
/* MicroWire Interface */
struct omap_uwire_s {
MemoryRegion iomem;
qemu_irq txirq;
qemu_irq rxirq;
qemu_irq txdrq;
uint16_t txbuf;
uint16_t rxbuf;
uint16_t control;
uint16_t setup[5];
uWireSlave *chip[4];
};
static void omap_uwire_transfer_start(struct omap_uwire_s *s)
{
int chipselect = (s->control >> 10) & 3; /* INDEX */
uWireSlave *slave = s->chip[chipselect];
if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
if (s->control & (1 << 12)) /* CS_CMD */
if (slave && slave->send)
slave->send(slave->opaque,
s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
s->control &= ~(1 << 14); /* CSRB */
/* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
* a DRQ. When is the level IRQ supposed to be reset? */
}
if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
if (s->control & (1 << 12)) /* CS_CMD */
if (slave && slave->receive)
s->rxbuf = slave->receive(slave->opaque);
s->control |= 1 << 15; /* RDRB */
/* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
* a DRQ. When is the level IRQ supposed to be reset? */
}
}
static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (offset) {
case 0x00: /* RDR */
s->control &= ~(1 << 15); /* RDRB */
return s->rxbuf;
case 0x04: /* CSR */
return s->control;
case 0x08: /* SR1 */
return s->setup[0];
case 0x0c: /* SR2 */
return s->setup[1];
case 0x10: /* SR3 */
return s->setup[2];
case 0x14: /* SR4 */
return s->setup[3];
case 0x18: /* SR5 */
return s->setup[4];
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_uwire_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (offset) {
case 0x00: /* TDR */
s->txbuf = value; /* TD */
if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
(s->control & (1 << 12)))) { /* CS_CMD */
s->control |= 1 << 14; /* CSRB */
omap_uwire_transfer_start(s);
}
break;
case 0x04: /* CSR */
s->control = value & 0x1fff;
if (value & (1 << 13)) /* START */
omap_uwire_transfer_start(s);
break;
case 0x08: /* SR1 */
s->setup[0] = value & 0x003f;
break;
case 0x0c: /* SR2 */
s->setup[1] = value & 0x0fc0;
break;
case 0x10: /* SR3 */
s->setup[2] = value & 0x0003;
break;
case 0x14: /* SR4 */
s->setup[3] = value & 0x0001;
break;
case 0x18: /* SR5 */
s->setup[4] = value & 0x000f;
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
static const MemoryRegionOps omap_uwire_ops = {
.read = omap_uwire_read,
.write = omap_uwire_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_uwire_reset(struct omap_uwire_s *s)
{
s->control = 0;
s->setup[0] = 0;
s->setup[1] = 0;
s->setup[2] = 0;
s->setup[3] = 0;
s->setup[4] = 0;
}
static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq dma,
omap_clk clk)
{
struct omap_uwire_s *s = (struct omap_uwire_s *)
g_malloc0(sizeof(struct omap_uwire_s));
s->txirq = txirq;
s->rxirq = rxirq;
s->txdrq = dma;
omap_uwire_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect)
{
if (chipselect < 0 || chipselect > 3) {
fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
exit(-1);
}
s->chip[chipselect] = slave;
}
/* Pseudonoise Pulse-Width Light Modulator */
struct omap_pwl_s {
MemoryRegion iomem;
uint8_t output;
uint8_t level;
uint8_t enable;
int clk;
};
static void omap_pwl_update(struct omap_pwl_s *s)
{
int output = (s->clk && s->enable) ? s->level : 0;
if (output != s->output) {
s->output = output;
printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
}
}
static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_read8(opaque, addr);
}
switch (offset) {
case 0x00: /* PWL_LEVEL */
return s->level;
case 0x04: /* PWL_CTRL */
return s->enable;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_pwl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, value);
}
switch (offset) {
case 0x00: /* PWL_LEVEL */
s->level = value;
omap_pwl_update(s);
break;
case 0x04: /* PWL_CTRL */
s->enable = value & 1;
omap_pwl_update(s);
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
static const MemoryRegionOps omap_pwl_ops = {
.read = omap_pwl_read,
.write = omap_pwl_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pwl_reset(struct omap_pwl_s *s)
{
s->output = 0;
s->level = 0;
s->enable = 0;
s->clk = 1;
omap_pwl_update(s);
}
static void omap_pwl_clk_update(void *opaque, int line, int on)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
s->clk = on;
omap_pwl_update(s);
}
static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
hwaddr base,
omap_clk clk)
{
struct omap_pwl_s *s = g_malloc0(sizeof(*s));
omap_pwl_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
"omap-pwl", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
return s;
}
/* Pulse-Width Tone module */
struct omap_pwt_s {
MemoryRegion iomem;
uint8_t frc;
uint8_t vrc;
uint8_t gcr;
omap_clk clk;
};
static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_read8(opaque, addr);
}
switch (offset) {
case 0x00: /* FRC */
return s->frc;
case 0x04: /* VCR */
return s->vrc;
case 0x08: /* GCR */
return s->gcr;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_pwt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, value);
}
switch (offset) {
case 0x00: /* FRC */
s->frc = value & 0x3f;
break;
case 0x04: /* VRC */
if ((value ^ s->vrc) & 1) {
if (value & 1)
printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
/* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
((omap_clk_getrate(s->clk) >> 3) /
/* Pre-multiplexer divider */
((s->gcr & 2) ? 1 : 154) /
/* Octave multiplexer */
(2 << (value & 3)) *
/* 101/107 divider */
((value & (1 << 2)) ? 101 : 107) *
/* 49/55 divider */
((value & (1 << 3)) ? 49 : 55) *
/* 50/63 divider */
((value & (1 << 4)) ? 50 : 63) *
/* 80/127 divider */
((value & (1 << 5)) ? 80 : 127) /
(107 * 55 * 63 * 127)));
else
printf("%s: silence!\n", __FUNCTION__);
}
s->vrc = value & 0x7f;
break;
case 0x08: /* GCR */
s->gcr = value & 3;
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
static const MemoryRegionOps omap_pwt_ops = {
.read =omap_pwt_read,
.write = omap_pwt_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pwt_reset(struct omap_pwt_s *s)
{
s->frc = 0;
s->vrc = 0;
s->gcr = 0;
}
static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
hwaddr base,
omap_clk clk)
{
struct omap_pwt_s *s = g_malloc0(sizeof(*s));
s->clk = clk;
omap_pwt_reset(s);
memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
"omap-pwt", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
/* Real-time Clock module */
struct omap_rtc_s {
MemoryRegion iomem;
qemu_irq irq;
qemu_irq alarm;
QEMUTimer *clk;
uint8_t interrupts;
uint8_t status;
int16_t comp_reg;
int running;
int pm_am;
int auto_comp;
int round;
struct tm alarm_tm;
time_t alarm_ti;
struct tm current_tm;
time_t ti;
uint64_t tick;
};
static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
{
/* s->alarm is level-triggered */
qemu_set_irq(s->alarm, (s->status >> 6) & 1);
}
static void omap_rtc_alarm_update(struct omap_rtc_s *s)
{
s->alarm_ti = mktimegm(&s->alarm_tm);
if (s->alarm_ti == -1)
printf("%s: conversion failed\n", __FUNCTION__);