)]}'
{
  "commit": "1c70aa6264ea7f3d7be6f3acb65a1e0aac8b3944",
  "tree": "b78ff4ad33b28ef60d80d9f3c34351e8dbd5ff08",
  "parents": [
    "f727d0e6219e6d5a9f91326f01b85aa563e37bb9"
  ],
  "author": {
    "name": "Beniamino Galvani",
    "email": "b.galvani@gmail.com",
    "time": "Tue Mar 25 19:22:04 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Apr 17 21:34:06 2014 +0100"
  },
  "message": "allwinner-a10-pic: set vector address when an interrupt is pending\n\nThis patch implements proper updating of the vector register which\nshould hold, according to the A10 user manual, the vector address for\nthe interrupt currently active on the CPU IRQ input.\n\nInterrupt priority is not implemented at the moment and thus the first\npending interrupt is returned.\n\nSigned-off-by: Beniamino Galvani \u003cb.galvani@gmail.com\u003e\nReviewed-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nReviewed-by: Li Guang \u003clig.fnst@cn.fujitsu.com\u003e\nMessage-id: 1395771730-16882-2-git-send-email-b.galvani@gmail.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "407d5635148907b6b54be94c690cac3625608ba3",
      "old_mode": 33188,
      "old_path": "hw/intc/allwinner-a10-pic.c",
      "new_id": "00f3c11b4667c1888b72bba1ac9018da666b6e19",
      "new_mode": 33188,
      "new_path": "hw/intc/allwinner-a10-pic.c"
    }
  ]
}