commit 1f944c661a821774e7b8cfbf5560a238795f2a60
author Michael S. Tsirkin <mst@redhat.com> Wed Nov 25 12:00:10 2009 +0200
committer Michael S. Tsirkin <mst@redhat.com> Tue Dec 01 18:00:00 2009 +0200
tree 5665679277dac50aaa9eaedf025a1ca954ab38fc
parent ae1be0bbc127a9a6289873efdb7cb22c57d81a9d

msix: fix reset value for enable bit

On reset, we currently clear all bits in msix control register *except*
enable bit.  This is wrong: the spec says we should clear writeable
bits: function mask and enable bit.
Correct this.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

hw/msix.c

diff --git a/hw/msix.c b/hw/msix.c
index 45f83dd..785e097 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -361,7 +361,8 @@
     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
         return;
     msix_free_irq_entries(dev);
-    dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
+    dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &=
+	    ~dev->wmask[dev->msix_cap + MSIX_ENABLE_OFFSET];
     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
     msix_mask_all(dev, dev->msix_entries_nr);
 }