)]}'
{
  "commit": "2133a5f6b8f8941a6a3734c6c1990656553de76c",
  "tree": "886e8997b1b0625734040b6765b129736d59aeed",
  "parents": [
    "15408b428f5b4db56da555fbda4f1aaf40d77f4b"
  ],
  "author": {
    "name": "Peter Crosthwaite",
    "email": "peter.crosthwaite@xilinx.com",
    "time": "Mon Jun 03 17:17:43 2013 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jun 03 17:17:43 2013 +0100"
  },
  "message": "xilinx_spips: Fix CTRL register RW bits\n\nThe CTRL register was RAZ/WI on some of the RW bits. Even though the\nfunction behind these bits is invalid in QEMU, they should still be\nguest accessible. Fix.\n\nSigned-off-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Edgar E. Iglesias \u003cedgar.iglesias@gmail.com\u003e\nMessage-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ea8a593214a410f0d30f62616329616147e31f32",
      "old_mode": 33188,
      "old_path": "hw/ssi/xilinx_spips.c",
      "new_id": "3e9e76c165d885bf8434495fba945ce395e883e3",
      "new_mode": 33188,
      "new_path": "hw/ssi/xilinx_spips.c"
    }
  ]
}