)]}'
{
  "commit": "261ccf426a6df854ba398be92413476919dd67f9",
  "tree": "e72d79039c7a01270f4869331f5aecd2840dc264",
  "parents": [
    "f50a1640fb82708a5d528dee1ace42a224b95b15",
    "257621a9566054472d1d55a819880d0f9da02bda"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jul 06 11:04:54 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jul 06 11:04:54 2015 +0100"
  },
  "message": "Merge remote-tracking branch \u0027remotes/pmaydell/tags/pull-target-arm-20150706\u0027 into staging\n\ntarget-arm queue:\n * TLBI ALLEI1IS should operate on all CPUs, not just this one\n * Fix interval interrupt of cadence ttc in decrement mode\n * Implement YIELD insn to yield in ARM and Thumb translators\n * ARM GIC: reset all registers\n * arm_mptimer: fix timer shutdown and mode change\n * arm_mptimer: respect IT bit state\n\n# gpg: Signature made Mon Jul  6 10:58:27 2015 BST using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n\n* remotes/pmaydell/tags/pull-target-arm-20150706:\n  arm_mptimer: Respect IT bit state\n  arm_mptimer: Fix timer shutdown and mode change\n  hw/intc/arm_gic_common.c: Reset all registers\n  target-arm: Implement YIELD insn to yield in ARM and Thumb translators\n  target-arm: Split DISAS_YIELD from DISAS_WFE\n  Fix interval interrupt of cadence ttc when timer is in decrement mode\n  target-arm: fix write helper for TLBI ALLE1IS\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}