)]}'
{
  "commit": "2801339f2fb2534ccf01561d274398328bdd446d",
  "tree": "96962ba0a29c40330dd3687e4913524d835bb71e",
  "parents": [
    "8b8f1c7e9ddb2e88a144638f6527bf70e32343e3"
  ],
  "author": {
    "name": "Sai Pavan Boddu",
    "email": "sai.pavan.boddu@xilinx.com",
    "time": "Fri May 29 11:52:35 2015 +0530"
  },
  "committer": {
    "name": "Michael Tokarev",
    "email": "mjt@tls.msk.ru",
    "time": "Wed Jun 03 16:03:03 2015 +0300"
  },
  "message": "cadence_gem: Fix Rx buffer size field mask\n\nThis patch corrects the Rx buffer size field mask to mask bits 23 to 16\nto match Xilinx UG585 documentation.\n\nSigned-off-by: Sai Pavan Boddu \u003csaipava@xilinx.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@xilinx.com\u003e\nReviewed-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nSigned-off-by: Michael Tokarev \u003cmjt@tls.msk.ru\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dafe91421b1208bad88713d34cbee5523ad4f7c5",
      "old_mode": 33188,
      "old_path": "hw/net/cadence_gem.c",
      "new_id": "494a346cf6f2d0023e9d53c32e3f858ce8117364",
      "new_mode": 33188,
      "new_path": "hw/net/cadence_gem.c"
    }
  ]
}