commit 2dcf7908d9e0274c08911400beb7ed14276bb170
author Leon Alrae <leon.alrae@imgtec.com> Mon Sep 14 13:51:31 2015 +0100
committer Leon Alrae <leon.alrae@imgtec.com> Thu Oct 29 16:16:44 2015 +0000
tree 31852b7fb89257870cb1ce5a96e9f703183efb72
parent 7540a43a1d9de71fa7a53ccd2bb24a04e2aace41

target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6

Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

target-mips/cpu.h

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3799d26..c68681d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -1001,7 +1001,12 @@
 
     if (env->insn_flags & ISA_MIPS32R6) {
         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-
+#if defined(TARGET_MIPS64)
+        uint32_t ksux = (1 << CP0St_KX) & val;
+        ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+        ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+        val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
             mask &= ~(3 << CP0St_KSU);
         }