)]}'
{
  "commit": "327ed10fa2331384c1a58c794e0356e6d88089c8",
  "tree": "7c0a3f3bc6e638a341800158846f35f0eb4964d5",
  "parents": [
    "a505d7fe5f638c4aaba93150f71968147f7c2b3a"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 26 17:20:04 2014 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 26 17:20:04 2014 +0000"
  },
  "message": "target-arm: Implement AArch64 TTBR*\n\nImplement the AArch64 TTBR* registers. For v7 these were already 64 bits\nto handle LPAE, but implemented as two separate uint32_t fields.\nCombine them into a single uint64_t which can be used for all purposes.\nSince this requires touching every use, take the opportunity to rename\nthe field to the architectural name.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "45a99c819de1f81d6d94b2c166ae3a04a9c8a0c4",
      "old_mode": 33188,
      "old_path": "hw/arm/pxa2xx.c",
      "new_id": "5579036482e020ab0b78cdd30b068498545a9c80",
      "new_mode": 33188,
      "new_path": "hw/arm/pxa2xx.c"
    },
    {
      "type": "modify",
      "old_id": "06953ac9bd5c9b2d06f0c22c60aed6c0bd00f636",
      "old_mode": 33188,
      "old_path": "target-arm/cpu.h",
      "new_id": "4bbc9ad54874f5f45e49d73a075170330cc1de30",
      "new_mode": 33188,
      "new_path": "target-arm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "274dfbde3c7ea1a55addd9680ff95c747908f92f",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "9dcdf8ee2c3f024c356e42ca1e445dfc52db542a",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}