commit 34a0fad10210a3e639a8e68323c923494047eefc
author Tom Musta <tommusta@gmail.com> Tue Aug 12 08:45:09 2014 -0500
committer Alexander Graf <agraf@suse.de> Mon Sep 08 12:50:50 2014 +0200
tree a9b3d5ad1e859f7d2afcbe12c18270575590a26e
parent 9824d01d5d789a57d27360c0f5e8ee44955eb1d7

target-ppc: Bug Fix: srawi

For 64 bit implementations, the special case of a shift by zero
should result in the sign extension of the least significant 32 bits
of the source GPR (not a direct copy of the 64 bit source GPR).

Example:

R3 A6212433228F41DC
srawi 3,3,0
R3 expected : 00000000228F41DC
R3 actual   : A6212433228F41DC (without this patch)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

target-ppc/translate.c

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b19eb14..47dc903 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1944,7 +1944,7 @@
     TCGv dst = cpu_gpr[rA(ctx->opcode)];
     TCGv src = cpu_gpr[rS(ctx->opcode)];
     if (sh == 0) {
-        tcg_gen_mov_tl(dst, src);
+        tcg_gen_ext32s_tl(dst, src);
         tcg_gen_movi_tl(cpu_ca, 0);
     } else {
         TCGv t0;