)]}'
{
  "commit": "35b5c0442798c1754f1d56452528dce5fee003c2",
  "tree": "ffc45877d83c476a726558b1a0121521ea3de40a",
  "parents": [
    "e61dc8f72c096e084106d5e97101d9d88f642d0e"
  ],
  "author": {
    "name": "Max Filippov",
    "email": "jcmvbkbc@gmail.com",
    "time": "Sun Jan 15 05:40:50 2012 +0400"
  },
  "committer": {
    "name": "Max Filippov",
    "email": "jcmvbkbc@gmail.com",
    "time": "Sat Feb 18 14:55:52 2012 +0400"
  },
  "message": "target-xtensa: add ICOUNT SR and debug exception\n\nICOUNT SR gets incremented on every instruction completion provided that\nCINTLEVEL at the beginning of the instruction execution is lower than\nICOUNTLEVEL.\n\nWhen ICOUNT would increment to 0 a debug exception is raised if\nCINTLEVEL is lower than DEBUGLEVEL.\n\nSee ISA, 4.7.7.5 for more details.\n\nSigned-off-by: Max Filippov \u003cjcmvbkbc@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a18072b7bd6037d3b1d1142db0409c9ff0c1dcc4",
      "old_mode": 33188,
      "old_path": "target-xtensa/cpu.h",
      "new_id": "92441e34f90e0cfb85f72c081f6939aa1a053377",
      "new_mode": 33188,
      "new_path": "target-xtensa/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "a438474b4758f46a4cc40291371af2c903308d7c",
      "old_mode": 33188,
      "old_path": "target-xtensa/translate.c",
      "new_id": "3bf880f5cb2556fbac24e1b69221160ed4ca80bc",
      "new_mode": 33188,
      "new_path": "target-xtensa/translate.c"
    }
  ]
}