Code provision for new PowerPC embedded target support with:
- 1 kB page size
- 64 bits GPR
- 64 bits physical address space
- SPE extension support.
Change TARGET_PPCSPE into TARGET_PPCEMB
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 4a241f1..a25d30a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -23,11 +23,13 @@
#include "config.h"
#include <inttypes.h>
+#if !defined(TARGET_PPCEMB)
#if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
/* When using 64 bits temporary registers,
* we can use 64 bits GPR with no extra cost
*/
-#define TARGET_PPCSPE
+#define TARGET_PPCEMB
+#endif
#endif
#if defined (TARGET_PPC64)
@@ -35,7 +37,8 @@
#define TARGET_LONG_BITS 64
#define TARGET_GPR_BITS 64
#define REGX "%016" PRIx64
-#elif defined(TARGET_PPCSPE)
+#define TARGET_PAGE_BITS 12
+#elif defined(TARGET_PPCEMB)
/* e500v2 have 36 bits physical address space */
#define TARGET_PHYS_ADDR_BITS 64
/* GPR are 64 bits: used by vector extension */
@@ -43,11 +46,14 @@
#define TARGET_LONG_BITS 32
#define TARGET_GPR_BITS 64
#define REGX "%016" PRIx64
+/* Pages can be 1 kB small */
+#define TARGET_PAGE_BITS 10
#else
typedef uint32_t ppc_gpr_t;
#define TARGET_LONG_BITS 32
#define TARGET_GPR_BITS 32
#define REGX "%08" PRIx32
+#define TARGET_PAGE_BITS 12
#endif
#include "cpu-defs.h"
@@ -893,7 +899,6 @@
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
-#define TARGET_PAGE_BITS 12
#include "cpu-all.h"
/*****************************************************************************/
diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index a0f91cc..4f5abe9 100644
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -43,7 +43,7 @@
register unsigned long T2 asm(AREG3);
#endif
/* We may, sometime, need 64 bits registers on 32 bits target */
-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64)
+#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64)
#define T0_64 T0
#define T1_64 T1
#define T2_64 T2
diff --git a/target-ppc/op.c b/target-ppc/op.c
index f18e7f3..019594c 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -2479,7 +2479,7 @@
#endif /* !defined(CONFIG_USER_ONLY) */
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/* SPE extension */
void OPPROTO op_splatw_T1_64 (void)
{
@@ -3198,4 +3198,4 @@
T0 = _do_efdtsteq(T0_64, T1_64);
RETURN();
}
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index a888821..10390a9 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1340,7 +1340,7 @@
T0 = i;
}
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/* SPE extension helpers */
/* Use a table to make this quicker */
static uint8_t hbrev[16] = {
@@ -2200,7 +2200,7 @@
DO_SPE_OP1(fsctsf);
/* evfsctuf */
DO_SPE_OP1(fsctuf);
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
/*****************************************************************************/
/* Softmmu support */
diff --git a/target-ppc/op_helper.h b/target-ppc/op_helper.h
index 2930310..82307d4 100644
--- a/target-ppc/op_helper.h
+++ b/target-ppc/op_helper.h
@@ -183,7 +183,7 @@
void do_store_403_pb (int num);
#endif
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/* SPE extension helpers */
void do_brinc (void);
/* Fixed-point vector helpers */
@@ -264,7 +264,7 @@
void do_evfsctui (void);
void do_evfsctsiz (void);
void do_evfsctuiz (void);
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
/* Inlined helpers: used in micro-operation as well as helpers */
/* Generic fixed-point helpers */
@@ -338,7 +338,7 @@
return cnt;
}
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/* SPE extension */
/* Single precision floating-point helpers */
static inline uint32_t _do_efsabs (uint32_t val)
@@ -459,5 +459,5 @@
u2.u = op2;
return float64_eq(u1.f, u2.f, &env->spe_status) ? 1 : 0;
}
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
#endif
diff --git a/target-ppc/op_mem.h b/target-ppc/op_mem.h
index a78aa62..612d120 100644
--- a/target-ppc/op_mem.h
+++ b/target-ppc/op_mem.h
@@ -37,7 +37,7 @@
((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
}
-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE)
+#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB)
static inline uint64_t glue(ld64r, MEMSUFFIX) (target_ulong EA)
{
uint64_t tmp = glue(ldq, MEMSUFFIX)(EA);
@@ -79,7 +79,7 @@
glue(stl, MEMSUFFIX)(EA, tmp);
}
-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE)
+#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB)
static inline void glue(st64r, MEMSUFFIX) (target_ulong EA, uint64_t data)
{
uint64_t tmp = ((data & 0xFF00000000000000ULL) >> 56) |
@@ -895,7 +895,7 @@
RETURN();
}
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/* SPE extension */
#define _PPC_SPE_LD_OP(name, op) \
void OPPROTO glue(glue(op_spe_l, name), MEMSUFFIX) (void) \
@@ -1151,6 +1151,6 @@
return ret;
}
PPC_SPE_LD_OP(whsplat_le, spe_lwhsplat_le);
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
#undef MEMSUFFIX
diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h
index bcef1a5..4487a87 100644
--- a/target-ppc/op_template.h
+++ b/target-ppc/op_template.h
@@ -57,7 +57,7 @@
}
#endif
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
{
T0_64 = regs->gpr[REG];
@@ -97,7 +97,7 @@
RETURN();
}
#endif
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
#if REG <= 7
/* Condition register moves */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6e27854..2ea759a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -161,7 +161,7 @@
int sf_mode;
#endif
int fpu_enabled;
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
int spe_enabled;
#endif
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
@@ -4761,7 +4761,7 @@
*/
}
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/*** SPE extension ***/
/* Register moves */
@@ -5740,7 +5740,7 @@
ctx.sf_mode = msr_sf;
#endif
ctx.fpu_enabled = msr_fp;
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
ctx.spe_enabled = msr_spe;
#endif
ctx.singlestep_enabled = env->singlestep_enabled;
