)]}'
{
  "commit": "382d2db62bcb34dff7febc270783d5ff662ced7a",
  "tree": "6997e3caabed16552509587067e8daa7713c8f11",
  "parents": [
    "0c967de9c00321f893a57617a4e3dfcda05266f5"
  ],
  "author": {
    "name": "Greg Kurz",
    "email": "gkurz@linux.vnet.ibm.com",
    "time": "Mon May 19 19:59:05 2014 +0200"
  },
  "committer": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Mon Jun 16 13:24:36 2014 +0200"
  },
  "message": "target-ppc: Introduce callback for interrupt endianness\n\nPOWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR\nspecial purpose register to decide the endianness to use when\nentering interrupt handlers. When running a Linux guest, this\nprovides a hint on the endianness used by the kernel. And when\nit comes to dumping a guest, the information is needed to write\nELF headers using the kernel endianness.\n\nSuggested-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nReviewed-by: Alexander Graf \u003cagraf@suse.de\u003e\nSigned-off-by: Greg Kurz \u003cgkurz@linux.vnet.ibm.com\u003e\n[agraf: change subject line]\nSigned-off-by: Alexander Graf \u003cagraf@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d926d9369e73e6556dd66909b91a547a9c55f8cb",
      "old_mode": 33188,
      "old_path": "target-ppc/cpu-qom.h",
      "new_id": "046ea0effa7ae9b34b525635b2bc5dbe7a6b1e9e",
      "new_mode": 33188,
      "new_path": "target-ppc/cpu-qom.h"
    },
    {
      "type": "modify",
      "old_id": "0f9dec753be3fe25a5693e28d000887610ecafec",
      "old_mode": 33188,
      "old_path": "target-ppc/translate_init.c",
      "new_id": "16ecada688f1e3f5dfd05333804a9a08d8b2ab1f",
      "new_mode": 33188,
      "new_path": "target-ppc/translate_init.c"
    }
  ]
}