)]}'
{
  "commit": "39d5492a186d156d4acc306ae258d7e04f8a6c29",
  "tree": "fa968b2dae88179ae1d4d808d9387a3c318db099",
  "parents": [
    "fd469df97ab4277411ecdd4032a2f045a3a87b2a"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu May 23 12:59:55 2013 +0100"
  },
  "committer": {
    "name": "Blue Swirl",
    "email": "blauwirbel@gmail.com",
    "time": "Sun May 26 10:04:54 2013 +0000"
  },
  "message": "target-arm: Don\u0027t use TCGv when we mean TCGv_i32\n\nTCGv changes size depending on the compile time value of\nTARGET_LONG_BITS.  This is useful for generating code for MIPS style\n\"instructions are the same but the register width changes\" CPUs, and\nalso for the generic bits of QEMU which operate on \"width of a\nvirtual address\" values, but mostly in the ARM target code we were\nusing it purely as a shorthand for \"any 32 bit value\".\n\nThis needs to change in preparation for AArch64 support, since an\nAArch64-capable v8 core will have 64 bit virtual addresses but still\nuse 32 bit values for the 32 bit instruction set.\n\nThis patch mechanically converts all the occurrences of TCGv,\ntcg_temp_new(), tcg_temp_free(), tcg_temp_local_new() and\nTCGV_UNUSED() to their explicitly 32 bit counterparts.  This is\ncorrect for everything except the arguments to tcg_gen_qemu_{ld,st}*,\nwhich really do need to be TCGv and so will require a 32-to-64\nconversion when building the 32 bit code for AArch64.  Those changes\nwill be in a separate patch for easier review.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crth@twiddle.net\u003e\nSigned-off-by: Blue Swirl \u003cblauwirbel@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a1b7b8c1a8fc07d68b4413d9076839c6d8fc7765",
      "old_mode": 33188,
      "old_path": "target-arm/translate.c",
      "new_id": "75972cfb24e32e02263c542ca52bdefbeff89d85",
      "new_mode": 33188,
      "new_path": "target-arm/translate.c"
    }
  ]
}
