tree fa968b2dae88179ae1d4d808d9387a3c318db099
parent fd469df97ab4277411ecdd4032a2f045a3a87b2a
author Peter Maydell <peter.maydell@linaro.org> 1369310395 +0100
committer Blue Swirl <blauwirbel@gmail.com> 1369562694 +0000

target-arm: Don't use TCGv when we mean TCGv_i32

TCGv changes size depending on the compile time value of
TARGET_LONG_BITS.  This is useful for generating code for MIPS style
"instructions are the same but the register width changes" CPUs, and
also for the generic bits of QEMU which operate on "width of a
virtual address" values, but mostly in the ARM target code we were
using it purely as a shorthand for "any 32 bit value".

This needs to change in preparation for AArch64 support, since an
AArch64-capable v8 core will have 64 bit virtual addresses but still
use 32 bit values for the 32 bit instruction set.

This patch mechanically converts all the occurrences of TCGv,
tcg_temp_new(), tcg_temp_free(), tcg_temp_local_new() and
TCGV_UNUSED() to their explicitly 32 bit counterparts.  This is
correct for everything except the arguments to tcg_gen_qemu_{ld,st}*,
which really do need to be TCGv and so will require a 32-to-64
conversion when building the 32 bit code for AArch64.  Those changes
will be in a separate patch for easier review.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>