Merge remote-tracking branch 'mst/tags/for_anthony' into staging
virtio,pci,qom
Work by Alex to support VGA assignment,
pci and virtio fixes by Stefan, Jason and myself, and a
new qmp event for hotplug support by myself.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Tue 26 Mar 2013 02:02:24 PM CDT using RSA key ID D28D5469
# gpg: Can't check signature: public key not found
# By Alex Williamson (13) and others
# Via Michael S. Tsirkin
* mst/tags/for_anthony: (23 commits)
pcie: Add endpoint capability initialization wrapper
roms: switch oldnoconfig to olddefconfig
pcie: Mangle types to match topology
pci: Create and use API to determine root buses
pci: Create pci_bus_is_express helper
pci: Q35, Root Ports, and Switches create PCI Express buses
pci: Allow PCI bus creation interfaces to specify the type of bus
pci: Move PCI and PCIE type defines
pci: Create and register a new PCI Express TypeInfo
exec: assert that RAMBlock size is non-zero
pci: refuse empty ROM files
pci_bridge: Remove duplicate IRQ swizzle function
pci_bridge: Use a default map_irq function
pci: Fix INTx routing notifier recursion
pci_bridge: drop formatting from source
pci_bridge: factor out common code
pci: Teach PCI Bridges about VGA routing
pci: Add PCI VGA helpers
virtio-pci: guest notifier mask without non-irqfd
virtio-net: remove layout assumptions for mq ctrl
...
diff --git a/.gitignore b/.gitignore
index 27ad002..9c234a3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -80,6 +80,9 @@
*.swp
*.orig
.pc
+*.patch
+*.gcda
+*.gcno
patches
pc-bios/bios-pq/status
pc-bios/vgabios-pq/status
diff --git a/MAINTAINERS b/MAINTAINERS
index 0ca7e1d..db14ffc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -91,6 +91,11 @@
S: Odd Fixes
F: target-mips/
+Moxie
+M: Anthony Green <green@moxielogic.com>
+S: Maintained
+F: target-moxie/
+
PowerPC
M: Alexander Graf <agraf@suse.de>
L: qemu-ppc@nongnu.org
diff --git a/QMP/qmp-shell b/QMP/qmp-shell
index 24b665c..d126e63 100755
--- a/QMP/qmp-shell
+++ b/QMP/qmp-shell
@@ -101,7 +101,12 @@
try:
value = int(opt[1])
except ValueError:
- value = opt[1]
+ if opt[1] == 'true':
+ value = True
+ elif opt[1] == 'false':
+ value = False
+ else:
+ value = opt[1]
qmpcmd['arguments'][opt[0]] = value
return qmpcmd
diff --git a/arch_init.c b/arch_init.c
index 98e2bc6..4ef5a15 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -85,6 +85,8 @@
#define QEMU_ARCH QEMU_ARCH_MICROBLAZE
#elif defined(TARGET_MIPS)
#define QEMU_ARCH QEMU_ARCH_MIPS
+#elif defined(TARGET_MOXIE)
+#define QEMU_ARCH QEMU_ARCH_MOXIE
#elif defined(TARGET_OPENRISC)
#define QEMU_ARCH QEMU_ARCH_OPENRISC
#elif defined(TARGET_PPC)
@@ -114,26 +116,6 @@
#define RAM_SAVE_FLAG_CONTINUE 0x20
#define RAM_SAVE_FLAG_XBZRLE 0x40
-#ifdef __ALTIVEC__
-#include <altivec.h>
-#define VECTYPE vector unsigned char
-#define SPLAT(p) vec_splat(vec_ld(0, p), 0)
-#define ALL_EQ(v1, v2) vec_all_eq(v1, v2)
-/* altivec.h may redefine the bool macro as vector type.
- * Reset it to POSIX semantics. */
-#undef bool
-#define bool _Bool
-#elif defined __SSE2__
-#include <emmintrin.h>
-#define VECTYPE __m128i
-#define SPLAT(p) _mm_set1_epi8(*(p))
-#define ALL_EQ(v1, v2) (_mm_movemask_epi8(_mm_cmpeq_epi8(v1, v2)) == 0xFFFF)
-#else
-#define VECTYPE unsigned long
-#define SPLAT(p) (*(p) * (~0UL / 255))
-#define ALL_EQ(v1, v2) ((v1) == (v2))
-#endif
-
static struct defconfig_file {
const char *filename;
@@ -164,19 +146,10 @@
return 0;
}
-static int is_dup_page(uint8_t *page)
+static inline bool is_zero_page(uint8_t *p)
{
- VECTYPE *p = (VECTYPE *)page;
- VECTYPE val = SPLAT(page);
- int i;
-
- for (i = 0; i < TARGET_PAGE_SIZE / sizeof(VECTYPE); i++) {
- if (!ALL_EQ(val, p[i])) {
- return 0;
- }
- }
-
- return 1;
+ return buffer_find_nonzero_offset(p, TARGET_PAGE_SIZE) ==
+ TARGET_PAGE_SIZE;
}
/* struct contains XBZRLE cache and a static page
@@ -210,6 +183,7 @@
/* accounting for migration statistics */
typedef struct AccountingInfo {
uint64_t dup_pages;
+ uint64_t skipped_pages;
uint64_t norm_pages;
uint64_t iterations;
uint64_t xbzrle_bytes;
@@ -235,6 +209,16 @@
return acct_info.dup_pages;
}
+uint64_t skipped_mig_bytes_transferred(void)
+{
+ return acct_info.skipped_pages * TARGET_PAGE_SIZE;
+}
+
+uint64_t skipped_mig_pages_transferred(void)
+{
+ return acct_info.skipped_pages;
+}
+
uint64_t norm_mig_bytes_transferred(void)
{
return acct_info.norm_pages * TARGET_PAGE_SIZE;
@@ -346,6 +330,7 @@
static unsigned long *migration_bitmap;
static uint64_t migration_dirty_pages;
static uint32_t last_version;
+static bool ram_bulk_stage;
static inline
ram_addr_t migration_bitmap_find_and_reset_dirty(MemoryRegion *mr,
@@ -355,7 +340,13 @@
unsigned long nr = base + (start >> TARGET_PAGE_BITS);
unsigned long size = base + (int128_get64(mr->size) >> TARGET_PAGE_BITS);
- unsigned long next = find_next_bit(migration_bitmap, size, nr);
+ unsigned long next;
+
+ if (ram_bulk_stage && nr > base) {
+ next = nr + 1;
+ } else {
+ next = find_next_bit(migration_bitmap, size, nr);
+ }
if (next < size) {
clear_bit(next, migration_bitmap);
@@ -453,6 +444,7 @@
if (!block) {
block = QTAILQ_FIRST(&ram_list.blocks);
complete_round = true;
+ ram_bulk_stage = false;
}
} else {
uint8_t *p;
@@ -463,13 +455,18 @@
/* In doubt sent page as normal */
bytes_sent = -1;
- if (is_dup_page(p)) {
+ if (is_zero_page(p)) {
acct_info.dup_pages++;
- bytes_sent = save_block_hdr(f, block, offset, cont,
- RAM_SAVE_FLAG_COMPRESS);
- qemu_put_byte(f, *p);
- bytes_sent += 1;
- } else if (migrate_use_xbzrle()) {
+ if (!ram_bulk_stage) {
+ bytes_sent = save_block_hdr(f, block, offset, cont,
+ RAM_SAVE_FLAG_COMPRESS);
+ qemu_put_byte(f, 0);
+ bytes_sent++;
+ } else {
+ acct_info.skipped_pages++;
+ bytes_sent = 0;
+ }
+ } else if (!ram_bulk_stage && migrate_use_xbzrle()) {
current_addr = block->offset + offset;
bytes_sent = save_xbzrle_page(f, p, current_addr, block,
offset, cont, last_stage);
@@ -481,7 +478,7 @@
/* XBZRLE overflow or normal page */
if (bytes_sent == -1) {
bytes_sent = save_block_hdr(f, block, offset, cont, RAM_SAVE_FLAG_PAGE);
- qemu_put_buffer(f, p, TARGET_PAGE_SIZE);
+ qemu_put_buffer_async(f, p, TARGET_PAGE_SIZE);
bytes_sent += TARGET_PAGE_SIZE;
acct_info.norm_pages++;
}
@@ -556,6 +553,7 @@
last_sent_block = NULL;
last_offset = 0;
last_version = ram_list.version;
+ ram_bulk_stage = true;
}
#define MAX_WAIT 50 /* ms, half buffered_file limit */
diff --git a/block.c b/block.c
index 037e15e..16a92a4 100644
--- a/block.c
+++ b/block.c
@@ -676,7 +676,7 @@
assert(drv != NULL);
assert(bs->file == NULL);
- assert(options == NULL || bs->options != options);
+ assert(options != NULL && bs->options != options);
trace_bdrv_open_common(bs, filename, flags, drv->format_name);
@@ -688,7 +688,11 @@
bdrv_enable_copy_on_read(bs);
}
- pstrcpy(bs->filename, sizeof(bs->filename), filename);
+ if (filename != NULL) {
+ pstrcpy(bs->filename, sizeof(bs->filename), filename);
+ } else {
+ bs->filename[0] = '\0';
+ }
if (use_bdrv_whitelist && !bdrv_is_whitelisted(drv)) {
return -ENOTSUP;
@@ -708,7 +712,8 @@
bdrv_swap(file, bs);
ret = 0;
} else {
- ret = drv->bdrv_file_open(bs, filename, open_flags);
+ assert(drv->bdrv_parse_filename || filename != NULL);
+ ret = drv->bdrv_file_open(bs, filename, options, open_flags);
}
} else {
assert(file != NULL);
@@ -727,6 +732,7 @@
#ifndef _WIN32
if (bs->is_temporary) {
+ assert(filename != NULL);
unlink(filename);
}
#endif
@@ -742,27 +748,92 @@
/*
* Opens a file using a protocol (file, host_device, nbd, ...)
+ *
+ * options is a QDict of options to pass to the block drivers, or NULL for an
+ * empty set of options. The reference to the QDict belongs to the block layer
+ * after the call (even on failure), so if the caller intends to reuse the
+ * dictionary, it needs to use QINCREF() before calling bdrv_file_open.
*/
-int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags)
+int bdrv_file_open(BlockDriverState **pbs, const char *filename,
+ QDict *options, int flags)
{
BlockDriverState *bs;
BlockDriver *drv;
+ const char *drvname;
int ret;
- drv = bdrv_find_protocol(filename);
- if (!drv) {
- return -ENOENT;
+ /* NULL means an empty set of options */
+ if (options == NULL) {
+ options = qdict_new();
}
bs = bdrv_new("");
- ret = bdrv_open_common(bs, NULL, filename, NULL, flags, drv);
- if (ret < 0) {
- bdrv_delete(bs);
- return ret;
+ bs->options = options;
+ options = qdict_clone_shallow(options);
+
+ /* Find the right block driver */
+ drvname = qdict_get_try_str(options, "driver");
+ if (drvname) {
+ drv = bdrv_find_whitelisted_format(drvname);
+ qdict_del(options, "driver");
+ } else if (filename) {
+ drv = bdrv_find_protocol(filename);
+ } else {
+ qerror_report(ERROR_CLASS_GENERIC_ERROR,
+ "Must specify either driver or file");
+ drv = NULL;
}
+
+ if (!drv) {
+ ret = -ENOENT;
+ goto fail;
+ }
+
+ /* Parse the filename and open it */
+ if (drv->bdrv_parse_filename && filename) {
+ Error *local_err = NULL;
+ drv->bdrv_parse_filename(filename, options, &local_err);
+ if (error_is_set(&local_err)) {
+ qerror_report_err(local_err);
+ error_free(local_err);
+ ret = -EINVAL;
+ goto fail;
+ }
+ } else if (!drv->bdrv_parse_filename && !filename) {
+ qerror_report(ERROR_CLASS_GENERIC_ERROR,
+ "The '%s' block driver requires a file name",
+ drv->format_name);
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ ret = bdrv_open_common(bs, NULL, filename, options, flags, drv);
+ if (ret < 0) {
+ goto fail;
+ }
+
+ /* Check if any unknown options were used */
+ if (qdict_size(options) != 0) {
+ const QDictEntry *entry = qdict_first(options);
+ qerror_report(ERROR_CLASS_GENERIC_ERROR, "Block protocol '%s' doesn't "
+ "support the option '%s'",
+ drv->format_name, entry->key);
+ ret = -EINVAL;
+ goto fail;
+ }
+ QDECREF(options);
+
bs->growable = 1;
*pbs = bs;
return 0;
+
+fail:
+ QDECREF(options);
+ if (!bs->drv) {
+ QDECREF(bs->options);
+ }
+ bdrv_delete(bs);
+ return ret;
}
int bdrv_open_backing_file(BlockDriverState *bs)
@@ -802,6 +873,25 @@
return 0;
}
+static void extract_subqdict(QDict *src, QDict **dst, const char *start)
+{
+ const QDictEntry *entry, *next;
+ const char *p;
+
+ *dst = qdict_new();
+ entry = qdict_first(src);
+
+ while (entry != NULL) {
+ next = qdict_next(src, entry);
+ if (strstart(entry->key, start, &p)) {
+ qobject_incref(entry->value);
+ qdict_put_obj(*dst, p, entry->value);
+ qdict_del(src, entry->key);
+ }
+ entry = next;
+ }
+}
+
/*
* Opens a disk image (raw, qcow2, vmdk, ...)
*
@@ -817,6 +907,7 @@
/* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */
char tmp_filename[PATH_MAX + 1];
BlockDriverState *file = NULL;
+ QDict *file_options = NULL;
/* NULL means an empty set of options */
if (options == NULL) {
@@ -830,11 +921,17 @@
if (flags & BDRV_O_SNAPSHOT) {
BlockDriverState *bs1;
int64_t total_size;
- int is_protocol = 0;
BlockDriver *bdrv_qcow2;
- QEMUOptionParameter *options;
+ QEMUOptionParameter *create_options;
char backing_filename[PATH_MAX];
+ if (qdict_size(options) != 0) {
+ error_report("Can't use snapshot=on with driver-specific options");
+ ret = -EINVAL;
+ goto fail;
+ }
+ assert(filename != NULL);
+
/* if snapshot, we create a temporary backing file and open it
instead of opening 'filename' directly */
@@ -847,9 +944,6 @@
}
total_size = bdrv_getlength(bs1) & BDRV_SECTOR_MASK;
- if (bs1->drv && bs1->drv->protocol_name)
- is_protocol = 1;
-
bdrv_delete(bs1);
ret = get_tmp_filename(tmp_filename, sizeof(tmp_filename));
@@ -858,7 +952,7 @@
}
/* Real path is meaningless for protocols */
- if (is_protocol) {
+ if (path_has_protocol(filename)) {
snprintf(backing_filename, sizeof(backing_filename),
"%s", filename);
} else if (!realpath(filename, backing_filename)) {
@@ -867,17 +961,19 @@
}
bdrv_qcow2 = bdrv_find_format("qcow2");
- options = parse_option_parameters("", bdrv_qcow2->create_options, NULL);
+ create_options = parse_option_parameters("", bdrv_qcow2->create_options,
+ NULL);
- set_option_parameter_int(options, BLOCK_OPT_SIZE, total_size);
- set_option_parameter(options, BLOCK_OPT_BACKING_FILE, backing_filename);
+ set_option_parameter_int(create_options, BLOCK_OPT_SIZE, total_size);
+ set_option_parameter(create_options, BLOCK_OPT_BACKING_FILE,
+ backing_filename);
if (drv) {
- set_option_parameter(options, BLOCK_OPT_BACKING_FMT,
+ set_option_parameter(create_options, BLOCK_OPT_BACKING_FMT,
drv->format_name);
}
- ret = bdrv_create(bdrv_qcow2, tmp_filename, options);
- free_option_parameters(options);
+ ret = bdrv_create(bdrv_qcow2, tmp_filename, create_options);
+ free_option_parameters(create_options);
if (ret < 0) {
goto fail;
}
@@ -892,7 +988,10 @@
flags |= BDRV_O_ALLOW_RDWR;
}
- ret = bdrv_file_open(&file, filename, bdrv_open_flags(bs, flags));
+ extract_subqdict(options, &file_options, "file.");
+
+ ret = bdrv_file_open(&file, filename, file_options,
+ bdrv_open_flags(bs, flags));
if (ret < 0) {
goto fail;
}
@@ -2491,10 +2590,6 @@
return -EACCES;
if (bdrv_in_use(bs))
return -EBUSY;
-
- /* There better not be any in-flight IOs when we truncate the device. */
- bdrv_drain_all();
-
ret = drv->bdrv_truncate(bs, offset);
if (ret == 0) {
ret = refresh_total_sectors(bs, offset >> BDRV_SECTOR_BITS);
diff --git a/block/blkdebug.c b/block/blkdebug.c
index 6f74637..37cfbc7 100644
--- a/block/blkdebug.c
+++ b/block/blkdebug.c
@@ -304,7 +304,8 @@
}
/* Valid blkdebug filenames look like blkdebug:path/to/config:path/to/image */
-static int blkdebug_open(BlockDriverState *bs, const char *filename, int flags)
+static int blkdebug_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVBlkdebugState *s = bs->opaque;
int ret;
@@ -335,7 +336,7 @@
s->state = 1;
/* Open the backing file */
- ret = bdrv_file_open(&bs->file, filename, flags);
+ ret = bdrv_file_open(&bs->file, filename, NULL, flags);
if (ret < 0) {
return ret;
}
diff --git a/block/blkverify.c b/block/blkverify.c
index 2086d97..59e3b05 100644
--- a/block/blkverify.c
+++ b/block/blkverify.c
@@ -69,7 +69,8 @@
}
/* Valid blkverify filenames look like blkverify:path/to/raw_image:path/to/image */
-static int blkverify_open(BlockDriverState *bs, const char *filename, int flags)
+static int blkverify_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVBlkverifyState *s = bs->opaque;
int ret;
@@ -89,7 +90,7 @@
raw = g_strdup(filename);
raw[c - filename] = '\0';
- ret = bdrv_file_open(&bs->file, raw, flags);
+ ret = bdrv_file_open(&bs->file, raw, NULL, flags);
g_free(raw);
if (ret < 0) {
return ret;
diff --git a/block/cow.c b/block/cow.c
index d73e08c..9f94599 100644
--- a/block/cow.c
+++ b/block/cow.c
@@ -279,7 +279,7 @@
return ret;
}
- ret = bdrv_file_open(&cow_bs, filename, BDRV_O_RDWR);
+ ret = bdrv_file_open(&cow_bs, filename, NULL, BDRV_O_RDWR);
if (ret < 0) {
return ret;
}
diff --git a/block/curl.c b/block/curl.c
index 98947da..186e3b0 100644
--- a/block/curl.c
+++ b/block/curl.c
@@ -335,7 +335,8 @@
s->in_use = 0;
}
-static int curl_open(BlockDriverState *bs, const char *filename, int flags)
+static int curl_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVCURLState *s = bs->opaque;
CURLState *state = NULL;
diff --git a/block/dmg.c b/block/dmg.c
index c1066df..3141cb5 100644
--- a/block/dmg.c
+++ b/block/dmg.c
@@ -51,9 +51,16 @@
static int dmg_probe(const uint8_t *buf, int buf_size, const char *filename)
{
- int len=strlen(filename);
- if(len>4 && !strcmp(filename+len-4,".dmg"))
- return 2;
+ int len;
+
+ if (!filename) {
+ return 0;
+ }
+
+ len = strlen(filename);
+ if (len > 4 && !strcmp(filename + len - 4, ".dmg")) {
+ return 2;
+ }
return 0;
}
diff --git a/block/gluster.c b/block/gluster.c
index ccd684d..9ccd4d4 100644
--- a/block/gluster.c
+++ b/block/gluster.c
@@ -283,7 +283,7 @@
}
static int qemu_gluster_open(BlockDriverState *bs, const char *filename,
- int bdrv_flags)
+ QDict *options, int bdrv_flags)
{
BDRVGlusterState *s = bs->opaque;
int open_flags = O_BINARY;
diff --git a/block/iscsi.c b/block/iscsi.c
index 3d52921..51a2889 100644
--- a/block/iscsi.c
+++ b/block/iscsi.c
@@ -1007,7 +1007,8 @@
* We support iscsi url's on the form
* iscsi://[<username>%<password>@]<host>[:<port>]/<targetname>/<lun>
*/
-static int iscsi_open(BlockDriverState *bs, const char *filename, int flags)
+static int iscsi_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
IscsiLun *iscsilun = bs->opaque;
struct iscsi_context *iscsi = NULL;
@@ -1203,7 +1204,7 @@
bs.opaque = g_malloc0(sizeof(struct IscsiLun));
iscsilun = bs.opaque;
- ret = iscsi_open(&bs, filename, 0);
+ ret = iscsi_open(&bs, filename, NULL, 0);
if (ret != 0) {
goto out;
}
diff --git a/block/nbd.c b/block/nbd.c
index a581294..3d711b2 100644
--- a/block/nbd.c
+++ b/block/nbd.c
@@ -32,6 +32,8 @@
#include "block/block_int.h"
#include "qemu/module.h"
#include "qemu/sockets.h"
+#include "qapi/qmp/qjson.h"
+#include "qapi/qmp/qint.h"
#include <sys/types.h>
#include <unistd.h>
@@ -65,17 +67,19 @@
Coroutine *recv_coroutine[MAX_NBD_REQUESTS];
struct nbd_reply reply;
- int is_unix;
- char *host_spec;
+ bool is_unix;
+ QemuOpts *socket_opts;
+
char *export_name; /* An NBD server may export several devices */
} BDRVNBDState;
-static int nbd_parse_uri(BDRVNBDState *s, const char *filename)
+static int nbd_parse_uri(const char *filename, QDict *options)
{
URI *uri;
const char *p;
QueryParams *qp = NULL;
int ret = 0;
+ bool is_unix;
uri = uri_parse(filename);
if (!uri) {
@@ -84,11 +88,11 @@
/* transport */
if (!strcmp(uri->scheme, "nbd")) {
- s->is_unix = false;
+ is_unix = false;
} else if (!strcmp(uri->scheme, "nbd+tcp")) {
- s->is_unix = false;
+ is_unix = false;
} else if (!strcmp(uri->scheme, "nbd+unix")) {
- s->is_unix = true;
+ is_unix = true;
} else {
ret = -EINVAL;
goto out;
@@ -97,32 +101,35 @@
p = uri->path ? uri->path : "/";
p += strspn(p, "/");
if (p[0]) {
- s->export_name = g_strdup(p);
+ qdict_put(options, "export", qstring_from_str(p));
}
qp = query_params_parse(uri->query);
- if (qp->n > 1 || (s->is_unix && !qp->n) || (!s->is_unix && qp->n)) {
+ if (qp->n > 1 || (is_unix && !qp->n) || (!is_unix && qp->n)) {
ret = -EINVAL;
goto out;
}
- if (s->is_unix) {
+ if (is_unix) {
/* nbd+unix:///export?socket=path */
if (uri->server || uri->port || strcmp(qp->p[0].name, "socket")) {
ret = -EINVAL;
goto out;
}
- s->host_spec = g_strdup(qp->p[0].value);
+ qdict_put(options, "path", qstring_from_str(qp->p[0].value));
} else {
- /* nbd[+tcp]://host:port/export */
+ /* nbd[+tcp]://host[:port]/export */
if (!uri->server) {
ret = -EINVAL;
goto out;
}
- if (!uri->port) {
- uri->port = NBD_DEFAULT_PORT;
+
+ qdict_put(options, "host", qstring_from_str(uri->server));
+ if (uri->port) {
+ char* port_str = g_strdup_printf("%d", uri->port);
+ qdict_put(options, "port", qstring_from_str(port_str));
+ g_free(port_str);
}
- s->host_spec = g_strdup_printf("%s:%d", uri->server, uri->port);
}
out:
@@ -133,16 +140,29 @@
return ret;
}
-static int nbd_config(BDRVNBDState *s, const char *filename)
+static void nbd_parse_filename(const char *filename, QDict *options,
+ Error **errp)
{
char *file;
char *export_name;
const char *host_spec;
const char *unixpath;
- int err = -EINVAL;
+
+ if (qdict_haskey(options, "host")
+ || qdict_haskey(options, "port")
+ || qdict_haskey(options, "path"))
+ {
+ error_setg(errp, "host/port/path and a file name may not be specified "
+ "at the same time");
+ return;
+ }
if (strstr(filename, "://")) {
- return nbd_parse_uri(s, filename);
+ int ret = nbd_parse_uri(filename, options);
+ if (ret < 0) {
+ error_setg(errp, "No valid URL specified");
+ }
+ return;
}
file = g_strdup(filename);
@@ -154,34 +174,79 @@
}
export_name[0] = 0; /* truncate 'file' */
export_name += strlen(EN_OPTSTR);
- s->export_name = g_strdup(export_name);
+
+ qdict_put(options, "export", qstring_from_str(export_name));
}
/* extract the host_spec - fail if it's not nbd:... */
if (!strstart(file, "nbd:", &host_spec)) {
+ error_setg(errp, "File name string for NBD must start with 'nbd:'");
+ goto out;
+ }
+
+ if (!*host_spec) {
goto out;
}
/* are we a UNIX or TCP socket? */
if (strstart(host_spec, "unix:", &unixpath)) {
- s->is_unix = true;
- s->host_spec = g_strdup(unixpath);
+ qdict_put(options, "path", qstring_from_str(unixpath));
} else {
- s->is_unix = false;
- s->host_spec = g_strdup(host_spec);
- }
+ InetSocketAddress *addr = NULL;
- err = 0;
+ addr = inet_parse(host_spec, errp);
+ if (error_is_set(errp)) {
+ goto out;
+ }
+
+ qdict_put(options, "host", qstring_from_str(addr->host));
+ qdict_put(options, "port", qstring_from_str(addr->port));
+ qapi_free_InetSocketAddress(addr);
+ }
out:
g_free(file);
- if (err != 0) {
- g_free(s->export_name);
- g_free(s->host_spec);
- }
- return err;
}
+static int nbd_config(BDRVNBDState *s, QDict *options)
+{
+ Error *local_err = NULL;
+
+ if (qdict_haskey(options, "path")) {
+ if (qdict_haskey(options, "host")) {
+ qerror_report(ERROR_CLASS_GENERIC_ERROR, "path and host may not "
+ "be used at the same time.");
+ return -EINVAL;
+ }
+ s->is_unix = true;
+ } else if (qdict_haskey(options, "host")) {
+ s->is_unix = false;
+ } else {
+ return -EINVAL;
+ }
+
+ s->socket_opts = qemu_opts_create_nofail(&socket_optslist);
+
+ qemu_opts_absorb_qdict(s->socket_opts, options, &local_err);
+ if (error_is_set(&local_err)) {
+ qerror_report_err(local_err);
+ error_free(local_err);
+ return -EINVAL;
+ }
+
+ if (!qemu_opt_get(s->socket_opts, "port")) {
+ qemu_opt_set_number(s->socket_opts, "port", NBD_DEFAULT_PORT);
+ }
+
+ s->export_name = g_strdup(qdict_get_try_str(options, "export"));
+ if (s->export_name) {
+ qdict_del(options, "export");
+ }
+
+ return 0;
+}
+
+
static void nbd_coroutine_start(BDRVNBDState *s, struct nbd_request *request)
{
int i;
@@ -328,9 +393,9 @@
size_t blocksize;
if (s->is_unix) {
- sock = unix_socket_outgoing(s->host_spec);
+ sock = unix_socket_outgoing(qemu_opt_get(s->socket_opts, "path"));
} else {
- sock = tcp_socket_outgoing_spec(s->host_spec);
+ sock = tcp_socket_outgoing_opts(s->socket_opts);
}
/* Failed to establish connection */
@@ -376,7 +441,8 @@
closesocket(s->sock);
}
-static int nbd_open(BlockDriverState *bs, const char* filename, int flags)
+static int nbd_open(BlockDriverState *bs, const char* filename,
+ QDict *options, int flags)
{
BDRVNBDState *s = bs->opaque;
int result;
@@ -385,7 +451,7 @@
qemu_co_mutex_init(&s->free_sema);
/* Pop the config into our state object. Exit if invalid. */
- result = nbd_config(s, filename);
+ result = nbd_config(s, options);
if (result != 0) {
return result;
}
@@ -549,7 +615,7 @@
{
BDRVNBDState *s = bs->opaque;
g_free(s->export_name);
- g_free(s->host_spec);
+ qemu_opts_del(s->socket_opts);
nbd_teardown_connection(bs);
}
@@ -565,6 +631,7 @@
.format_name = "nbd",
.protocol_name = "nbd",
.instance_size = sizeof(BDRVNBDState),
+ .bdrv_parse_filename = nbd_parse_filename,
.bdrv_file_open = nbd_open,
.bdrv_co_readv = nbd_co_readv,
.bdrv_co_writev = nbd_co_writev,
@@ -578,6 +645,7 @@
.format_name = "nbd",
.protocol_name = "nbd+tcp",
.instance_size = sizeof(BDRVNBDState),
+ .bdrv_parse_filename = nbd_parse_filename,
.bdrv_file_open = nbd_open,
.bdrv_co_readv = nbd_co_readv,
.bdrv_co_writev = nbd_co_writev,
@@ -591,6 +659,7 @@
.format_name = "nbd",
.protocol_name = "nbd+unix",
.instance_size = sizeof(BDRVNBDState),
+ .bdrv_parse_filename = nbd_parse_filename,
.bdrv_file_open = nbd_open,
.bdrv_co_readv = nbd_co_readv,
.bdrv_co_writev = nbd_co_writev,
diff --git a/block/qcow.c b/block/qcow.c
index f6750a5..13d396b 100644
--- a/block/qcow.c
+++ b/block/qcow.c
@@ -679,7 +679,7 @@
return ret;
}
- ret = bdrv_file_open(&qcow_bs, filename, BDRV_O_RDWR);
+ ret = bdrv_file_open(&qcow_bs, filename, NULL, BDRV_O_RDWR);
if (ret < 0) {
return ret;
}
diff --git a/block/qcow2.c b/block/qcow2.c
index 1f99866..8ea696a 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -29,6 +29,7 @@
#include "block/qcow2.h"
#include "qemu/error-report.h"
#include "qapi/qmp/qerror.h"
+#include "qapi/qmp/qbool.h"
#include "trace.h"
/*
@@ -520,7 +521,7 @@
goto fail;
}
- s->use_lazy_refcounts = qemu_opt_get_bool(opts, "lazy_refcounts",
+ s->use_lazy_refcounts = qemu_opt_get_bool(opts, QCOW2_OPT_LAZY_REFCOUNTS,
(s->compatible_features & QCOW2_COMPAT_LAZY_REFCOUNTS));
qemu_opts_del(opts);
@@ -930,6 +931,7 @@
AES_KEY aes_encrypt_key;
AES_KEY aes_decrypt_key;
uint32_t crypt_method = 0;
+ QDict *options;
/*
* Backing files are read-only which makes all of their metadata immutable,
@@ -944,8 +946,14 @@
qcow2_close(bs);
+ options = qdict_new();
+ qdict_put(options, QCOW2_OPT_LAZY_REFCOUNTS,
+ qbool_from_int(s->use_lazy_refcounts));
+
memset(s, 0, sizeof(BDRVQcowState));
- qcow2_open(bs, NULL, flags);
+ qcow2_open(bs, options, flags);
+
+ QDECREF(options);
if (crypt_method) {
s->crypt_method = crypt_method;
@@ -1246,7 +1254,7 @@
return ret;
}
- ret = bdrv_file_open(&bs, filename, BDRV_O_RDWR);
+ ret = bdrv_file_open(&bs, filename, NULL, BDRV_O_RDWR);
if (ret < 0) {
return ret;
}
diff --git a/block/qcow2.h b/block/qcow2.h
index 103abdb..e4b5e11 100644
--- a/block/qcow2.h
+++ b/block/qcow2.h
@@ -58,6 +58,9 @@
#define DEFAULT_CLUSTER_SIZE 65536
+
+#define QCOW2_OPT_LAZY_REFCOUNTS "lazy_refcounts"
+
typedef struct QCowHeader {
uint32_t magic;
uint32_t version;
diff --git a/block/qed.c b/block/qed.c
index 46e12b3..4651403 100644
--- a/block/qed.c
+++ b/block/qed.c
@@ -558,7 +558,7 @@
return ret;
}
- ret = bdrv_file_open(&bs, filename, BDRV_O_RDWR | BDRV_O_CACHE_WB);
+ ret = bdrv_file_open(&bs, filename, NULL, BDRV_O_RDWR | BDRV_O_CACHE_WB);
if (ret < 0) {
return ret;
}
diff --git a/block/raw-posix.c b/block/raw-posix.c
index 8a3cdbc..99ac869 100644
--- a/block/raw-posix.c
+++ b/block/raw-posix.c
@@ -303,7 +303,8 @@
return 0;
}
-static int raw_open(BlockDriverState *bs, const char *filename, int flags)
+static int raw_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
@@ -1292,7 +1293,8 @@
return 0;
}
-static int hdev_open(BlockDriverState *bs, const char *filename, int flags)
+static int hdev_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
int ret;
@@ -1530,7 +1532,8 @@
};
#ifdef __linux__
-static int floppy_open(BlockDriverState *bs, const char *filename, int flags)
+static int floppy_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
int ret;
@@ -1652,7 +1655,8 @@
.bdrv_eject = floppy_eject,
};
-static int cdrom_open(BlockDriverState *bs, const char *filename, int flags)
+static int cdrom_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
@@ -1760,7 +1764,8 @@
#endif /* __linux__ */
#if defined (__FreeBSD__) || defined(__FreeBSD_kernel__)
-static int cdrom_open(BlockDriverState *bs, const char *filename, int flags)
+static int cdrom_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
int ret;
diff --git a/block/raw-win32.c b/block/raw-win32.c
index 18e0068..ece2f1a 100644
--- a/block/raw-win32.c
+++ b/block/raw-win32.c
@@ -221,7 +221,8 @@
}
}
-static int raw_open(BlockDriverState *bs, const char *filename, int flags)
+static int raw_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
int access_flags;
@@ -494,7 +495,8 @@
return 0;
}
-static int hdev_open(BlockDriverState *bs, const char *filename, int flags)
+static int hdev_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRawState *s = bs->opaque;
int access_flags, create_flags;
diff --git a/block/rbd.c b/block/rbd.c
index 8cd10a7..1a8ea6d 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -441,7 +441,8 @@
return (s->qemu_aio_count > 0);
}
-static int qemu_rbd_open(BlockDriverState *bs, const char *filename, int flags)
+static int qemu_rbd_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
BDRVRBDState *s = bs->opaque;
char pool[RBD_MAX_POOL_NAME_SIZE];
diff --git a/block/sheepdog.c b/block/sheepdog.c
index 4245328..bb67c4c 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -65,6 +65,7 @@
#define SD_RES_WAIT_FOR_FORMAT 0x16 /* Waiting for a format operation */
#define SD_RES_WAIT_FOR_JOIN 0x17 /* Waiting for other nodes joining */
#define SD_RES_JOIN_FAILED 0x18 /* Target node had failed to join sheepdog */
+#define SD_RES_HALT 0x19 /* Sheepdog is stopped serving IO request */
/*
* Object ID rules
@@ -344,6 +345,7 @@
{SD_RES_WAIT_FOR_FORMAT, "Sheepdog is waiting for a format operation"},
{SD_RES_WAIT_FOR_JOIN, "Sheepdog is waiting for other nodes joining"},
{SD_RES_JOIN_FAILED, "Target node had failed to join sheepdog"},
+ {SD_RES_HALT, "Sheepdog is stopped serving IO request"},
};
for (i = 0; i < ARRAY_SIZE(errors); ++i) {
@@ -1124,7 +1126,8 @@
create, cache_flags);
}
-static int sd_open(BlockDriverState *bs, const char *filename, int flags)
+static int sd_open(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags)
{
int ret, fd;
uint32_t vid = 0;
@@ -1267,7 +1270,7 @@
void *buf = g_malloc0(SD_DATA_OBJ_SIZE);
int ret;
- ret = bdrv_file_open(&bs, filename, BDRV_O_RDWR);
+ ret = bdrv_file_open(&bs, filename, NULL, BDRV_O_RDWR);
if (ret < 0) {
goto out;
}
@@ -1365,7 +1368,7 @@
goto out;
}
- ret = bdrv_file_open(&bs, backing_file, 0);
+ ret = bdrv_file_open(&bs, backing_file, NULL, 0);
if (ret < 0) {
goto out;
}
diff --git a/block/vmdk.c b/block/vmdk.c
index e92104a..7bad757 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -661,7 +661,7 @@
path_combine(extent_path, sizeof(extent_path),
desc_file_path, fname);
- ret = bdrv_file_open(&extent_file, extent_path, bs->open_flags);
+ ret = bdrv_file_open(&extent_file, extent_path, NULL, bs->open_flags);
if (ret) {
return ret;
}
diff --git a/block/vvfat.c b/block/vvfat.c
index b8eb38a..ef74c30 100644
--- a/block/vvfat.c
+++ b/block/vvfat.c
@@ -988,7 +988,8 @@
s->bs = bs;
}
-static int vvfat_open(BlockDriverState *bs, const char* dirname, int flags)
+static int vvfat_open(BlockDriverState *bs, const char* dirname,
+ QDict *options, int flags)
{
BDRVVVFATState *s = bs->opaque;
int i, cyls, heads, secs;
diff --git a/blockdev.c b/blockdev.c
index 09f76b7..8cdc9ce 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -658,7 +658,11 @@
abort();
}
if (!file || !*file) {
- return dinfo;
+ if (qdict_size(bs_opts)) {
+ file = NULL;
+ } else {
+ return dinfo;
+ }
}
if (snapshot) {
/* always use cache=unsafe with snapshot */
@@ -697,10 +701,10 @@
if (ret < 0) {
if (ret == -EMEDIUMTYPE) {
error_report("could not open disk image %s: not in %s format",
- file, drv->format_name);
+ file ?: dinfo->id, drv->format_name);
} else {
error_report("could not open disk image %s: %s",
- file, strerror(-ret));
+ file ?: dinfo->id, strerror(-ret));
}
goto err;
}
@@ -1127,6 +1131,9 @@
return;
}
+ /* complete all in-flight operations before resizing the device */
+ bdrv_drain_all();
+
switch (bdrv_truncate(bs, size)) {
case 0:
break;
diff --git a/bt-host.c b/bt-host.c
index 2092754..2da3c32 100644
--- a/bt-host.c
+++ b/bt-host.c
@@ -171,7 +171,7 @@
hci_filter_all_ptypes(&flt);
hci_filter_all_events(&flt);
- if (setsockopt(fd, SOL_HCI, HCI_FILTER, &flt, sizeof(flt)) < 0) {
+ if (qemu_setsockopt(fd, SOL_HCI, HCI_FILTER, &flt, sizeof(flt)) < 0) {
fprintf(stderr, "qemu: Can't set HCI filter on socket (%i)\n", errno);
return 0;
}
diff --git a/configure b/configure
index 46a7594..f2af714 100755
--- a/configure
+++ b/configure
@@ -217,7 +217,7 @@
rbd=""
smartcard_nss=""
usb_redir=""
-opengl=""
+glx=""
zlib="yes"
guest_agent="yes"
want_tools="yes"
@@ -858,9 +858,9 @@
;;
--enable-vhost-net) vhost_net="yes"
;;
- --disable-opengl) opengl="no"
+ --disable-glx) glx="no"
;;
- --enable-opengl) opengl="yes"
+ --enable-glx) glx="yes"
;;
--disable-rbd) rbd="no"
;;
@@ -961,6 +961,7 @@
mipsel-softmmu \
mips64-softmmu \
mips64el-softmmu \
+moxie-softmmu \
or32-softmmu \
ppc-softmmu \
ppcemb-softmmu \
@@ -1050,6 +1051,7 @@
echo " --datadir=PATH install firmware in PATH$confsuffix"
echo " --docdir=PATH install documentation in PATH$confsuffix"
echo " --bindir=PATH install binaries in PATH"
+echo " --libdir=PATH install libraries in PATH"
echo " --sysconfdir=PATH install config in PATH$confsuffix"
echo " --localstatedir=PATH install local state in PATH"
echo " --with-confsuffix=SUFFIX suffix for QEMU data inside datadir and sysconfdir [$confsuffix]"
@@ -2435,23 +2437,23 @@
fi
##########################################
-# opengl probe, used by milkymist-tmu2
-if test "$opengl" != "no" ; then
- opengl_libs="-lGL -lX11"
+# GLX probe, used by milkymist-tmu2
+if test "$glx" != "no" ; then
+ glx_libs="-lGL -lX11"
cat > $TMPC << EOF
#include <X11/Xlib.h>
#include <GL/gl.h>
#include <GL/glx.h>
-int main(void) { return GL_VERSION != 0; }
+int main(void) { glBegin(0); glXQueryVersion(0,0,0); return 0; }
EOF
- if compile_prog "" "-lGL" ; then
- opengl=yes
+ if compile_prog "" "-lGL -lX11" ; then
+ glx=yes
else
- if test "$opengl" = "yes" ; then
- feature_not_found "opengl"
+ if test "$glx" = "yes" ; then
+ feature_not_found "glx"
fi
- opengl_libs=
- opengl=no
+ glx_libs=
+ glx=no
fi
fi
@@ -3429,7 +3431,7 @@
echo "xfsctl support $xfs"
echo "nss used $smartcard_nss"
echo "usb net redir $usb_redir"
-echo "OpenGL support $opengl"
+echo "GLX support $glx"
echo "libiscsi support $libiscsi"
echo "build guest agent $guest_agent"
echo "seccomp support $seccomp"
@@ -3740,8 +3742,8 @@
echo "CONFIG_USB_REDIR=y" >> $config_host_mak
fi
-if test "$opengl" = "yes" ; then
- echo "CONFIG_OPENGL=y" >> $config_host_mak
+if test "$glx" = "yes" ; then
+ echo "CONFIG_GLX=y" >> $config_host_mak
fi
if test "$libiscsi" = "yes" ; then
@@ -3946,7 +3948,7 @@
target_bigendian="no"
case "$target_arch2" in
- armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+ armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
target_bigendian=yes
;;
esac
@@ -4019,7 +4021,7 @@
target_nptl="yes"
;;
lm32)
- target_libs_softmmu="$opengl_libs"
+ target_libs_softmmu="$glx_libs"
;;
m68k)
bflt="yes"
@@ -4050,6 +4052,8 @@
echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
target_long_alignment=8
;;
+ moxie)
+ ;;
or32)
TARGET_ARCH=openrisc
TARGET_BASE_ARCH=openrisc
@@ -4287,6 +4291,10 @@
echo "CONFIG_MIPS_DIS=y" >> $config_target_mak
echo "CONFIG_MIPS_DIS=y" >> config-all-disas.mak
;;
+ moxie*)
+ echo "CONFIG_MOXIE_DIS=y" >> $config_target_mak
+ echo "CONFIG_MOXIE_DIS=y" >> config-all-disas.mak
+ ;;
or32)
echo "CONFIG_OPENRISC_DIS=y" >> $config_target_mak
echo "CONFIG_OPENRISC_DIS=y" >> config-all-disas.mak
diff --git a/cpu-exec.c b/cpu-exec.c
index 94fedc5..e74e556 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -240,6 +240,7 @@
#elif defined(TARGET_LM32)
#elif defined(TARGET_MICROBLAZE)
#elif defined(TARGET_MIPS)
+#elif defined(TARGET_MOXIE)
#elif defined(TARGET_OPENRISC)
#elif defined(TARGET_SH4)
#elif defined(TARGET_CRIS)
@@ -570,10 +571,7 @@
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
/* restore flags in standard format */
#if defined(TARGET_I386)
- env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
- | (DF & DF_MASK);
log_cpu_state(env, CPU_DUMP_CCOP);
- env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_M68K)
cpu_m68k_flush_flags(env, env->cc_op);
env->cc_op = CC_OP_FLAGS;
@@ -692,6 +690,7 @@
| env->cc_dest | (env->cc_x << 4);
#elif defined(TARGET_MICROBLAZE)
#elif defined(TARGET_MIPS)
+#elif defined(TARGET_MOXIE)
#elif defined(TARGET_OPENRISC)
#elif defined(TARGET_SH4)
#elif defined(TARGET_ALPHA)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 68b2045..ab87035 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -42,6 +42,7 @@
CONFIG_PL181=y
CONFIG_PL190=y
CONFIG_PL310=y
+CONFIG_PL330=y
CONFIG_CADENCE=y
CONFIG_XGMAC=y
diff --git a/default-configs/moxie-softmmu.mak b/default-configs/moxie-softmmu.mak
new file mode 100644
index 0000000..8ede8d5
--- /dev/null
+++ b/default-configs/moxie-softmmu.mak
@@ -0,0 +1 @@
+# Default configuration for moxie-softmmu
diff --git a/default-configs/pci.mak b/default-configs/pci.mak
index ee2d18d..ce56d58 100644
--- a/default-configs/pci.mak
+++ b/default-configs/pci.mak
@@ -13,6 +13,7 @@
CONFIG_MEGASAS_SCSI_PCI=y
CONFIG_RTL8139_PCI=y
CONFIG_E1000_PCI=y
+CONFIG_VMXNET3_PCI=y
CONFIG_IDE_CORE=y
CONFIG_IDE_QDEV=y
CONFIG_IDE_PCI=y
diff --git a/disas.c b/disas.c
index a46faee..74d3ba0 100644
--- a/disas.c
+++ b/disas.c
@@ -256,6 +256,9 @@
#elif defined(TARGET_MICROBLAZE)
s.info.mach = bfd_arch_microblaze;
print_insn = print_insn_microblaze;
+#elif defined(TARGET_MOXIE)
+ s.info.mach = bfd_arch_moxie;
+ print_insn = print_insn_moxie;
#elif defined(TARGET_LM32)
s.info.mach = bfd_mach_lm32;
print_insn = print_insn_lm32;
@@ -462,6 +465,9 @@
#elif defined(TARGET_S390X)
s.info.mach = bfd_mach_s390_64;
print_insn = print_insn_s390;
+#elif defined(TARGET_MOXIE)
+ s.info.mach = bfd_arch_moxie;
+ print_insn = print_insn_moxie;
#elif defined(TARGET_LM32)
s.info.mach = bfd_mach_lm32;
print_insn = print_insn_lm32;
diff --git a/disas/Makefile.objs b/disas/Makefile.objs
index ed75f9a..3b1e77a 100644
--- a/disas/Makefile.objs
+++ b/disas/Makefile.objs
@@ -7,6 +7,7 @@
common-obj-$(CONFIG_M68K_DIS) += m68k.o
common-obj-$(CONFIG_MICROBLAZE_DIS) += microblaze.o
common-obj-$(CONFIG_MIPS_DIS) += mips.o
+common-obj-$(CONFIG_MOXIE_DIS) += moxie.o
common-obj-$(CONFIG_PPC_DIS) += ppc.o
common-obj-$(CONFIG_S390_DIS) += s390.o
common-obj-$(CONFIG_SH4_DIS) += sh4.o
diff --git a/disas/lm32.c b/disas/lm32.c
index a8eefe0..1718c86 100644
--- a/disas/lm32.c
+++ b/disas/lm32.c
@@ -303,11 +303,11 @@
}
case 'c': {
uint8_t csr;
- const char *csr_name;
+ const Lm32CsrInfo *info;
csr = (op >> 21) & 0x1f;
- csr_name = find_csr_info(csr)->name;
- if (csr_name) {
- fprintf_fn(stream, "%s", csr_name);
+ info = find_csr_info(csr);
+ if (info) {
+ fprintf_fn(stream, "%s", info->name);
} else {
fprintf_fn(stream, "0x%x", csr);
}
diff --git a/disas/moxie.c b/disas/moxie.c
new file mode 100644
index 0000000..4c5f180
--- /dev/null
+++ b/disas/moxie.c
@@ -0,0 +1,360 @@
+/* Disassemble moxie instructions.
+ Copyright (c) 2009 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>. */
+
+#include <stdio.h>
+#define STATIC_TABLE
+#define DEFINE_TABLE
+
+#include "disas/bfd.h"
+
+static void *stream;
+
+/* Form 1 instructions come in different flavors:
+
+ Some have no arguments (MOXIE_F1_NARG)
+ Some only use the A operand (MOXIE_F1_A)
+ Some use A and B registers (MOXIE_F1_AB)
+ Some use A and consume a 4 byte immediate value (MOXIE_F1_A4)
+ Some use just a 4 byte immediate value (MOXIE_F1_4)
+ Some use just a 4 byte memory address (MOXIE_F1_M)
+ Some use B and an indirect A (MOXIE_F1_AiB)
+ Some use A and an indirect B (MOXIE_F1_ABi)
+ Some consume a 4 byte immediate value and use X (MOXIE_F1_4A)
+ Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4)
+ Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4)
+
+ Form 2 instructions also come in different flavors:
+
+ Some have no arguments (MOXIE_F2_NARG)
+ Some use the A register and an 8-bit value (MOXIE_F2_A8V)
+
+ Form 3 instructions also come in different flavors:
+
+ Some have no arguments (MOXIE_F3_NARG)
+ Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */
+
+#define MOXIE_F1_NARG 0x100
+#define MOXIE_F1_A 0x101
+#define MOXIE_F1_AB 0x102
+/* #define MOXIE_F1_ABC 0x103 */
+#define MOXIE_F1_A4 0x104
+#define MOXIE_F1_4 0x105
+#define MOXIE_F1_AiB 0x106
+#define MOXIE_F1_ABi 0x107
+#define MOXIE_F1_4A 0x108
+#define MOXIE_F1_AiB4 0x109
+#define MOXIE_F1_ABi4 0x10a
+#define MOXIE_F1_M 0x10b
+
+#define MOXIE_F2_NARG 0x200
+#define MOXIE_F2_A8V 0x201
+
+#define MOXIE_F3_NARG 0x300
+#define MOXIE_F3_PCREL 0x301
+
+typedef struct moxie_opc_info_t {
+ short opcode;
+ unsigned itype;
+ const char * name;
+} moxie_opc_info_t;
+
+extern const moxie_opc_info_t moxie_form1_opc_info[64];
+extern const moxie_opc_info_t moxie_form2_opc_info[4];
+extern const moxie_opc_info_t moxie_form3_opc_info[16];
+
+/* The moxie processor's 16-bit instructions come in two forms:
+
+ FORM 1 instructions start with a 0 bit...
+
+ 0oooooooaaaabbbb
+ 0 F
+
+ ooooooo - form 1 opcode number
+ aaaa - operand A
+ bbbb - operand B
+
+ FORM 2 instructions start with bits "10"...
+
+ 10ooaaaavvvvvvvv
+ 0 F
+
+ oo - form 2 opcode number
+ aaaa - operand A
+ vvvvvvvv - 8-bit immediate value
+
+ FORM 3 instructions start with a bits "11"...
+
+ 11oooovvvvvvvvvv
+ 0 F
+
+ oooo - form 3 opcode number
+ vvvvvvvvvv - 10-bit immediate value. */
+
+const moxie_opc_info_t moxie_form1_opc_info[64] =
+ {
+ { 0x00, MOXIE_F1_NARG, "nop" },
+ { 0x01, MOXIE_F1_A4, "ldi.l" },
+ { 0x02, MOXIE_F1_AB, "mov" },
+ { 0x03, MOXIE_F1_M, "jsra" },
+ { 0x04, MOXIE_F1_NARG, "ret" },
+ { 0x05, MOXIE_F1_AB, "add.l" },
+ { 0x06, MOXIE_F1_AB, "push" },
+ { 0x07, MOXIE_F1_AB, "pop" },
+ { 0x08, MOXIE_F1_A4, "lda.l" },
+ { 0x09, MOXIE_F1_4A, "sta.l" },
+ { 0x0a, MOXIE_F1_ABi, "ld.l" },
+ { 0x0b, MOXIE_F1_AiB, "st.l" },
+ { 0x0c, MOXIE_F1_ABi4, "ldo.l" },
+ { 0x0d, MOXIE_F1_AiB4, "sto.l" },
+ { 0x0e, MOXIE_F1_AB, "cmp" },
+ { 0x0f, MOXIE_F1_NARG, "bad" },
+ { 0x10, MOXIE_F1_NARG, "bad" },
+ { 0x11, MOXIE_F1_NARG, "bad" },
+ { 0x12, MOXIE_F1_NARG, "bad" },
+ { 0x13, MOXIE_F1_NARG, "bad" },
+ { 0x14, MOXIE_F1_NARG, "bad" },
+ { 0x15, MOXIE_F1_NARG, "bad" },
+ { 0x16, MOXIE_F1_NARG, "bad" },
+ { 0x17, MOXIE_F1_NARG, "bad" },
+ { 0x18, MOXIE_F1_NARG, "bad" },
+ { 0x19, MOXIE_F1_A, "jsr" },
+ { 0x1a, MOXIE_F1_M, "jmpa" },
+ { 0x1b, MOXIE_F1_A4, "ldi.b" },
+ { 0x1c, MOXIE_F1_ABi, "ld.b" },
+ { 0x1d, MOXIE_F1_A4, "lda.b" },
+ { 0x1e, MOXIE_F1_AiB, "st.b" },
+ { 0x1f, MOXIE_F1_4A, "sta.b" },
+ { 0x20, MOXIE_F1_A4, "ldi.s" },
+ { 0x21, MOXIE_F1_ABi, "ld.s" },
+ { 0x22, MOXIE_F1_A4, "lda.s" },
+ { 0x23, MOXIE_F1_AiB, "st.s" },
+ { 0x24, MOXIE_F1_4A, "sta.s" },
+ { 0x25, MOXIE_F1_A, "jmp" },
+ { 0x26, MOXIE_F1_AB, "and" },
+ { 0x27, MOXIE_F1_AB, "lshr" },
+ { 0x28, MOXIE_F1_AB, "ashl" },
+ { 0x29, MOXIE_F1_AB, "sub.l" },
+ { 0x2a, MOXIE_F1_AB, "neg" },
+ { 0x2b, MOXIE_F1_AB, "or" },
+ { 0x2c, MOXIE_F1_AB, "not" },
+ { 0x2d, MOXIE_F1_AB, "ashr" },
+ { 0x2e, MOXIE_F1_AB, "xor" },
+ { 0x2f, MOXIE_F1_AB, "mul.l" },
+ { 0x30, MOXIE_F1_4, "swi" },
+ { 0x31, MOXIE_F1_AB, "div.l" },
+ { 0x32, MOXIE_F1_AB, "udiv.l" },
+ { 0x33, MOXIE_F1_AB, "mod.l" },
+ { 0x34, MOXIE_F1_AB, "umod.l" },
+ { 0x35, MOXIE_F1_NARG, "brk" },
+ { 0x36, MOXIE_F1_ABi4, "ldo.b" },
+ { 0x37, MOXIE_F1_AiB4, "sto.b" },
+ { 0x38, MOXIE_F1_ABi4, "ldo.s" },
+ { 0x39, MOXIE_F1_AiB4, "sto.s" },
+ { 0x3a, MOXIE_F1_NARG, "bad" },
+ { 0x3b, MOXIE_F1_NARG, "bad" },
+ { 0x3c, MOXIE_F1_NARG, "bad" },
+ { 0x3d, MOXIE_F1_NARG, "bad" },
+ { 0x3e, MOXIE_F1_NARG, "bad" },
+ { 0x3f, MOXIE_F1_NARG, "bad" }
+ };
+
+const moxie_opc_info_t moxie_form2_opc_info[4] =
+ {
+ { 0x00, MOXIE_F2_A8V, "inc" },
+ { 0x01, MOXIE_F2_A8V, "dec" },
+ { 0x02, MOXIE_F2_A8V, "gsr" },
+ { 0x03, MOXIE_F2_A8V, "ssr" }
+ };
+
+const moxie_opc_info_t moxie_form3_opc_info[16] =
+ {
+ { 0x00, MOXIE_F3_PCREL,"beq" },
+ { 0x01, MOXIE_F3_PCREL,"bne" },
+ { 0x02, MOXIE_F3_PCREL,"blt" },
+ { 0x03, MOXIE_F3_PCREL,"bgt" },
+ { 0x04, MOXIE_F3_PCREL,"bltu" },
+ { 0x05, MOXIE_F3_PCREL,"bgtu" },
+ { 0x06, MOXIE_F3_PCREL,"bge" },
+ { 0x07, MOXIE_F3_PCREL,"ble" },
+ { 0x08, MOXIE_F3_PCREL,"bgeu" },
+ { 0x09, MOXIE_F3_PCREL,"bleu" },
+ { 0x0a, MOXIE_F3_NARG, "bad" },
+ { 0x0b, MOXIE_F3_NARG, "bad" },
+ { 0x0c, MOXIE_F3_NARG, "bad" },
+ { 0x0d, MOXIE_F3_NARG, "bad" },
+ { 0x0e, MOXIE_F3_NARG, "bad" },
+ { 0x0f, MOXIE_F3_NARG, "bad" }
+ };
+
+/* Macros to extract operands from the instruction word. */
+#define OP_A(i) ((i >> 4) & 0xf)
+#define OP_B(i) (i & 0xf)
+#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)
+
+static const char * reg_names[16] =
+ { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5",
+ "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" };
+
+int
+print_insn_moxie(bfd_vma addr, struct disassemble_info * info)
+{
+ int length = 2;
+ int status;
+ stream = info->stream;
+ const moxie_opc_info_t * opcode;
+ bfd_byte buffer[4];
+ unsigned short iword;
+ fprintf_function fpr = info->fprintf_func;
+
+ if ((status = info->read_memory_func(addr, buffer, 2, info)))
+ goto fail;
+ iword = (bfd_getb16(buffer) >> 16);
+
+ /* Form 1 instructions have the high bit set to 0. */
+ if ((iword & (1<<15)) == 0) {
+ /* Extract the Form 1 opcode. */
+ opcode = &moxie_form1_opc_info[iword >> 8];
+ switch (opcode->itype) {
+ case MOXIE_F1_NARG:
+ fpr(stream, "%s", opcode->name);
+ break;
+ case MOXIE_F1_A:
+ fpr(stream, "%s\t%s", opcode->name,
+ reg_names[OP_A(iword)]);
+ break;
+ case MOXIE_F1_AB:
+ fpr(stream, "%s\t%s, %s", opcode->name,
+ reg_names[OP_A(iword)],
+ reg_names[OP_B(iword)]);
+ break;
+ case MOXIE_F1_A4:
+ {
+ unsigned imm;
+ if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
+ goto fail;
+ imm = bfd_getb32(buffer);
+ fpr(stream, "%s\t%s, 0x%x", opcode->name,
+ reg_names[OP_A(iword)], imm);
+ length = 6;
+ }
+ break;
+ case MOXIE_F1_4:
+ {
+ unsigned imm;
+ if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
+ goto fail;
+ imm = bfd_getb32(buffer);
+ fpr(stream, "%s\t0x%x", opcode->name, imm);
+ length = 6;
+ }
+ break;
+ case MOXIE_F1_M:
+ {
+ unsigned imm;
+ if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
+ goto fail;
+ imm = bfd_getb32(buffer);
+ fpr(stream, "%s\t", opcode->name);
+ info->print_address_func((bfd_vma) imm, info);
+ length = 6;
+ }
+ break;
+ case MOXIE_F1_AiB:
+ fpr (stream, "%s\t(%s), %s", opcode->name,
+ reg_names[OP_A(iword)], reg_names[OP_B(iword)]);
+ break;
+ case MOXIE_F1_ABi:
+ fpr(stream, "%s\t%s, (%s)", opcode->name,
+ reg_names[OP_A(iword)], reg_names[OP_B(iword)]);
+ break;
+ case MOXIE_F1_4A:
+ {
+ unsigned imm;
+ if ((status = info->read_memory_func(addr + 2, buffer, 4, info)))
+ goto fail;
+ imm = bfd_getb32(buffer);
+ fpr(stream, "%s\t0x%x, %s",
+ opcode->name, imm, reg_names[OP_A(iword)]);
+ length = 6;
+ }
+ break;
+ case MOXIE_F1_AiB4:
+ {
+ unsigned imm;
+ if ((status = info->read_memory_func(addr+2, buffer, 4, info)))
+ goto fail;
+ imm = bfd_getb32(buffer);
+ fpr(stream, "%s\t0x%x(%s), %s", opcode->name,
+ imm,
+ reg_names[OP_A(iword)],
+ reg_names[OP_B(iword)]);
+ length = 6;
+ }
+ break;
+ case MOXIE_F1_ABi4:
+ {
+ unsigned imm;
+ if ((status = info->read_memory_func(addr+2, buffer, 4, info)))
+ goto fail;
+ imm = bfd_getb32(buffer);
+ fpr(stream, "%s\t%s, 0x%x(%s)",
+ opcode->name,
+ reg_names[OP_A(iword)],
+ imm,
+ reg_names[OP_B(iword)]);
+ length = 6;
+ }
+ break;
+ default:
+ abort();
+ }
+ }
+ else if ((iword & (1<<14)) == 0) {
+ /* Extract the Form 2 opcode. */
+ opcode = &moxie_form2_opc_info[(iword >> 12) & 3];
+ switch (opcode->itype) {
+ case MOXIE_F2_A8V:
+ fpr(stream, "%s\t%s, 0x%x",
+ opcode->name,
+ reg_names[(iword >> 8) & 0xf],
+ iword & ((1 << 8) - 1));
+ break;
+ case MOXIE_F2_NARG:
+ fpr(stream, "%s", opcode->name);
+ break;
+ default:
+ abort();
+ }
+ } else {
+ /* Extract the Form 3 opcode. */
+ opcode = &moxie_form3_opc_info[(iword >> 10) & 15];
+ switch (opcode->itype) {
+ case MOXIE_F3_PCREL:
+ fpr(stream, "%s\t", opcode->name);
+ info->print_address_func((bfd_vma) (addr + INST2OFFSET(iword) + 2),
+ info);
+ break;
+ default:
+ abort();
+ }
+ }
+
+ return length;
+
+ fail:
+ info->memory_error_func(status, addr, info);
+ return -1;
+}
diff --git a/docs/usb-storage.txt b/docs/usb-storage.txt
index fa93111..c5a3866 100644
--- a/docs/usb-storage.txt
+++ b/docs/usb-storage.txt
@@ -5,7 +5,7 @@
QEMU has three devices for usb storage emulation.
Number one emulates the classic bulk-only transport protocol which is
-used by 99% of the usb sticks on the marked today and is called
+used by 99% of the usb sticks on the market today and is called
"usb-storage". Usage (hooking up to xhci, other host controllers work
too):
@@ -36,7 +36,7 @@
the guest will not be able to see the difference. The qemu command
line interface is simliar to usb-uas though, i.e. no automatic scsi
disk creation. It also features support for up to 16 LUNs. The LUN
-numbers must be continous, i.e. for three devices you must use 0+1+2.
+numbers must be continuous, i.e. for three devices you must use 0+1+2.
The 0+1+5 numbering from the "usb-uas" example isn't going to work
with "usb-bot".
diff --git a/gdbstub.c b/gdbstub.c
index 43b7d4d..a666cb5 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -781,7 +781,8 @@
/* fpscr */
if (gdb_has_xml)
return 0;
- return 4;
+ store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
+ return sizeof(target_ulong);
}
}
return 0;
@@ -2887,7 +2888,7 @@
/* allow fast reuse */
val = 1;
- setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
+ qemu_setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val));
sockaddr.sin_family = AF_INET;
sockaddr.sin_port = htons(port);
diff --git a/hmp-commands.hx b/hmp-commands.hx
index df44906..3d98604 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -1643,6 +1643,8 @@
show roms
@item info tpm
show the TPM device
+@item info cpu_max
+show the number of CPUs supported by the machine being emulated.
@end table
ETEXI
diff --git a/hmp.c b/hmp.c
index b0a861c..dbe9b90 100644
--- a/hmp.c
+++ b/hmp.c
@@ -173,6 +173,8 @@
info->ram->total >> 10);
monitor_printf(mon, "duplicate: %" PRIu64 " pages\n",
info->ram->duplicate);
+ monitor_printf(mon, "skipped: %" PRIu64 " pages\n",
+ info->ram->skipped);
monitor_printf(mon, "normal: %" PRIu64 " pages\n",
info->ram->normal);
monitor_printf(mon, "normal bytes: %" PRIu64 " kbytes\n",
@@ -631,11 +633,11 @@
c, TpmModel_lookup[ti->model]);
monitor_printf(mon, " \\ %s: type=%s",
- ti->id, TpmType_lookup[ti->type]);
+ ti->id, TpmTypeOptionsKind_lookup[ti->options->kind]);
- switch (ti->tpm_options->kind) {
- case TPM_TYPE_OPTIONS_KIND_TPM_PASSTHROUGH_OPTIONS:
- tpo = ti->tpm_options->tpm_passthrough_options;
+ switch (ti->options->kind) {
+ case TPM_TYPE_OPTIONS_KIND_PASSTHROUGH:
+ tpo = ti->options->passthrough;
monitor_printf(mon, "%s%s%s%s",
tpo->has_path ? ",path=" : "",
tpo->has_path ? tpo->path : "",
@@ -748,6 +750,14 @@
g_free(data);
}
+void hmp_query_cpu_max(Monitor *mon, const QDict *qdict)
+{
+ int cpu_max;
+
+ cpu_max = qmp_query_cpu_max(NULL);
+ monitor_printf(mon, "Maximum number of CPUs is %d\n", cpu_max);
+}
+
static void hmp_cont_cb(void *opaque, int err)
{
if (!err) {
diff --git a/hmp.h b/hmp.h
index 95fe76e..80e8b41 100644
--- a/hmp.h
+++ b/hmp.h
@@ -42,6 +42,7 @@
void hmp_system_reset(Monitor *mon, const QDict *qdict);
void hmp_system_powerdown(Monitor *mon, const QDict *qdict);
void hmp_cpu(Monitor *mon, const QDict *qdict);
+void hmp_query_cpu_max(Monitor *mon, const QDict *qdict);
void hmp_memsave(Monitor *mon, const QDict *qdict);
void hmp_pmemsave(Monitor *mon, const QDict *qdict);
void hmp_ringbuf_write(Monitor *mon, const QDict *qdict);
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index eb7eb31..d0b2ecb 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -98,6 +98,7 @@
common-obj-$(CONFIG_PL181) += pl181.o
common-obj-$(CONFIG_PL190) += pl190.o
common-obj-$(CONFIG_PL310) += arm_l2x0.o
+common-obj-$(CONFIG_PL330) += pl330.o
common-obj-$(CONFIG_VERSATILE_PCI) += versatile_pci.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
common-obj-$(CONFIG_CADENCE) += cadence_uart.o
@@ -118,6 +119,8 @@
common-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
common-obj-$(CONFIG_E1000_PCI) += e1000.o
common-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
+common-obj-$(CONFIG_VMXNET3_PCI) += vmxnet_tx_pkt.o vmxnet_rx_pkt.o
+common-obj-$(CONFIG_VMXNET3_PCI) += vmxnet3.o
common-obj-$(CONFIG_SMC91C111) += smc91c111.o
common-obj-$(CONFIG_LAN9118) += lan9118.o
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index cba7553..7b2b02d 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -14,7 +14,7 @@
#include "exec/memory.h"
#include "hw/irq.h"
-/* The CPU is also modeled as an interrupt controller. */
+/* The CPU is also modelled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu);
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index a37dbd7..edd5282 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -462,7 +462,7 @@
uint32_t irqctrl;
uint32_t page;
uint32_t page_off;
- DisplayState *ds;
+ QemuConsole *con;
uint8_t video_ram[128*64/8];
} musicpal_lcd_state;
@@ -483,7 +483,8 @@
(musicpal_lcd_state *s, int x, int y, type col) \
{ \
int dx, dy; \
- type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
+ DisplaySurface *surface = qemu_console_surface(s->con); \
+ type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
\
for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
for (dx = 0; dx < 3; dx++, pixel++) \
@@ -496,9 +497,10 @@
static void lcd_refresh(void *opaque)
{
musicpal_lcd_state *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
int x, y, col;
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
return;
#define LCD_REFRESH(depth, func) \
@@ -518,14 +520,14 @@
break;
LCD_REFRESH(8, rgb_to_pixel8)
LCD_REFRESH(16, rgb_to_pixel16)
- LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
+ LCD_REFRESH(32, (is_surface_bgr(surface) ?
rgb_to_pixel32bgr : rgb_to_pixel32))
default:
hw_error("unsupported colour depth %i\n",
- ds_get_bits_per_pixel(s->ds));
+ surface_bits_per_pixel(surface));
}
- dpy_gfx_update(s->ds, 0, 0, 128*3, 64*3);
+ dpy_gfx_update(s->con, 0, 0, 128*3, 64*3);
}
static void lcd_invalidate(void *opaque)
@@ -609,9 +611,9 @@
"musicpal-lcd", MP_LCD_SIZE);
sysbus_init_mmio(dev, &s->iomem);
- s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
- NULL, NULL, s);
- qemu_console_resize(s->ds, 128*3, 64*3);
+ s->con = graphic_console_init(lcd_refresh, lcd_invalidate,
+ NULL, NULL, s);
+ qemu_console_resize(s->con, 128*3, 64*3);
qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index c5bf9f9..6747c1c 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1290,7 +1290,6 @@
MemoryRegion *sysmem = get_system_memory();
struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
int sdram_size = binfo->ram_size;
- DisplayState *ds;
s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model);
@@ -1370,12 +1369,6 @@
n800_setup_nolo_tags(nolo_tags);
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
}
- /* FIXME: We shouldn't really be doing this here. The LCD controller
- will set the size once configured, so this just sets an initial
- size until the guest activates the display. */
- ds = get_displaystate();
- ds->surface = qemu_resize_displaysurface(ds, 800, 480);
- dpy_gfx_resize(ds);
}
static struct arm_boot_info n800_binfo = {
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 91bc74a..baeb585 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -205,7 +205,6 @@
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
int rom_size, rom_loaded = 0;
- DisplayState *ds = get_displaystate();
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
@@ -268,12 +267,6 @@
palmte_binfo.initrd_filename = initrd_filename;
arm_load_kernel(mpu->cpu, &palmte_binfo);
}
-
- /* FIXME: We shouldn't really be doing this here. The LCD controller
- will set the size once configured, so this just sets an initial
- size until the guest activates the display. */
- ds->surface = qemu_resize_displaysurface(ds, 320, 320);
- dpy_gfx_resize(ds);
}
static QEMUMachine palmte_machine = {
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 02922c3..2e1a5d0 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -147,19 +147,24 @@
typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
ram_addr_t ram_size,
const char *cpu_model,
- qemu_irq *pic, uint32_t *proc_id);
+ qemu_irq *pic);
struct VEDBoardInfo {
const hwaddr *motherboard_map;
hwaddr loader_start;
const hwaddr gic_cpu_if_addr;
+ uint32_t proc_id;
+ uint32_t num_voltage_sensors;
+ const uint32_t *voltages;
+ uint32_t num_clocks;
+ const uint32_t *clocks;
DBoardInitFn *init;
};
static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
ram_addr_t ram_size,
const char *cpu_model,
- qemu_irq *pic, uint32_t *proc_id)
+ qemu_irq *pic)
{
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
@@ -175,8 +180,6 @@
cpu_model = "cortex-a9";
}
- *proc_id = 0x0c000191;
-
for (n = 0; n < smp_cpus; n++) {
ARMCPU *cpu = cpu_arm_init(cpu_model);
if (!cpu) {
@@ -247,17 +250,41 @@
sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
}
+/* Voltage values for SYS_CFG_VOLT daughterboard registers;
+ * values are in microvolts.
+ */
+static const uint32_t a9_voltages[] = {
+ 1000000, /* VD10 : 1.0V : SoC internal logic voltage */
+ 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
+ 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
+ 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
+ 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
+ 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
+};
+
+/* Reset values for daughterboard oscillators (in Hz) */
+static const uint32_t a9_clocks[] = {
+ 45000000, /* AMBA AXI ACLK: 45MHz */
+ 23750000, /* daughterboard CLCD clock: 23.75MHz */
+ 66670000, /* Test chip reference clock: 66.67MHz */
+};
+
static const VEDBoardInfo a9_daughterboard = {
.motherboard_map = motherboard_legacy_map,
.loader_start = 0x60000000,
.gic_cpu_if_addr = 0x1e000100,
+ .proc_id = 0x0c000191,
+ .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
+ .voltages = a9_voltages,
+ .num_clocks = ARRAY_SIZE(a9_clocks),
+ .clocks = a9_clocks,
.init = a9_daughterboard_init,
};
static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
ram_addr_t ram_size,
const char *cpu_model,
- qemu_irq *pic, uint32_t *proc_id)
+ qemu_irq *pic)
{
int n;
MemoryRegion *sysmem = get_system_memory();
@@ -271,8 +298,6 @@
cpu_model = "cortex-a15";
}
- *proc_id = 0x14000237;
-
for (n = 0; n < smp_cpus; n++) {
ARMCPU *cpu;
qemu_irq *irqp;
@@ -340,10 +365,31 @@
/* 0x7ffd0000: PL354 static memory controller: not modelled */
}
+static const uint32_t a15_voltages[] = {
+ 900000, /* Vcore: 0.9V : CPU core voltage */
+};
+
+static const uint32_t a15_clocks[] = {
+ 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
+ 0, /* OSCCLK1: reserved */
+ 0, /* OSCCLK2: reserved */
+ 0, /* OSCCLK3: reserved */
+ 40000000, /* OSCCLK4: 40MHz : external AXI master clock */
+ 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
+ 50000000, /* OSCCLK6: 50MHz : static memory controller clock */
+ 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
+ 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
+};
+
static const VEDBoardInfo a15_daughterboard = {
.motherboard_map = motherboard_aseries_map,
.loader_start = 0x80000000,
.gic_cpu_if_addr = 0x2c002000,
+ .proc_id = 0x14000237,
+ .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
+ .voltages = a15_voltages,
+ .num_clocks = ARRAY_SIZE(a15_clocks),
+ .clocks = a15_clocks,
.init = a15_daughterboard_init,
};
@@ -352,7 +398,6 @@
{
DeviceState *dev, *sysctl, *pl041;
qemu_irq pic[64];
- uint32_t proc_id;
uint32_t sys_id;
DriveInfo *dinfo;
ram_addr_t vram_size, sram_size;
@@ -360,9 +405,9 @@
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
const hwaddr *map = daughterboard->motherboard_map;
+ int i;
- daughterboard->init(daughterboard, args->ram_size, args->cpu_model,
- pic, &proc_id);
+ daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
/* Motherboard peripherals: the wiring is the same but the
* addresses vary between the legacy and A-Series memory maps.
@@ -372,7 +417,21 @@
sysctl = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
- qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
+ qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
+ qdev_prop_set_uint32(sysctl, "len-db-voltage",
+ daughterboard->num_voltage_sensors);
+ for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
+ char *propname = g_strdup_printf("db-voltage[%d]", i);
+ qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
+ g_free(propname);
+ }
+ qdev_prop_set_uint32(sysctl, "len-db-clock",
+ daughterboard->num_clocks);
+ for (i = 0; i < daughterboard->num_clocks; i++) {
+ char *propname = g_strdup_printf("db-clock[%d]", i);
+ qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
+ g_free(propname);
+ }
qdev_init_nofail(sysctl);
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index f78c47e..6f36286 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -35,6 +35,10 @@
#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
+static const int dma_irqs[8] = {
+ 46, 47, 48, 49, 72, 73, 74, 75
+};
+
static struct arm_boot_info zynq_binfo = {};
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
@@ -196,6 +200,26 @@
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
+ dev = qdev_create(NULL, "pl330");
+ qdev_prop_set_uint8(dev, "num_chnls", 8);
+ qdev_prop_set_uint8(dev, "num_periph_req", 4);
+ qdev_prop_set_uint8(dev, "num_events", 16);
+
+ qdev_prop_set_uint8(dev, "data_width", 64);
+ qdev_prop_set_uint8(dev, "wr_cap", 8);
+ qdev_prop_set_uint8(dev, "wr_q_dep", 16);
+ qdev_prop_set_uint8(dev, "rd_cap", 8);
+ qdev_prop_set_uint8(dev, "rd_q_dep", 16);
+ qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
+
+ qdev_init_nofail(dev);
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, 0xF8003000);
+ sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
+ for (n = 0; n < 8; ++n) { /* event irqs */
+ sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
+ }
+
zynq_binfo.ram_size = ram_size;
zynq_binfo.kernel_filename = kernel_filename;
zynq_binfo.kernel_cmdline = kernel_cmdline;
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index a46f8d4..25fc6ea 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -9,6 +9,7 @@
#include "hw/hw.h"
#include "qemu/timer.h"
+#include "qemu/bitops.h"
#include "hw/sysbus.h"
#include "hw/primecell.h"
#include "sysemu/sysemu.h"
@@ -34,11 +35,17 @@
uint32_t sys_cfgctrl;
uint32_t sys_cfgstat;
uint32_t sys_clcd;
+ uint32_t mb_clock[6];
+ uint32_t *db_clock;
+ uint32_t db_num_vsensors;
+ uint32_t *db_voltage;
+ uint32_t db_num_clocks;
+ uint32_t *db_clock_reset;
} arm_sysctl_state;
static const VMStateDescription vmstate_arm_sysctl = {
.name = "realview_sysctl",
- .version_id = 3,
+ .version_id = 4,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(leds, arm_sysctl_state),
@@ -53,6 +60,9 @@
VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
+ VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
+ VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
+ 4, vmstate_info_uint32, uint32_t),
VMSTATE_END_OF_LIST()
}
};
@@ -76,6 +86,7 @@
static void arm_sysctl_reset(DeviceState *d)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
+ int i;
s->leds = 0;
s->lockval = 0;
@@ -83,6 +94,17 @@
s->cfgdata2 = 0;
s->flags = 0;
s->resetlevel = 0;
+ /* Motherboard oscillators (in Hz) */
+ s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
+ s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
+ s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
+ s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
+ s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
+ s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
+ /* Daughterboard oscillators: reset from property values */
+ for (i = 0; i < s->db_num_clocks; i++) {
+ s->db_clock[i] = s->db_clock_reset[i];
+ }
if (board_id(s) == BOARD_ID_VEXPRESS) {
/* On VExpress this register will RAZ/WI */
s->sys_clcd = 0;
@@ -191,6 +213,166 @@
}
}
+/* SYS_CFGCTRL functions */
+#define SYS_CFG_OSC 1
+#define SYS_CFG_VOLT 2
+#define SYS_CFG_AMP 3
+#define SYS_CFG_TEMP 4
+#define SYS_CFG_RESET 5
+#define SYS_CFG_SCC 6
+#define SYS_CFG_MUXFPGA 7
+#define SYS_CFG_SHUTDOWN 8
+#define SYS_CFG_REBOOT 9
+#define SYS_CFG_DVIMODE 11
+#define SYS_CFG_POWER 12
+#define SYS_CFG_ENERGY 13
+
+/* SYS_CFGCTRL site field values */
+#define SYS_CFG_SITE_MB 0
+#define SYS_CFG_SITE_DB1 1
+#define SYS_CFG_SITE_DB2 2
+
+/**
+ * vexpress_cfgctrl_read:
+ * @s: arm_sysctl_state pointer
+ * @dcc, @function, @site, @position, @device: split out values from
+ * SYS_CFGCTRL register
+ * @val: pointer to where to put the read data on success
+ *
+ * Handle a VExpress SYS_CFGCTRL register read. On success, return true and
+ * write the read value to *val. On failure, return false (and val may
+ * or may not be written to).
+ */
+static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
+ unsigned int function, unsigned int site,
+ unsigned int position, unsigned int device,
+ uint32_t *val)
+{
+ /* We don't support anything other than DCC 0, board stack position 0
+ * or sites other than motherboard/daughterboard:
+ */
+ if (dcc != 0 || position != 0 ||
+ (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
+ goto cfgctrl_unimp;
+ }
+
+ switch (function) {
+ case SYS_CFG_VOLT:
+ if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
+ *val = s->db_voltage[device];
+ return true;
+ }
+ if (site == SYS_CFG_SITE_MB && device == 0) {
+ /* There is only one motherboard voltage sensor:
+ * VIO : 3.3V : bus voltage between mother and daughterboard
+ */
+ *val = 3300000;
+ return true;
+ }
+ break;
+ case SYS_CFG_OSC:
+ if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
+ /* motherboard clock */
+ *val = s->mb_clock[device];
+ return true;
+ }
+ if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
+ /* daughterboard clock */
+ *val = s->db_clock[device];
+ return true;
+ }
+ break;
+ default:
+ break;
+ }
+
+cfgctrl_unimp:
+ qemu_log_mask(LOG_UNIMP,
+ "arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
+ "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
+ function, dcc, site, position, device);
+ return false;
+}
+
+/**
+ * vexpress_cfgctrl_write:
+ * @s: arm_sysctl_state pointer
+ * @dcc, @function, @site, @position, @device: split out values from
+ * SYS_CFGCTRL register
+ * @val: data to write
+ *
+ * Handle a VExpress SYS_CFGCTRL register write. On success, return true.
+ * On failure, return false.
+ */
+static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
+ unsigned int function, unsigned int site,
+ unsigned int position, unsigned int device,
+ uint32_t val)
+{
+ /* We don't support anything other than DCC 0, board stack position 0
+ * or sites other than motherboard/daughterboard:
+ */
+ if (dcc != 0 || position != 0 ||
+ (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
+ goto cfgctrl_unimp;
+ }
+
+ switch (function) {
+ case SYS_CFG_OSC:
+ if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
+ /* motherboard clock */
+ s->mb_clock[device] = val;
+ return true;
+ }
+ if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
+ /* daughterboard clock */
+ s->db_clock[device] = val;
+ return true;
+ }
+ break;
+ case SYS_CFG_MUXFPGA:
+ if (site == SYS_CFG_SITE_MB && device == 0) {
+ /* Select whether video output comes from motherboard
+ * or daughterboard: log and ignore as QEMU doesn't
+ * support this.
+ */
+ qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
+ "not supported, ignoring\n");
+ return true;
+ }
+ break;
+ case SYS_CFG_SHUTDOWN:
+ if (site == SYS_CFG_SITE_MB && device == 0) {
+ qemu_system_shutdown_request();
+ return true;
+ }
+ break;
+ case SYS_CFG_REBOOT:
+ if (site == SYS_CFG_SITE_MB && device == 0) {
+ qemu_system_reset_request();
+ return true;
+ }
+ break;
+ case SYS_CFG_DVIMODE:
+ if (site == SYS_CFG_SITE_MB && device == 0) {
+ /* Selecting DVI mode is meaningless for QEMU: we will
+ * always display the output correctly according to the
+ * pixel height/width programmed into the CLCD controller.
+ */
+ return true;
+ }
+ default:
+ break;
+ }
+
+cfgctrl_unimp:
+ qemu_log_mask(LOG_UNIMP,
+ "arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
+ "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
+ function, dcc, site, position, device);
+ return false;
+}
+
static void arm_sysctl_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
@@ -322,17 +504,33 @@
if (board_id(s) != BOARD_ID_VEXPRESS) {
goto bad_reg;
}
- s->sys_cfgctrl = val & ~(3 << 18);
- s->sys_cfgstat = 1; /* complete */
- switch (s->sys_cfgctrl) {
- case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
- qemu_system_shutdown_request();
- break;
- case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
- qemu_system_reset_request();
- break;
- default:
- s->sys_cfgstat |= 2; /* error */
+ /* Undefined bits [19:18] are RAZ/WI, and writing to
+ * the start bit just triggers the action; it always reads
+ * as zero.
+ */
+ s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
+ if (val & (1 << 31)) {
+ /* Start bit set -- actually do something */
+ unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
+ unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
+ unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
+ unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
+ unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
+ s->sys_cfgstat = 1; /* complete */
+ if (s->sys_cfgctrl & (1 << 30)) {
+ if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
+ device, s->sys_cfgdata)) {
+ s->sys_cfgstat |= 2; /* error */
+ }
+ } else {
+ uint32_t val;
+ if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
+ device, &val)) {
+ s->sys_cfgstat |= 2; /* error */
+ } else {
+ s->sys_cfgdata = val;
+ }
+ }
}
s->sys_cfgctrl &= ~(1 << 31);
return;
@@ -385,29 +583,50 @@
}
}
-static int arm_sysctl_init(SysBusDevice *dev)
+static void arm_sysctl_init(Object *obj)
{
- arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
+ DeviceState *dev = DEVICE(obj);
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
+ arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd);
memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
- sysbus_init_mmio(dev, &s->iomem);
- qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
- qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
- return 0;
+ sysbus_init_mmio(sd, &s->iomem);
+ qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
+ qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
+}
+
+static void arm_sysctl_realize(DeviceState *d, Error **errp)
+{
+ arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
+ s->db_clock = g_new0(uint32_t, s->db_num_clocks);
+}
+
+static void arm_sysctl_finalize(Object *obj)
+{
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
+ g_free(s->db_voltage);
+ g_free(s->db_clock);
+ g_free(s->db_clock_reset);
}
static Property arm_sysctl_properties[] = {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
+ /* Daughterboard power supply voltages (as reported via SYS_CFG) */
+ DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
+ db_voltage, qdev_prop_uint32, uint32_t),
+ /* Daughterboard clock reset values (as reported via SYS_CFG) */
+ DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks,
+ db_clock_reset, qdev_prop_uint32, uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
static void arm_sysctl_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = arm_sysctl_init;
+ dc->realize = arm_sysctl_realize;
dc->reset = arm_sysctl_reset;
dc->vmsd = &vmstate_arm_sysctl;
dc->props = arm_sysctl_properties;
@@ -417,6 +636,8 @@
.name = "realview_sysctl",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(arm_sysctl_state),
+ .instance_init = arm_sysctl_init,
+ .instance_finalize = arm_sysctl_finalize,
.class_init = arm_sysctl_class_init,
};
diff --git a/hw/blizzard.c b/hw/blizzard.c
index 805f4d5..020d3de 100644
--- a/hw/blizzard.c
+++ b/hw/blizzard.c
@@ -69,7 +69,7 @@
uint8_t effect;
uint8_t iformat;
uint8_t source;
- DisplayState *state;
+ QemuConsole *con;
blizzard_fn_t *line_fn_tab[2];
void *fb;
@@ -144,6 +144,7 @@
static void blizzard_window(BlizzardState *s)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *src, *dst;
int bypp[2];
int bypl[3];
@@ -162,7 +163,7 @@
s->my[1] = s->data.y + s->data.dy;
bypp[0] = s->bpp;
- bypp[1] = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
+ bypp[1] = surface_bytes_per_pixel(surface);
bypl[0] = bypp[0] * s->data.pitch;
bypl[1] = bypp[1] * s->x;
bypl[2] = bypp[0] * s->data.dx;
@@ -883,23 +884,25 @@
static void blizzard_update_display(void *opaque)
{
BlizzardState *s = (BlizzardState *) opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
int y, bypp, bypl, bwidth;
uint8_t *src, *dst;
if (!s->enable)
return;
- if (s->x != ds_get_width(s->state) || s->y != ds_get_height(s->state)) {
+ if (s->x != surface_width(surface) || s->y != surface_height(surface)) {
s->invalidate = 1;
- qemu_console_resize(s->state, s->x, s->y);
+ qemu_console_resize(s->con, s->x, s->y);
+ surface = qemu_console_surface(s->con);
}
if (s->invalidate) {
s->invalidate = 0;
if (s->blank) {
- bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
- memset(ds_get_data(s->state), 0, bypp * s->x * s->y);
+ bypp = surface_bytes_per_pixel(surface);
+ memset(surface_data(surface), 0, bypp * s->x * s->y);
return;
}
@@ -912,16 +915,16 @@
if (s->mx[1] <= s->mx[0])
return;
- bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
+ bypp = surface_bytes_per_pixel(surface);
bypl = bypp * s->x;
bwidth = bypp * (s->mx[1] - s->mx[0]);
y = s->my[0];
src = s->fb + bypl * y + bypp * s->mx[0];
- dst = ds_get_data(s->state) + bypl * y + bypp * s->mx[0];
+ dst = surface_data(surface) + bypl * y + bypp * s->mx[0];
for (; y < s->my[1]; y ++, src += bypl, dst += bypl)
memcpy(dst, src, bwidth);
- dpy_gfx_update(s->state, s->mx[0], s->my[0],
+ dpy_gfx_update(s->con, s->mx[0], s->my[0],
s->mx[1] - s->mx[0], y - s->my[0]);
s->mx[0] = s->x;
@@ -934,10 +937,12 @@
bool cswitch, Error **errp)
{
BlizzardState *s = (BlizzardState *) opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
blizzard_update_display(opaque);
- if (s && ds_get_data(s->state))
- ppm_save(filename, s->state->surface, errp);
+ if (s && surface_data(surface)) {
+ ppm_save(filename, surface, errp);
+ }
}
#define DEPTH 8
@@ -954,14 +959,16 @@
void *s1d13745_init(qemu_irq gpio_int)
{
BlizzardState *s = (BlizzardState *) g_malloc0(sizeof(*s));
+ DisplaySurface *surface;
s->fb = g_malloc(0x180000);
- s->state = graphic_console_init(blizzard_update_display,
- blizzard_invalidate_display,
- blizzard_screen_dump, NULL, s);
+ s->con = graphic_console_init(blizzard_update_display,
+ blizzard_invalidate_display,
+ blizzard_screen_dump, NULL, s);
+ surface = qemu_console_surface(s->con);
- switch (ds_get_bits_per_pixel(s->state)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
s->line_fn_tab[0] = s->line_fn_tab[1] =
g_malloc0(sizeof(blizzard_fn_t) * 0x10);
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 7babcb6..7a4d634 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -729,11 +729,12 @@
s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
s->cirrus_blt_width, s->cirrus_blt_height);
- if (notify)
- qemu_console_copy(s->vga.ds,
+ if (notify) {
+ qemu_console_copy(s->vga.con,
sx, sy, dx, dy,
s->cirrus_blt_width / depth,
s->cirrus_blt_height);
+ }
/* we don't have to notify the display that this portion has
changed since qemu_console_copy implies this */
@@ -2176,6 +2177,7 @@
static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
{
CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
int w, h, bpp, x1, x2, poffset;
unsigned int color0, color1;
const uint8_t *palette, *src;
@@ -2228,9 +2230,9 @@
color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
c6_to_8(palette[0xf * 3 + 1]),
c6_to_8(palette[0xf * 3 + 2]));
- bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
+ bpp = surface_bytes_per_pixel(surface);
d1 += x1 * bpp;
- switch(ds_get_bits_per_pixel(s->vga.ds)) {
+ switch (surface_bits_per_pixel(surface)) {
default:
break;
case 8:
@@ -2908,9 +2910,9 @@
vga_common_init(s);
cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
isa_address_space(dev), isa_address_space_io(dev));
- s->ds = graphic_console_init(s->update, s->invalidate,
- s->screen_dump, s->text_update,
- s);
+ s->con = graphic_console_init(s->update, s->invalidate,
+ s->screen_dump, s->text_update,
+ s);
rom_add_vga(VGABIOS_CIRRUS_FILENAME);
/* XXX ISA-LFB support */
/* FIXME not qdev yet */
@@ -2957,9 +2959,9 @@
vga_common_init(&s->vga);
cirrus_init_common(s, device_id, 1, pci_address_space(dev),
pci_address_space_io(dev));
- s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
- s->vga.screen_dump, s->vga.text_update,
- &s->vga);
+ s->vga.con = graphic_console_init(s->vga.update, s->vga.invalidate,
+ s->vga.screen_dump, s->vga.text_update,
+ &s->vga);
/* setup PCI */
diff --git a/hw/e1000.c b/hw/e1000.c
index 80b6ee3..3f18041 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1378,7 +1378,7 @@
k->init = pci_e1000_init;
k->exit = pci_e1000_uninit;
- k->romfile = "pxe-e1000.rom";
+ k->romfile = "efi-e1000.rom";
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = E1000_DEVID;
k->revision = 0x03;
diff --git a/hw/exynos4210_fimd.c b/hw/exynos4210_fimd.c
index 6b31ae3..bf316c6 100644
--- a/hw/exynos4210_fimd.c
+++ b/hw/exynos4210_fimd.c
@@ -296,7 +296,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
- DisplayState *console;
+ QemuConsole *console;
qemu_irq irq[3];
uint32_t vidcon[4]; /* Video main control registers 0-3 */
@@ -1221,16 +1221,18 @@
static void exynos4210_update_resolution(Exynos4210fimdState *s)
{
+ DisplaySurface *surface = qemu_console_surface(s->console);
+
/* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
FIMD_VIDTCON2_SIZE_MASK) + 1;
uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
FIMD_VIDTCON2_SIZE_MASK) + 1;
- if (s->ifb == NULL || ds_get_width(s->console) != width ||
- ds_get_height(s->console) != height) {
+ if (s->ifb == NULL || surface_width(surface) != width ||
+ surface_height(surface) != height) {
DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
- ds_get_width(s->console), ds_get_height(s->console), width, height);
+ surface_width(surface), surface_height(surface), width, height);
qemu_console_resize(s->console, width, height);
s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
@@ -1241,6 +1243,7 @@
static void exynos4210_fimd_update(void *opaque)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
+ DisplaySurface *surface = qemu_console_surface(s->console);
Exynos4210fimdWindow *w;
int i, line;
hwaddr fb_line_addr, inc_size;
@@ -1253,7 +1256,7 @@
const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
FIMD_VIDTCON2_SIZE_MASK) + 1;
- if (!s || !s->console || !ds_get_bits_per_pixel(s->console) ||
+ if (!s || !s->console || !surface_bits_per_pixel(surface) ||
!s->enabled) {
return;
}
@@ -1299,10 +1302,10 @@
uint8_t *d;
int bpp;
- bpp = ds_get_bits_per_pixel(s->console);
+ bpp = surface_bits_per_pixel(surface);
fimd_update_putpix_qemu(bpp);
bpp = (bpp + 1) >> 3;
- d = ds_get_data(s->console);
+ d = surface_data(surface);
for (line = first_line; line <= last_line; line++) {
fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
RGBA_SIZE, d + global_width * line * bpp);
diff --git a/hw/framebuffer.c b/hw/framebuffer.c
index d341aa0..7326a98 100644
--- a/hw/framebuffer.c
+++ b/hw/framebuffer.c
@@ -24,7 +24,7 @@
/* Render an image from a shared memory framebuffer. */
void framebuffer_update_display(
- DisplayState *ds,
+ DisplaySurface *ds,
MemoryRegion *address_space,
hwaddr base,
int cols, /* Width in pixels. */
@@ -73,7 +73,7 @@
return;
}
src = src_base;
- dest = ds_get_data(ds);
+ dest = surface_data(ds);
if (dest_col_pitch < 0)
dest -= dest_col_pitch * (cols - 1);
if (dest_row_pitch < 0) {
diff --git a/hw/framebuffer.h b/hw/framebuffer.h
index 11f53ed..6eae035 100644
--- a/hw/framebuffer.h
+++ b/hw/framebuffer.h
@@ -8,7 +8,7 @@
typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
- DisplayState *ds,
+ DisplaySurface *ds,
MemoryRegion *address_space,
hwaddr base,
int cols,
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 7b69815..f7014e9 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -39,7 +39,7 @@
uint32_t top_of_screen;
uint32_t width, height; /* in pixels */
/* display refresh support */
- DisplayState *ds;
+ QemuConsole *con;
int depth;
int blanked;
} G364State;
@@ -77,6 +77,7 @@
static void g364fb_draw_graphic8(G364State *s)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i, w;
uint8_t *vram;
uint8_t *data_display, *dd;
@@ -87,7 +88,7 @@
int xcursor, ycursor;
unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 8:
rgb_to_pixel = rgb_to_pixel8;
w = 1;
@@ -106,7 +107,7 @@
break;
default:
hw_error("g364: unknown host depth %d",
- ds_get_bits_per_pixel(s->ds));
+ surface_bits_per_pixel(surface));
return;
}
@@ -129,7 +130,7 @@
vram = s->vram + s->top_of_screen;
/* XXX: out of range in vram? */
- data_display = dd = ds_get_data(s->ds);
+ data_display = dd = surface_data(surface);
while (y < s->height) {
if (check_dirty(s, page)) {
if (y < ymin)
@@ -182,7 +183,7 @@
ymax = s->height - 1;
goto done;
}
- data_display = dd = data_display + ds_get_linesize(s->ds);
+ data_display = dd = data_display + surface_stride(surface);
xmin = 0;
x = 0;
}
@@ -197,7 +198,7 @@
reset_dirty(s, page_min, page_max);
page_min = (ram_addr_t)-1;
page_max = 0;
- dpy_gfx_update(s->ds, xmin, ymin,
+ dpy_gfx_update(s->con, xmin, ymin,
xmax - xmin + 1, ymax - ymin + 1);
xmin = s->width;
xmax = 0;
@@ -209,7 +210,7 @@
x = x % s->width;
y += dy;
vram += G364_PAGE_SIZE;
- data_display += dy * ds_get_linesize(s->ds);
+ data_display += dy * surface_stride(surface);
dd = data_display + x * w;
}
page += G364_PAGE_SIZE;
@@ -217,13 +218,14 @@
done:
if (page_min != (ram_addr_t)-1) {
- dpy_gfx_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
+ dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
reset_dirty(s, page_min, page_max);
}
}
static void g364fb_draw_blank(G364State *s)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i, w;
uint8_t *d;
@@ -232,28 +234,30 @@
return;
}
- w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
- d = ds_get_data(s->ds);
+ w = s->width * surface_bytes_per_pixel(surface);
+ d = surface_data(surface);
for (i = 0; i < s->height; i++) {
memset(d, 0, w);
- d += ds_get_linesize(s->ds);
+ d += surface_stride(surface);
}
- dpy_gfx_update(s->ds, 0, 0, s->width, s->height);
+ dpy_gfx_update(s->con, 0, 0, s->width, s->height);
s->blanked = 1;
}
static void g364fb_update_display(void *opaque)
{
G364State *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
qemu_flush_coalesced_mmio_buffer();
if (s->width == 0 || s->height == 0)
return;
- if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
- qemu_console_resize(s->ds, s->width, s->height);
+ if (s->width != surface_width(surface) ||
+ s->height != surface_height(surface)) {
+ qemu_console_resize(s->con, s->width, s->height);
}
if (s->ctla & CTLA_FORCE_BLANK) {
@@ -413,13 +417,14 @@
static void g364_invalidate_cursor_position(G364State *s)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int ymin, ymax, start, end;
/* invalidate only near the cursor */
ymin = s->cursor_position & 0xfff;
ymax = MIN(s->height, ymin + 64);
- start = ymin * ds_get_linesize(s->ds);
- end = (ymax + 1) * ds_get_linesize(s->ds);
+ start = ymin * surface_stride(surface);
+ end = (ymax + 1) * surface_stride(surface);
memory_region_set_dirty(&s->mem_vram, start, end - start);
}
@@ -545,9 +550,9 @@
{
s->vram = g_malloc0(s->vram_size);
- s->ds = graphic_console_init(g364fb_update_display,
- g364fb_invalidate_display,
- g364fb_screen_dump, NULL, s);
+ s->con = graphic_console_init(g364fb_update_display,
+ g364fb_invalidate_display,
+ g364fb_screen_dump, NULL, s);
memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
memory_region_init_ram_ptr(&s->mem_vram, "vram",
diff --git a/hw/hw.h b/hw/hw.h
index 1553e54..1fb9afa 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -52,16 +52,22 @@
#if TARGET_LONG_BITS == 64
#define VMSTATE_UINTTL_V(_f, _s, _v) \
VMSTATE_UINT64_V(_f, _s, _v)
+#define VMSTATE_UINTTL_EQUAL_V(_f, _s, _v) \
+ VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
#else
#define VMSTATE_UINTTL_V(_f, _s, _v) \
VMSTATE_UINT32_V(_f, _s, _v)
+#define VMSTATE_UINTTL_EQUAL_V(_f, _s, _v) \
+ VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
#endif
#define VMSTATE_UINTTL(_f, _s) \
VMSTATE_UINTTL_V(_f, _s, 0)
+#define VMSTATE_UINTTL_EQUAL(_f, _s) \
+ VMSTATE_UINTTL_EQUAL_V(_f, _s, 0)
#define VMSTATE_UINTTL_ARRAY(_f, _s, _n) \
VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0)
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index a418a7d..05528c7 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -36,7 +36,7 @@
SysBusDevice busdev;
MemoryRegion iomem;
uint8_t segments;
- DisplayState *ds;
+ QemuConsole *con;
screen_state_t state;
} LedState;
@@ -75,13 +75,15 @@
/***********************************************************/
/* jazz_led display */
-static void draw_horizontal_line(DisplayState *ds, int posy, int posx1, int posx2, uint32_t color)
+static void draw_horizontal_line(DisplaySurface *ds,
+ int posy, int posx1, int posx2,
+ uint32_t color)
{
uint8_t *d;
int x, bpp;
- bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
- d = ds_get_data(ds) + ds_get_linesize(ds) * posy + bpp * posx1;
+ bpp = (surface_bits_per_pixel(ds) + 7) >> 3;
+ d = surface_data(ds) + surface_stride(ds) * posy + bpp * posx1;
switch(bpp) {
case 1:
for (x = posx1; x <= posx2; x++) {
@@ -104,30 +106,32 @@
}
}
-static void draw_vertical_line(DisplayState *ds, int posx, int posy1, int posy2, uint32_t color)
+static void draw_vertical_line(DisplaySurface *ds,
+ int posx, int posy1, int posy2,
+ uint32_t color)
{
uint8_t *d;
int y, bpp;
- bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
- d = ds_get_data(ds) + ds_get_linesize(ds) * posy1 + bpp * posx;
+ bpp = (surface_bits_per_pixel(ds) + 7) >> 3;
+ d = surface_data(ds) + surface_stride(ds) * posy1 + bpp * posx;
switch(bpp) {
case 1:
for (y = posy1; y <= posy2; y++) {
*((uint8_t *)d) = color;
- d += ds_get_linesize(ds);
+ d += surface_stride(ds);
}
break;
case 2:
for (y = posy1; y <= posy2; y++) {
*((uint16_t *)d) = color;
- d += ds_get_linesize(ds);
+ d += surface_stride(ds);
}
break;
case 4:
for (y = posy1; y <= posy2; y++) {
*((uint32_t *)d) = color;
- d += ds_get_linesize(ds);
+ d += surface_stride(ds);
}
break;
}
@@ -136,24 +140,24 @@
static void jazz_led_update_display(void *opaque)
{
LedState *s = opaque;
- DisplayState *ds = s->ds;
+ DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *d1;
uint32_t color_segment, color_led;
int y, bpp;
if (s->state & REDRAW_BACKGROUND) {
/* clear screen */
- bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
- d1 = ds_get_data(ds);
- for (y = 0; y < ds_get_height(ds); y++) {
- memset(d1, 0x00, ds_get_width(ds) * bpp);
- d1 += ds_get_linesize(ds);
+ bpp = (surface_bits_per_pixel(surface) + 7) >> 3;
+ d1 = surface_data(surface);
+ for (y = 0; y < surface_height(surface); y++) {
+ memset(d1, 0x00, surface_width(surface) * bpp);
+ d1 += surface_stride(surface);
}
}
if (s->state & REDRAW_SEGMENTS) {
/* set colors according to bpp */
- switch (ds_get_bits_per_pixel(ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 8:
color_segment = rgb_to_pixel8(0xaa, 0xaa, 0xaa);
color_led = rgb_to_pixel8(0x00, 0xff, 0x00);
@@ -178,26 +182,34 @@
}
/* display segments */
- draw_horizontal_line(ds, 40, 10, 40, (s->segments & 0x02) ? color_segment : 0);
- draw_vertical_line(ds, 10, 10, 40, (s->segments & 0x04) ? color_segment : 0);
- draw_vertical_line(ds, 10, 40, 70, (s->segments & 0x08) ? color_segment : 0);
- draw_horizontal_line(ds, 70, 10, 40, (s->segments & 0x10) ? color_segment : 0);
- draw_vertical_line(ds, 40, 40, 70, (s->segments & 0x20) ? color_segment : 0);
- draw_vertical_line(ds, 40, 10, 40, (s->segments & 0x40) ? color_segment : 0);
- draw_horizontal_line(ds, 10, 10, 40, (s->segments & 0x80) ? color_segment : 0);
+ draw_horizontal_line(surface, 40, 10, 40,
+ (s->segments & 0x02) ? color_segment : 0);
+ draw_vertical_line(surface, 10, 10, 40,
+ (s->segments & 0x04) ? color_segment : 0);
+ draw_vertical_line(surface, 10, 40, 70,
+ (s->segments & 0x08) ? color_segment : 0);
+ draw_horizontal_line(surface, 70, 10, 40,
+ (s->segments & 0x10) ? color_segment : 0);
+ draw_vertical_line(surface, 40, 40, 70,
+ (s->segments & 0x20) ? color_segment : 0);
+ draw_vertical_line(surface, 40, 10, 40,
+ (s->segments & 0x40) ? color_segment : 0);
+ draw_horizontal_line(surface, 10, 10, 40,
+ (s->segments & 0x80) ? color_segment : 0);
/* display led */
if (!(s->segments & 0x01))
color_led = 0; /* black */
- draw_horizontal_line(ds, 68, 50, 50, color_led);
- draw_horizontal_line(ds, 69, 49, 51, color_led);
- draw_horizontal_line(ds, 70, 48, 52, color_led);
- draw_horizontal_line(ds, 71, 49, 51, color_led);
- draw_horizontal_line(ds, 72, 50, 50, color_led);
+ draw_horizontal_line(surface, 68, 50, 50, color_led);
+ draw_horizontal_line(surface, 69, 49, 51, color_led);
+ draw_horizontal_line(surface, 70, 48, 52, color_led);
+ draw_horizontal_line(surface, 71, 49, 51, color_led);
+ draw_horizontal_line(surface, 72, 50, 50, color_led);
}
s->state = REDRAW_NONE;
- dpy_gfx_update(ds, 0, 0, ds_get_width(ds), ds_get_height(ds));
+ dpy_gfx_update(s->con, 0, 0,
+ surface_width(surface), surface_height(surface));
}
static void jazz_led_invalidate_display(void *opaque)
@@ -211,15 +223,15 @@
LedState *s = opaque;
char buf[2];
- dpy_text_cursor(s->ds, -1, -1);
- qemu_console_resize(s->ds, 2, 1);
+ dpy_text_cursor(s->con, -1, -1);
+ qemu_console_resize(s->con, 2, 1);
/* TODO: draw the segments */
snprintf(buf, 2, "%02hhx\n", s->segments);
console_write_ch(chardata++, 0x00200100 | buf[0]);
console_write_ch(chardata++, 0x00200100 | buf[1]);
- dpy_text_update(s->ds, 0, 0, 2, 1);
+ dpy_text_update(s->con, 0, 0, 2, 1);
}
static int jazz_led_post_load(void *opaque, int version_id)
@@ -249,10 +261,10 @@
memory_region_init_io(&s->iomem, &led_ops, s, "led", 1);
sysbus_init_mmio(dev, &s->iomem);
- s->ds = graphic_console_init(jazz_led_update_display,
- jazz_led_invalidate_display,
- NULL,
- jazz_led_text_update, s);
+ s->con = graphic_console_init(jazz_led_update_display,
+ jazz_led_invalidate_display,
+ NULL,
+ jazz_led_text_update, s);
return 0;
}
@@ -263,7 +275,7 @@
s->segments = 0;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
- qemu_console_resize(s->ds, 60, 80);
+ qemu_console_resize(s->con, 60, 80);
}
static void jazz_led_class_init(ObjectClass *klass, void *data)
diff --git a/hw/lm32/Makefile.objs b/hw/lm32/Makefile.objs
index 4592fe5..68ca90a 100644
--- a/hw/lm32/Makefile.objs
+++ b/hw/lm32/Makefile.objs
@@ -11,7 +11,7 @@
obj-y += milkymist-pfpu.o
obj-y += milkymist-softusb.o
obj-y += milkymist-sysctl.o
-obj-$(CONFIG_OPENGL) += milkymist-tmu2.o
+obj-$(CONFIG_GLX) += milkymist-tmu2.o
obj-y += milkymist-uart.o
obj-y += milkymist-vgafb.o
obj-y += framebuffer.o
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
index 02f6f89..32bc37a 100644
--- a/hw/lm32_uart.c
+++ b/hw/lm32_uart.c
@@ -137,6 +137,7 @@
r = s->regs[R_RXTX];
s->regs[R_LSR] &= ~LSR_DR;
uart_update_irq(s);
+ qemu_chr_accept_input(s->chr);
break;
case R_IIR:
case R_LSR:
diff --git a/hw/milkymist-hw.h b/hw/milkymist-hw.h
index ced1c5f..c047a70 100644
--- a/hw/milkymist-hw.h
+++ b/hw/milkymist-hw.h
@@ -87,7 +87,7 @@
return dev;
}
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GLX
#include <X11/Xlib.h>
#include <GL/glx.h>
static const int glx_fbconfig_attr[] = {
@@ -101,7 +101,7 @@
static inline DeviceState *milkymist_tmu2_create(hwaddr base,
qemu_irq irq)
{
-#ifdef CONFIG_OPENGL
+#ifdef CONFIG_GLX
DeviceState *dev;
Display *d;
GLXFBConfig *configs;
diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c
index ac6f537..f3bdf69 100644
--- a/hw/milkymist-uart.c
+++ b/hw/milkymist-uart.c
@@ -132,6 +132,7 @@
case R_STAT:
/* write one to clear bits */
s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
+ qemu_chr_accept_input(s->chr);
break;
default:
diff --git a/hw/milkymist-vgafb.c b/hw/milkymist-vgafb.c
index 85ebb85..98762ec 100644
--- a/hw/milkymist-vgafb.c
+++ b/hw/milkymist-vgafb.c
@@ -66,7 +66,7 @@
struct MilkymistVgafbState {
SysBusDevice busdev;
MemoryRegion regs_region;
- DisplayState *ds;
+ QemuConsole *con;
int invalidate;
uint32_t fb_offset;
@@ -84,6 +84,7 @@
static void vgafb_update_display(void *opaque)
{
MilkymistVgafbState *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
int first = 0;
int last = 0;
drawfn fn;
@@ -94,7 +95,7 @@
int dest_width = s->regs[R_HRES];
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 8:
@@ -121,7 +122,7 @@
break;
}
- framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
+ framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
s->regs[R_BASEADDRESS] + s->fb_offset,
s->regs[R_HRES],
s->regs[R_VRES],
@@ -134,7 +135,7 @@
&first, &last);
if (first >= 0) {
- dpy_gfx_update(s->ds, 0, first, s->regs[R_HRES], last - first + 1);
+ dpy_gfx_update(s->con, 0, first, s->regs[R_HRES], last - first + 1);
}
s->invalidate = 0;
}
@@ -151,7 +152,7 @@
return;
}
- qemu_console_resize(s->ds, s->regs[R_HRES], s->regs[R_VRES]);
+ qemu_console_resize(s->con, s->regs[R_HRES], s->regs[R_VRES]);
s->invalidate = 1;
}
@@ -277,9 +278,9 @@
"milkymist-vgafb", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
- s->ds = graphic_console_init(vgafb_update_display,
- vgafb_invalidate_display,
- NULL, NULL, s);
+ s->con = graphic_console_init(vgafb_update_display,
+ vgafb_invalidate_display,
+ NULL, NULL, s);
return 0;
}
diff --git a/hw/moxie/Makefile.objs b/hw/moxie/Makefile.objs
new file mode 100644
index 0000000..a5f1742
--- /dev/null
+++ b/hw/moxie/Makefile.objs
@@ -0,0 +1,5 @@
+# moxie boards
+obj-y = serial.o mc146818rtc.o vga.o
+
+obj-y := $(addprefix ../,$(obj-y))
+obj-y += moxiesim.o
diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c
new file mode 100644
index 0000000..e1e88a9
--- /dev/null
+++ b/hw/moxie/moxiesim.c
@@ -0,0 +1,174 @@
+/*
+ * QEMU/moxiesim emulation
+ *
+ * Emulates a very simple machine model similiar to the one use by the
+ * GDB moxie simulator.
+ *
+ * Copyright (c) 2008, 2009, 2010, 2013 Anthony Green
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/pc.h"
+#include "hw/isa.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/serial.h"
+#include "exec/address-spaces.h"
+
+#define PHYS_MEM_BASE 0x80000000
+
+typedef struct {
+ uint64_t ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+} LoaderParams;
+
+static void load_kernel(MoxieCPU *cpu, LoaderParams *loader_params)
+{
+ uint64_t entry, kernel_low, kernel_high;
+ long kernel_size;
+ long initrd_size;
+ ram_addr_t initrd_offset;
+
+ kernel_size = load_elf(loader_params->kernel_filename, NULL, NULL,
+ &entry, &kernel_low, &kernel_high, 1,
+ ELF_MACHINE, 0);
+
+ if (!kernel_size) {
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ loader_params->kernel_filename);
+ exit(1);
+ }
+
+ /* load initrd */
+ initrd_size = 0;
+ initrd_offset = 0;
+ if (loader_params->initrd_filename) {
+ initrd_size = get_image_size(loader_params->initrd_filename);
+ if (initrd_size > 0) {
+ initrd_offset = (kernel_high + ~TARGET_PAGE_MASK)
+ & TARGET_PAGE_MASK;
+ if (initrd_offset + initrd_size > loader_params->ram_size) {
+ fprintf(stderr,
+ "qemu: memory too small for initial ram disk '%s'\n",
+ loader_params->initrd_filename);
+ exit(1);
+ }
+ initrd_size = load_image_targphys(loader_params->initrd_filename,
+ initrd_offset,
+ ram_size);
+ }
+ if (initrd_size == (target_ulong)-1) {
+ fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
+ loader_params->initrd_filename);
+ exit(1);
+ }
+ }
+}
+
+static void main_cpu_reset(void *opaque)
+{
+ MoxieCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+}
+
+static inline DeviceState *
+moxie_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr)
+{
+ DeviceState *dev;
+
+ dev = qdev_create(NULL, "moxie,intc");
+ qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
+ return dev;
+}
+
+static void moxiesim_init(QEMUMachineInitArgs *args)
+{
+ MoxieCPU *cpu = NULL;
+ ram_addr_t ram_size = args->ram_size;
+ const char *cpu_model = args->cpu_model;
+ const char *kernel_filename = args->kernel_filename;
+ const char *kernel_cmdline = args->kernel_cmdline;
+ const char *initrd_filename = args->initrd_filename;
+ CPUMoxieState *env;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *rom = g_new(MemoryRegion, 1);
+ hwaddr ram_base = 0x200000;
+ LoaderParams loader_params;
+
+ /* Init CPUs. */
+ if (cpu_model == NULL) {
+ cpu_model = "MoxieLite-moxie-cpu";
+ }
+ cpu = cpu_moxie_init(cpu_model);
+ if (!cpu) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ env = &cpu->env;
+
+ qemu_register_reset(main_cpu_reset, cpu);
+
+ /* Allocate RAM. */
+ memory_region_init_ram(ram, "moxiesim.ram", ram_size);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(address_space_mem, ram_base, ram);
+
+ memory_region_init_ram(rom, "moxie.rom", 128*0x1000);
+ vmstate_register_ram_global(rom);
+ memory_region_add_subregion(get_system_memory(), 0x1000, rom);
+
+ if (kernel_filename) {
+ loader_params.ram_size = ram_size;
+ loader_params.kernel_filename = kernel_filename;
+ loader_params.kernel_cmdline = kernel_cmdline;
+ loader_params.initrd_filename = initrd_filename;
+ load_kernel(cpu, &loader_params);
+ }
+
+ /* A single 16450 sits at offset 0x3f8. */
+ if (serial_hds[0]) {
+ serial_mm_init(address_space_mem, 0x3f8, 0, env->irq[4],
+ 8000000/16, serial_hds[0], DEVICE_LITTLE_ENDIAN);
+ }
+}
+
+static QEMUMachine moxiesim_machine = {
+ .name = "moxiesim",
+ .desc = "Moxie simulator platform",
+ .init = moxiesim_init,
+ .is_default = 1,
+};
+
+static void moxie_machine_init(void)
+{
+ qemu_register_machine(&moxiesim_machine);
+}
+
+machine_init(moxie_machine_init)
diff --git a/hw/ne2000.c b/hw/ne2000.c
index 7dadc1c..7f45831 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -766,7 +766,7 @@
k->init = pci_ne2000_init;
k->exit = pci_ne2000_exit;
- k->romfile = "pxe-ne2k_pci.rom",
+ k->romfile = "efi-ne2k_pci.rom",
k->vendor_id = PCI_VENDOR_ID_REALTEK;
k->device_id = PCI_DEVICE_ID_REALTEK_8029;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index c426f3a..4f5b094 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -26,7 +26,7 @@
MemoryRegion *sysmem;
MemoryRegion iomem;
qemu_irq irq;
- DisplayState *state;
+ QemuConsole *con;
int plm;
int tft;
@@ -113,14 +113,16 @@
static void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
+ DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
hwaddr frame_base;
- if (!omap_lcd || omap_lcd->plm == 1 ||
- !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
+ if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
+ !surface_bits_per_pixel(surface)) {
return;
+ }
frame_offset = 0;
if (omap_lcd->plm != 2) {
@@ -139,25 +141,25 @@
/* Colour depth */
switch ((omap_lcd->palette[0] >> 12) & 7) {
case 1:
- draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)];
+ draw_line = draw_line_table2[surface_bits_per_pixel(surface)];
bpp = 2;
break;
case 2:
- draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)];
+ draw_line = draw_line_table4[surface_bits_per_pixel(surface)];
bpp = 4;
break;
case 3:
- draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)];
+ draw_line = draw_line_table8[surface_bits_per_pixel(surface)];
bpp = 8;
break;
case 4 ... 7:
if (!omap_lcd->tft)
- draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)];
+ draw_line = draw_line_table12[surface_bits_per_pixel(surface)];
else
- draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)];
+ draw_line = draw_line_table16[surface_bits_per_pixel(surface)];
bpp = 16;
break;
@@ -168,10 +170,11 @@
/* Resolution */
width = omap_lcd->width;
- if (width != ds_get_width(omap_lcd->state) ||
- omap_lcd->height != ds_get_height(omap_lcd->state)) {
- qemu_console_resize(omap_lcd->state,
+ if (width != surface_width(surface) ||
+ omap_lcd->height != surface_height(surface)) {
+ qemu_console_resize(omap_lcd->con,
omap_lcd->width, omap_lcd->height);
+ surface = qemu_console_surface(omap_lcd->con);
omap_lcd->invalidate = 1;
}
@@ -196,8 +199,9 @@
if (omap_lcd->dma->dual)
omap_lcd->dma->current_frame ^= 1;
- if (!ds_get_bits_per_pixel(omap_lcd->state))
+ if (!surface_bits_per_pixel(surface)) {
return;
+ }
first = 0;
height = omap_lcd->height;
@@ -210,15 +214,15 @@
}
step = width * bpp >> 3;
- linesize = ds_get_linesize(omap_lcd->state);
- framebuffer_update_display(omap_lcd->state, omap_lcd->sysmem,
+ linesize = surface_stride(surface);
+ framebuffer_update_display(surface, omap_lcd->sysmem,
frame_base, width, height,
step, linesize, 0,
omap_lcd->invalidate,
draw_line, omap_lcd->palette,
&first, &last);
if (first >= 0) {
- dpy_gfx_update(omap_lcd->state, 0, first, width, last - first + 1);
+ dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1);
}
omap_lcd->invalidate = 0;
}
@@ -298,12 +302,13 @@
Error **errp)
{
struct omap_lcd_panel_s *omap_lcd = opaque;
+ DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
omap_update_display(opaque);
- if (omap_lcd && ds_get_data(omap_lcd->state))
- omap_ppm_save(filename, ds_get_data(omap_lcd->state),
+ if (omap_lcd && surface_data(surface))
+ omap_ppm_save(filename, surface_data(surface),
omap_lcd->width, omap_lcd->height,
- ds_get_linesize(omap_lcd->state), errp);
+ surface_stride(surface), errp);
}
static void omap_invalidate_display(void *opaque) {
@@ -480,9 +485,9 @@
memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
- s->state = graphic_console_init(omap_update_display,
- omap_invalidate_display,
- omap_screen_dump, NULL, s);
+ s->con = graphic_console_init(omap_update_display,
+ omap_invalidate_display,
+ omap_screen_dump, NULL, s);
return s;
}
diff --git a/hw/pc.h b/hw/pc.h
index dbbd8cd..8e1dd4c 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -212,7 +212,7 @@
.driver = "ide-drive",\
.property = "discard_granularity",\
.value = stringify(0),\
- },{\
+ },{\
.driver = "virtio-blk-pci",\
.property = "discard_granularity",\
.value = stringify(0),\
@@ -221,6 +221,26 @@
.property = "vectors",\
/* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
.value = stringify(0xFFFFFFFF),\
- }
+ },{\
+ .driver = "e1000",\
+ .property = "romfile",\
+ .value = "pxe-e1000.rom",\
+ },{\
+ .driver = "ne2k_pci",\
+ .property = "romfile",\
+ .value = "pxe-ne2k_pci.rom",\
+ },{\
+ .driver = "pcnet",\
+ .property = "romfile",\
+ .value = "pxe-pcnet.rom",\
+ },{\
+ .driver = "rtl8139",\
+ .property = "romfile",\
+ .value = "pxe-rtl8139.rom",\
+ },{\
+ .driver = "virtio-net-pci",\
+ .property = "romfile",\
+ .value = "pxe-virtio.rom",\
+ }
#endif
diff --git a/hw/pci/pci.h b/hw/pci/pci.h
index 774369c..9ea67a3 100644
--- a/hw/pci/pci.h
+++ b/hw/pci/pci.h
@@ -60,6 +60,7 @@
#define PCI_DEVICE_ID_VMWARE_NET 0x0720
#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
+#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
/* Intel (0x8086) */
#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
index daca1c1..12254b1 100644
--- a/hw/pci/pci_host.c
+++ b/hw/pci/pci_host.c
@@ -38,7 +38,7 @@
* bit 0 - 7: offset in configuration space of a given pci device
*/
-/* the helper functio to get a PCIDeice* for a given pci address */
+/* the helper function to get a PCIDevice* for a given pci address */
static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
{
uint8_t bus_num = addr >> 16;
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 55f80ca..61af57e 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -351,7 +351,7 @@
k->init = pci_pcnet_init;
k->exit = pci_pcnet_uninit;
- k->romfile = "pxe-pcnet.rom",
+ k->romfile = "efi-pcnet.rom",
k->vendor_id = PCI_VENDOR_ID_AMD;
k->device_id = PCI_DEVICE_ID_AMD_LANCE;
k->revision = 0x10;
diff --git a/hw/pl110.c b/hw/pl110.c
index 924642d..fbef675 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -42,7 +42,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
- DisplayState *ds;
+ QemuConsole *con;
int version;
uint32_t timing[4];
@@ -129,6 +129,7 @@
static void pl110_update_display(void *opaque)
{
pl110_state *s = (pl110_state *)opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
drawfn* fntable;
drawfn fn;
int dest_width;
@@ -140,7 +141,7 @@
if (!pl110_enabled(s))
return;
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 8:
@@ -231,14 +232,14 @@
}
dest_width *= s->cols;
first = 0;
- framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
+ framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
s->upbase, s->cols, s->rows,
src_width, dest_width, 0,
s->invalidate,
fn, s->palette,
&first, &last);
if (first >= 0) {
- dpy_gfx_update(s->ds, 0, first, s->cols, last - first + 1);
+ dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
}
s->invalidate = 0;
}
@@ -248,12 +249,13 @@
pl110_state *s = (pl110_state *)opaque;
s->invalidate = 1;
if (pl110_enabled(s)) {
- qemu_console_resize(s->ds, s->cols, s->rows);
+ qemu_console_resize(s->con, s->cols, s->rows);
}
}
static void pl110_update_palette(pl110_state *s, int n)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i;
uint32_t raw;
unsigned int r, g, b;
@@ -268,7 +270,7 @@
b = (raw & 0x1f) << 3;
/* The I bit is ignored. */
raw >>= 6;
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 8:
s->palette[n] = rgb_to_pixel8(r, g, b);
break;
@@ -291,7 +293,7 @@
{
if (width != s->cols || height != s->rows) {
if (pl110_enabled(s)) {
- qemu_console_resize(s->ds, width, height);
+ qemu_console_resize(s->con, width, height);
}
}
s->cols = width;
@@ -409,7 +411,7 @@
s->cr = val;
s->bpp = (val >> 1) & 7;
if (pl110_enabled(s)) {
- qemu_console_resize(s->ds, s->cols, s->rows);
+ qemu_console_resize(s->con, s->cols, s->rows);
}
break;
case 10: /* LCDICR */
@@ -450,9 +452,9 @@
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
- s->ds = graphic_console_init(pl110_update_display,
- pl110_invalidate_display,
- NULL, NULL, s);
+ s->con = graphic_console_init(pl110_update_display,
+ pl110_invalidate_display,
+ NULL, NULL, s);
return 0;
}
diff --git a/hw/pl330.c b/hw/pl330.c
new file mode 100644
index 0000000..1a04773
--- /dev/null
+++ b/hw/pl330.c
@@ -0,0 +1,1654 @@
+/*
+ * ARM PrimeCell PL330 DMA Controller
+ *
+ * Copyright (c) 2009 Samsung Electronics.
+ * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 or later.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysbus.h"
+#include "qemu/timer.h"
+#include "sysemu/dma.h"
+
+#ifndef PL330_ERR_DEBUG
+#define PL330_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do {\
+ if (PL330_ERR_DEBUG >= lvl) {\
+ fprintf(stderr, "PL330: %s:" fmt, __func__, ## args);\
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+#define PL330_PERIPH_NUM 32
+#define PL330_MAX_BURST_LEN 128
+#define PL330_INSN_MAXSIZE 6
+
+#define PL330_FIFO_OK 0
+#define PL330_FIFO_STALL 1
+#define PL330_FIFO_ERR (-1)
+
+#define PL330_FAULT_UNDEF_INSTR (1 << 0)
+#define PL330_FAULT_OPERAND_INVALID (1 << 1)
+#define PL330_FAULT_DMAGO_ERR (1 << 4)
+#define PL330_FAULT_EVENT_ERR (1 << 5)
+#define PL330_FAULT_CH_PERIPH_ERR (1 << 6)
+#define PL330_FAULT_CH_RDWR_ERR (1 << 7)
+#define PL330_FAULT_ST_DATA_UNAVAILABLE (1 << 12)
+#define PL330_FAULT_FIFOEMPTY_ERR (1 << 13)
+#define PL330_FAULT_INSTR_FETCH_ERR (1 << 16)
+#define PL330_FAULT_DATA_WRITE_ERR (1 << 17)
+#define PL330_FAULT_DATA_READ_ERR (1 << 18)
+#define PL330_FAULT_DBG_INSTR (1 << 30)
+#define PL330_FAULT_LOCKUP_ERR (1 << 31)
+
+#define PL330_UNTAGGED 0xff
+
+#define PL330_SINGLE 0x0
+#define PL330_BURST 0x1
+
+#define PL330_WATCHDOG_LIMIT 1024
+
+/* IOMEM mapped registers */
+#define PL330_REG_DSR 0x000
+#define PL330_REG_DPC 0x004
+#define PL330_REG_INTEN 0x020
+#define PL330_REG_INT_EVENT_RIS 0x024
+#define PL330_REG_INTMIS 0x028
+#define PL330_REG_INTCLR 0x02C
+#define PL330_REG_FSRD 0x030
+#define PL330_REG_FSRC 0x034
+#define PL330_REG_FTRD 0x038
+#define PL330_REG_FTR_BASE 0x040
+#define PL330_REG_CSR_BASE 0x100
+#define PL330_REG_CPC_BASE 0x104
+#define PL330_REG_CHANCTRL 0x400
+#define PL330_REG_DBGSTATUS 0xD00
+#define PL330_REG_DBGCMD 0xD04
+#define PL330_REG_DBGINST0 0xD08
+#define PL330_REG_DBGINST1 0xD0C
+#define PL330_REG_CR0_BASE 0xE00
+#define PL330_REG_PERIPH_ID 0xFE0
+
+#define PL330_IOMEM_SIZE 0x1000
+
+#define CFG_BOOT_ADDR 2
+#define CFG_INS 3
+#define CFG_PNS 4
+#define CFG_CRD 5
+
+static const uint32_t pl330_id[] = {
+ 0x30, 0x13, 0x24, 0x00, 0x0D, 0xF0, 0x05, 0xB1
+};
+
+/* DMA channel states as they are described in PL330 Technical Reference Manual
+ * Most of them will not be used in emulation.
+ */
+typedef enum {
+ pl330_chan_stopped = 0,
+ pl330_chan_executing = 1,
+ pl330_chan_cache_miss = 2,
+ pl330_chan_updating_pc = 3,
+ pl330_chan_waiting_event = 4,
+ pl330_chan_at_barrier = 5,
+ pl330_chan_queue_busy = 6,
+ pl330_chan_waiting_periph = 7,
+ pl330_chan_killing = 8,
+ pl330_chan_completing = 9,
+ pl330_chan_fault_completing = 14,
+ pl330_chan_fault = 15,
+} PL330ChanState;
+
+typedef struct PL330State PL330State;
+
+typedef struct PL330Chan {
+ uint32_t src;
+ uint32_t dst;
+ uint32_t pc;
+ uint32_t control;
+ uint32_t status;
+ uint32_t lc[2];
+ uint32_t fault_type;
+ uint32_t watchdog_timer;
+
+ bool ns;
+ uint8_t request_flag;
+ uint8_t wakeup;
+ uint8_t wfp_sbp;
+
+ uint8_t state;
+ uint8_t stall;
+
+ bool is_manager;
+ PL330State *parent;
+ uint8_t tag;
+} PL330Chan;
+
+static const VMStateDescription vmstate_pl330_chan = {
+ .name = "pl330_chan",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(src, PL330Chan),
+ VMSTATE_UINT32(dst, PL330Chan),
+ VMSTATE_UINT32(pc, PL330Chan),
+ VMSTATE_UINT32(control, PL330Chan),
+ VMSTATE_UINT32(status, PL330Chan),
+ VMSTATE_UINT32_ARRAY(lc, PL330Chan, 2),
+ VMSTATE_UINT32(fault_type, PL330Chan),
+ VMSTATE_UINT32(watchdog_timer, PL330Chan),
+ VMSTATE_BOOL(ns, PL330Chan),
+ VMSTATE_UINT8(request_flag, PL330Chan),
+ VMSTATE_UINT8(wakeup, PL330Chan),
+ VMSTATE_UINT8(wfp_sbp, PL330Chan),
+ VMSTATE_UINT8(state, PL330Chan),
+ VMSTATE_UINT8(stall, PL330Chan),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+typedef struct PL330Fifo {
+ uint8_t *buf;
+ uint8_t *tag;
+ uint32_t head;
+ uint32_t num;
+ uint32_t buf_size;
+} PL330Fifo;
+
+static const VMStateDescription vmstate_pl330_fifo = {
+ .name = "pl330_chan",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VBUFFER_UINT32(buf, PL330Fifo, 1, NULL, 0, buf_size),
+ VMSTATE_VBUFFER_UINT32(tag, PL330Fifo, 1, NULL, 0, buf_size),
+ VMSTATE_UINT32(head, PL330Fifo),
+ VMSTATE_UINT32(num, PL330Fifo),
+ VMSTATE_UINT32(buf_size, PL330Fifo),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+typedef struct PL330QueueEntry {
+ uint32_t addr;
+ uint32_t len;
+ uint8_t n;
+ bool inc;
+ bool z;
+ uint8_t tag;
+ uint8_t seqn;
+} PL330QueueEntry;
+
+static const VMStateDescription vmstate_pl330_queue_entry = {
+ .name = "pl330_queue_entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(addr, PL330QueueEntry),
+ VMSTATE_UINT32(len, PL330QueueEntry),
+ VMSTATE_UINT8(n, PL330QueueEntry),
+ VMSTATE_BOOL(inc, PL330QueueEntry),
+ VMSTATE_BOOL(z, PL330QueueEntry),
+ VMSTATE_UINT8(tag, PL330QueueEntry),
+ VMSTATE_UINT8(seqn, PL330QueueEntry),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+typedef struct PL330Queue {
+ PL330State *parent;
+ PL330QueueEntry *queue;
+ uint32_t queue_size;
+} PL330Queue;
+
+static const VMStateDescription vmstate_pl330_queue = {
+ .name = "pl330_queue",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_VARRAY_UINT32(queue, PL330Queue, queue_size, 1,
+ vmstate_pl330_queue_entry, PL330QueueEntry),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+struct PL330State {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ qemu_irq irq_abort;
+ qemu_irq *irq;
+
+ /* Config registers. cfg[5] = CfgDn. */
+ uint32_t cfg[6];
+#define EVENT_SEC_STATE 3
+#define PERIPH_SEC_STATE 4
+ /* cfg 0 bits and pieces */
+ uint32_t num_chnls;
+ uint8_t num_periph_req;
+ uint8_t num_events;
+ uint8_t mgr_ns_at_rst;
+ /* cfg 1 bits and pieces */
+ uint8_t i_cache_len;
+ uint8_t num_i_cache_lines;
+ /* CRD bits and pieces */
+ uint8_t data_width;
+ uint8_t wr_cap;
+ uint8_t wr_q_dep;
+ uint8_t rd_cap;
+ uint8_t rd_q_dep;
+ uint16_t data_buffer_dep;
+
+ PL330Chan manager;
+ PL330Chan *chan;
+ PL330Fifo fifo;
+ PL330Queue read_queue;
+ PL330Queue write_queue;
+ uint8_t *lo_seqn;
+ uint8_t *hi_seqn;
+ QEMUTimer *timer; /* is used for restore dma. */
+
+ uint32_t inten;
+ uint32_t int_status;
+ uint32_t ev_status;
+ uint32_t dbg[2];
+ uint8_t debug_status;
+ uint8_t num_faulting;
+ uint8_t periph_busy[PL330_PERIPH_NUM];
+
+};
+
+#define TYPE_PL330 "pl330"
+#define PL330(obj) OBJECT_CHECK(PL330State, (obj), TYPE_PL330)
+
+static const VMStateDescription vmstate_pl330 = {
+ .name = "pl330",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(manager, PL330State, 0, vmstate_pl330_chan, PL330Chan),
+ VMSTATE_STRUCT_VARRAY_UINT32(chan, PL330State, num_chnls, 0,
+ vmstate_pl330_chan, PL330Chan),
+ VMSTATE_VBUFFER_UINT32(lo_seqn, PL330State, 1, NULL, 0, num_chnls),
+ VMSTATE_VBUFFER_UINT32(hi_seqn, PL330State, 1, NULL, 0, num_chnls),
+ VMSTATE_STRUCT(fifo, PL330State, 0, vmstate_pl330_fifo, PL330Fifo),
+ VMSTATE_STRUCT(read_queue, PL330State, 0, vmstate_pl330_queue,
+ PL330Queue),
+ VMSTATE_STRUCT(write_queue, PL330State, 0, vmstate_pl330_queue,
+ PL330Queue),
+ VMSTATE_TIMER(timer, PL330State),
+ VMSTATE_UINT32(inten, PL330State),
+ VMSTATE_UINT32(int_status, PL330State),
+ VMSTATE_UINT32(ev_status, PL330State),
+ VMSTATE_UINT32_ARRAY(dbg, PL330State, 2),
+ VMSTATE_UINT8(debug_status, PL330State),
+ VMSTATE_UINT8(num_faulting, PL330State),
+ VMSTATE_UINT8_ARRAY(periph_busy, PL330State, PL330_PERIPH_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+typedef struct PL330InsnDesc {
+ /* OPCODE of the instruction */
+ uint8_t opcode;
+ /* Mask so we can select several sibling instructions, such as
+ DMALD, DMALDS and DMALDB */
+ uint8_t opmask;
+ /* Size of instruction in bytes */
+ uint8_t size;
+ /* Interpreter */
+ void (*exec)(PL330Chan *, uint8_t opcode, uint8_t *args, int len);
+} PL330InsnDesc;
+
+
+/* MFIFO Implementation
+ *
+ * MFIFO is implemented as a cyclic buffer of BUF_SIZE size. Tagged bytes are
+ * stored in this buffer. Data is stored in BUF field, tags - in the
+ * corresponding array elements of TAG field.
+ */
+
+/* Initialize queue. */
+
+static void pl330_fifo_init(PL330Fifo *s, uint32_t size)
+{
+ s->buf = g_malloc0(size);
+ s->tag = g_malloc0(size);
+ s->buf_size = size;
+}
+
+/* Cyclic increment */
+
+static inline int pl330_fifo_inc(PL330Fifo *s, int x)
+{
+ return (x + 1) % s->buf_size;
+}
+
+/* Number of empty bytes in MFIFO */
+
+static inline int pl330_fifo_num_free(PL330Fifo *s)
+{
+ return s->buf_size - s->num;
+}
+
+/* Push LEN bytes of data stored in BUF to MFIFO and tag it with TAG.
+ * Zero returned on success, PL330_FIFO_STALL if there is no enough free
+ * space in MFIFO to store requested amount of data. If push was unsuccessful
+ * no data is stored to MFIFO.
+ */
+
+static int pl330_fifo_push(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
+{
+ int i;
+
+ if (s->buf_size - s->num < len) {
+ return PL330_FIFO_STALL;
+ }
+ for (i = 0; i < len; i++) {
+ int push_idx = (s->head + s->num + i) % s->buf_size;
+ s->buf[push_idx] = buf[i];
+ s->tag[push_idx] = tag;
+ }
+ s->num += len;
+ return PL330_FIFO_OK;
+}
+
+/* Get LEN bytes of data from MFIFO and store it to BUF. Tag value of each
+ * byte is verified. Zero returned on success, PL330_FIFO_ERR on tag mismatch
+ * and PL330_FIFO_STALL if there is no enough data in MFIFO. If get was
+ * unsuccessful no data is removed from MFIFO.
+ */
+
+static int pl330_fifo_get(PL330Fifo *s, uint8_t *buf, int len, uint8_t tag)
+{
+ int i;
+
+ if (s->num < len) {
+ return PL330_FIFO_STALL;
+ }
+ for (i = 0; i < len; i++) {
+ if (s->tag[s->head] == tag) {
+ int get_idx = (s->head + i) % s->buf_size;
+ buf[i] = s->buf[get_idx];
+ } else { /* Tag mismatch - Rollback transaction */
+ return PL330_FIFO_ERR;
+ }
+ }
+ s->head = (s->head + len) % s->buf_size;
+ s->num -= len;
+ return PL330_FIFO_OK;
+}
+
+/* Reset MFIFO. This completely erases all data in it. */
+
+static inline void pl330_fifo_reset(PL330Fifo *s)
+{
+ s->head = 0;
+ s->num = 0;
+}
+
+/* Return tag of the first byte stored in MFIFO. If MFIFO is empty
+ * PL330_UNTAGGED is returned.
+ */
+
+static inline uint8_t pl330_fifo_tag(PL330Fifo *s)
+{
+ return (!s->num) ? PL330_UNTAGGED : s->tag[s->head];
+}
+
+/* Returns non-zero if tag TAG is present in fifo or zero otherwise */
+
+static int pl330_fifo_has_tag(PL330Fifo *s, uint8_t tag)
+{
+ int i, n;
+
+ i = s->head;
+ for (n = 0; n < s->num; n++) {
+ if (s->tag[i] == tag) {
+ return 1;
+ }
+ i = pl330_fifo_inc(s, i);
+ }
+ return 0;
+}
+
+/* Remove all entry tagged with TAG from MFIFO */
+
+static void pl330_fifo_tagged_remove(PL330Fifo *s, uint8_t tag)
+{
+ int i, t, n;
+
+ t = i = s->head;
+ for (n = 0; n < s->num; n++) {
+ if (s->tag[i] != tag) {
+ s->buf[t] = s->buf[i];
+ s->tag[t] = s->tag[i];
+ t = pl330_fifo_inc(s, t);
+ } else {
+ s->num = s->num - 1;
+ }
+ i = pl330_fifo_inc(s, i);
+ }
+}
+
+/* Read-Write Queue implementation
+ *
+ * A Read-Write Queue stores up to QUEUE_SIZE instructions (loads or stores).
+ * Each instruction is described by source (for loads) or destination (for
+ * stores) address ADDR, width of data to be loaded/stored LEN, number of
+ * stores/loads to be performed N, INC bit, Z bit and TAG to identify channel
+ * this instruction belongs to. Queue does not store any information about
+ * nature of the instruction: is it load or store. PL330 has different queues
+ * for loads and stores so this is already known at the top level where it
+ * matters.
+ *
+ * Queue works as FIFO for instructions with equivalent tags, but can issue
+ * instructions with different tags in arbitrary order. SEQN field attached to
+ * each instruction helps to achieve this. For each TAG queue contains
+ * instructions with consecutive SEQN values ranging from LO_SEQN[TAG] to
+ * HI_SEQN[TAG]-1 inclusive. SEQN is 8-bit unsigned integer, so SEQN=255 is
+ * followed by SEQN=0.
+ *
+ * Z bit indicates that zeroes should be stored. No MFIFO fetches are performed
+ * in this case.
+ */
+
+static void pl330_queue_reset(PL330Queue *s)
+{
+ int i;
+
+ for (i = 0; i < s->queue_size; i++) {
+ s->queue[i].tag = PL330_UNTAGGED;
+ }
+}
+
+/* Initialize queue */
+static void pl330_queue_init(PL330Queue *s, int size, PL330State *parent)
+{
+ s->parent = parent;
+ s->queue = g_new0(PL330QueueEntry, size);
+ s->queue_size = size;
+}
+
+/* Returns pointer to an empty slot or NULL if queue is full */
+static PL330QueueEntry *pl330_queue_find_empty(PL330Queue *s)
+{
+ int i;
+
+ for (i = 0; i < s->queue_size; i++) {
+ if (s->queue[i].tag == PL330_UNTAGGED) {
+ return &s->queue[i];
+ }
+ }
+ return NULL;
+}
+
+/* Put instruction in queue.
+ * Return value:
+ * - zero - OK
+ * - non-zero - queue is full
+ */
+
+static int pl330_queue_put_insn(PL330Queue *s, uint32_t addr,
+ int len, int n, bool inc, bool z, uint8_t tag)
+{
+ PL330QueueEntry *entry = pl330_queue_find_empty(s);
+
+ if (!entry) {
+ return 1;
+ }
+ entry->tag = tag;
+ entry->addr = addr;
+ entry->len = len;
+ entry->n = n;
+ entry->z = z;
+ entry->inc = inc;
+ entry->seqn = s->parent->hi_seqn[tag];
+ s->parent->hi_seqn[tag]++;
+ return 0;
+}
+
+/* Returns a pointer to queue slot containing instruction which satisfies
+ * following conditions:
+ * - it has valid tag value (not PL330_UNTAGGED)
+ * - if enforce_seq is set it has to be issuable without violating queue
+ * logic (see above)
+ * - if TAG argument is not PL330_UNTAGGED this instruction has tag value
+ * equivalent to the argument TAG value.
+ * If such instruction cannot be found NULL is returned.
+ */
+
+static PL330QueueEntry *pl330_queue_find_insn(PL330Queue *s, uint8_t tag,
+ bool enforce_seq)
+{
+ int i;
+
+ for (i = 0; i < s->queue_size; i++) {
+ if (s->queue[i].tag != PL330_UNTAGGED) {
+ if ((!enforce_seq ||
+ s->queue[i].seqn == s->parent->lo_seqn[s->queue[i].tag]) &&
+ (s->queue[i].tag == tag || tag == PL330_UNTAGGED ||
+ s->queue[i].z)) {
+ return &s->queue[i];
+ }
+ }
+ }
+ return NULL;
+}
+
+/* Removes instruction from queue. */
+
+static inline void pl330_queue_remove_insn(PL330Queue *s, PL330QueueEntry *e)
+{
+ s->parent->lo_seqn[e->tag]++;
+ e->tag = PL330_UNTAGGED;
+}
+
+/* Removes all instructions tagged with TAG from queue. */
+
+static inline void pl330_queue_remove_tagged(PL330Queue *s, uint8_t tag)
+{
+ int i;
+
+ for (i = 0; i < s->queue_size; i++) {
+ if (s->queue[i].tag == tag) {
+ s->queue[i].tag = PL330_UNTAGGED;
+ }
+ }
+}
+
+/* DMA instruction execution engine */
+
+/* Moves DMA channel to the FAULT state and updates it's status. */
+
+static inline void pl330_fault(PL330Chan *ch, uint32_t flags)
+{
+ DB_PRINT("ch: %p, flags: %x\n", ch, flags);
+ ch->fault_type |= flags;
+ if (ch->state == pl330_chan_fault) {
+ return;
+ }
+ ch->state = pl330_chan_fault;
+ ch->parent->num_faulting++;
+ if (ch->parent->num_faulting == 1) {
+ DB_PRINT("abort interrupt raised\n");
+ qemu_irq_raise(ch->parent->irq_abort);
+ }
+}
+
+/*
+ * For information about instructions see PL330 Technical Reference Manual.
+ *
+ * Arguments:
+ * CH - channel executing the instruction
+ * OPCODE - opcode
+ * ARGS - array of 8-bit arguments
+ * LEN - number of elements in ARGS array
+ */
+
+static void pl330_dmaaddh(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint16_t im = (((uint16_t)args[1]) << 8) | ((uint16_t)args[0]);
+ uint8_t ra = (opcode >> 1) & 1;
+
+ if (ch->is_manager) {
+ pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
+ return;
+ }
+ if (ra) {
+ ch->dst += im;
+ } else {
+ ch->src += im;
+ }
+}
+
+static void pl330_dmaend(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ PL330State *s = ch->parent;
+
+ if (ch->state == pl330_chan_executing && !ch->is_manager) {
+ /* Wait for all transfers to complete */
+ if (pl330_fifo_has_tag(&s->fifo, ch->tag) ||
+ pl330_queue_find_insn(&s->read_queue, ch->tag, false) != NULL ||
+ pl330_queue_find_insn(&s->write_queue, ch->tag, false) != NULL) {
+
+ ch->stall = 1;
+ return;
+ }
+ }
+ DB_PRINT("DMA ending!\n");
+ pl330_fifo_tagged_remove(&s->fifo, ch->tag);
+ pl330_queue_remove_tagged(&s->read_queue, ch->tag);
+ pl330_queue_remove_tagged(&s->write_queue, ch->tag);
+ ch->state = pl330_chan_stopped;
+}
+
+static void pl330_dmaflushp(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ uint8_t periph_id;
+
+ if (args[0] & 7) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ periph_id = (args[0] >> 3) & 0x1f;
+ if (periph_id >= ch->parent->num_periph_req) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
+ pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
+ return;
+ }
+ /* Do nothing */
+}
+
+static void pl330_dmago(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t chan_id;
+ uint8_t ns;
+ uint32_t pc;
+ PL330Chan *s;
+
+ DB_PRINT("\n");
+
+ if (!ch->is_manager) {
+ pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
+ return;
+ }
+ ns = !!(opcode & 2);
+ chan_id = args[0] & 7;
+ if ((args[0] >> 3)) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (chan_id >= ch->parent->num_chnls) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ pc = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
+ (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
+ if (ch->parent->chan[chan_id].state != pl330_chan_stopped) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !ns) {
+ pl330_fault(ch, PL330_FAULT_DMAGO_ERR);
+ return;
+ }
+ s = &ch->parent->chan[chan_id];
+ s->ns = ns;
+ s->pc = pc;
+ s->state = pl330_chan_executing;
+}
+
+static void pl330_dmald(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t bs = opcode & 3;
+ uint32_t size, num;
+ bool inc;
+
+ if (bs == 2) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if ((bs == 1 && ch->request_flag == PL330_BURST) ||
+ (bs == 3 && ch->request_flag == PL330_SINGLE)) {
+ /* Perform NOP */
+ return;
+ }
+ if (bs == 1 && ch->request_flag == PL330_SINGLE) {
+ num = 1;
+ } else {
+ num = ((ch->control >> 4) & 0xf) + 1;
+ }
+ size = (uint32_t)1 << ((ch->control >> 1) & 0x7);
+ inc = !!(ch->control & 1);
+ ch->stall = pl330_queue_put_insn(&ch->parent->read_queue, ch->src,
+ size, num, inc, 0, ch->tag);
+ if (!ch->stall) {
+ DB_PRINT("channel:%d address:%08x size:%d num:%d %c\n",
+ ch->tag, ch->src, size, num, inc ? 'Y' : 'N');
+ ch->src += inc ? size * num - (ch->src & (size - 1)) : 0;
+ }
+}
+
+static void pl330_dmaldp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t periph_id;
+
+ if (args[0] & 7) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ periph_id = (args[0] >> 3) & 0x1f;
+ if (periph_id >= ch->parent->num_periph_req) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
+ pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
+ return;
+ }
+ pl330_dmald(ch, opcode, args, len);
+}
+
+static void pl330_dmalp(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t lc = (opcode & 2) >> 1;
+
+ ch->lc[lc] = args[0];
+}
+
+static void pl330_dmakill(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ if (ch->state == pl330_chan_fault ||
+ ch->state == pl330_chan_fault_completing) {
+ /* This is the only way for a channel to leave the faulting state */
+ ch->fault_type = 0;
+ ch->parent->num_faulting--;
+ if (ch->parent->num_faulting == 0) {
+ DB_PRINT("abort interrupt lowered\n");
+ qemu_irq_lower(ch->parent->irq_abort);
+ }
+ }
+ ch->state = pl330_chan_killing;
+ pl330_fifo_tagged_remove(&ch->parent->fifo, ch->tag);
+ pl330_queue_remove_tagged(&ch->parent->read_queue, ch->tag);
+ pl330_queue_remove_tagged(&ch->parent->write_queue, ch->tag);
+ ch->state = pl330_chan_stopped;
+}
+
+static void pl330_dmalpend(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ uint8_t nf = (opcode & 0x10) >> 4;
+ uint8_t bs = opcode & 3;
+ uint8_t lc = (opcode & 4) >> 2;
+
+ if (bs == 2) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if ((bs == 1 && ch->request_flag == PL330_BURST) ||
+ (bs == 3 && ch->request_flag == PL330_SINGLE)) {
+ /* Perform NOP */
+ return;
+ }
+ if (!nf || ch->lc[lc]) {
+ if (nf) {
+ ch->lc[lc]--;
+ }
+ DB_PRINT("loop reiteration\n");
+ ch->pc -= args[0];
+ ch->pc -= len + 1;
+ /* "ch->pc -= args[0] + len + 1" is incorrect when args[0] == 256 */
+ } else {
+ DB_PRINT("loop fallthrough\n");
+ }
+}
+
+
+static void pl330_dmamov(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t rd = args[0] & 7;
+ uint32_t im;
+
+ if ((args[0] >> 3)) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ im = (((uint32_t)args[4]) << 24) | (((uint32_t)args[3]) << 16) |
+ (((uint32_t)args[2]) << 8) | (((uint32_t)args[1]));
+ switch (rd) {
+ case 0:
+ ch->src = im;
+ break;
+ case 1:
+ ch->control = im;
+ break;
+ case 2:
+ ch->dst = im;
+ break;
+ default:
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+}
+
+static void pl330_dmanop(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ /* NOP is NOP. */
+}
+
+static void pl330_dmarmb(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ if (pl330_queue_find_insn(&ch->parent->read_queue, ch->tag, false)) {
+ ch->state = pl330_chan_at_barrier;
+ ch->stall = 1;
+ return;
+ } else {
+ ch->state = pl330_chan_executing;
+ }
+}
+
+static void pl330_dmasev(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t ev_id;
+
+ if (args[0] & 7) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ ev_id = (args[0] >> 3) & 0x1f;
+ if (ev_id >= ch->parent->num_events) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
+ pl330_fault(ch, PL330_FAULT_EVENT_ERR);
+ return;
+ }
+ if (ch->parent->inten & (1 << ev_id)) {
+ ch->parent->int_status |= (1 << ev_id);
+ DB_PRINT("event interrupt raised %d\n", ev_id);
+ qemu_irq_raise(ch->parent->irq[ev_id]);
+ } else {
+ ch->parent->ev_status |= (1 << ev_id);
+ }
+}
+
+static void pl330_dmast(PL330Chan *ch, uint8_t opcode, uint8_t *args, int len)
+{
+ uint8_t bs = opcode & 3;
+ uint32_t size, num;
+ bool inc;
+
+ if (bs == 2) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if ((bs == 1 && ch->request_flag == PL330_BURST) ||
+ (bs == 3 && ch->request_flag == PL330_SINGLE)) {
+ /* Perform NOP */
+ return;
+ }
+ num = ((ch->control >> 18) & 0xf) + 1;
+ size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
+ inc = !!((ch->control >> 14) & 1);
+ ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
+ size, num, inc, 0, ch->tag);
+ if (!ch->stall) {
+ DB_PRINT("channel:%d address:%08x size:%d num:%d %c\n",
+ ch->tag, ch->dst, size, num, inc ? 'Y' : 'N');
+ ch->dst += inc ? size * num - (ch->dst & (size - 1)) : 0;
+ }
+}
+
+static void pl330_dmastp(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ uint8_t periph_id;
+
+ if (args[0] & 7) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ periph_id = (args[0] >> 3) & 0x1f;
+ if (periph_id >= ch->parent->num_periph_req) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
+ pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
+ return;
+ }
+ pl330_dmast(ch, opcode, args, len);
+}
+
+static void pl330_dmastz(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ uint32_t size, num;
+ bool inc;
+
+ num = ((ch->control >> 18) & 0xf) + 1;
+ size = (uint32_t)1 << ((ch->control >> 15) & 0x7);
+ inc = !!((ch->control >> 14) & 1);
+ ch->stall = pl330_queue_put_insn(&ch->parent->write_queue, ch->dst,
+ size, num, inc, 1, ch->tag);
+ if (inc) {
+ ch->dst += size * num;
+ }
+}
+
+static void pl330_dmawfe(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ uint8_t ev_id;
+ int i;
+
+ if (args[0] & 5) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ ev_id = (args[0] >> 3) & 0x1f;
+ if (ev_id >= ch->parent->num_events) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !(ch->parent->cfg[CFG_INS] & (1 << ev_id))) {
+ pl330_fault(ch, PL330_FAULT_EVENT_ERR);
+ return;
+ }
+ ch->wakeup = ev_id;
+ ch->state = pl330_chan_waiting_event;
+ if (~ch->parent->inten & ch->parent->ev_status & 1 << ev_id) {
+ ch->state = pl330_chan_executing;
+ /* If anyone else is currently waiting on the same event, let them
+ * clear the ev_status so they pick up event as well
+ */
+ for (i = 0; i < ch->parent->num_chnls; ++i) {
+ PL330Chan *peer = &ch->parent->chan[i];
+ if (peer->state == pl330_chan_waiting_event &&
+ peer->wakeup == ev_id) {
+ return;
+ }
+ }
+ ch->parent->ev_status &= ~(1 << ev_id);
+ } else {
+ ch->stall = 1;
+ }
+}
+
+static void pl330_dmawfp(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ uint8_t bs = opcode & 3;
+ uint8_t periph_id;
+
+ if (args[0] & 7) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ periph_id = (args[0] >> 3) & 0x1f;
+ if (periph_id >= ch->parent->num_periph_req) {
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+ if (ch->ns && !(ch->parent->cfg[CFG_PNS] & (1 << periph_id))) {
+ pl330_fault(ch, PL330_FAULT_CH_PERIPH_ERR);
+ return;
+ }
+ switch (bs) {
+ case 0: /* S */
+ ch->request_flag = PL330_SINGLE;
+ ch->wfp_sbp = 0;
+ break;
+ case 1: /* P */
+ ch->request_flag = PL330_BURST;
+ ch->wfp_sbp = 2;
+ break;
+ case 2: /* B */
+ ch->request_flag = PL330_BURST;
+ ch->wfp_sbp = 1;
+ break;
+ default:
+ pl330_fault(ch, PL330_FAULT_OPERAND_INVALID);
+ return;
+ }
+
+ if (ch->parent->periph_busy[periph_id]) {
+ ch->state = pl330_chan_waiting_periph;
+ ch->stall = 1;
+ } else if (ch->state == pl330_chan_waiting_periph) {
+ ch->state = pl330_chan_executing;
+ }
+}
+
+static void pl330_dmawmb(PL330Chan *ch, uint8_t opcode,
+ uint8_t *args, int len)
+{
+ if (pl330_queue_find_insn(&ch->parent->write_queue, ch->tag, false)) {
+ ch->state = pl330_chan_at_barrier;
+ ch->stall = 1;
+ return;
+ } else {
+ ch->state = pl330_chan_executing;
+ }
+}
+
+/* NULL terminated array of the instruction descriptions. */
+static const PL330InsnDesc insn_desc[] = {
+ { .opcode = 0x54, .opmask = 0xFD, .size = 3, .exec = pl330_dmaaddh, },
+ { .opcode = 0x00, .opmask = 0xFF, .size = 1, .exec = pl330_dmaend, },
+ { .opcode = 0x35, .opmask = 0xFF, .size = 2, .exec = pl330_dmaflushp, },
+ { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
+ { .opcode = 0x04, .opmask = 0xFC, .size = 1, .exec = pl330_dmald, },
+ { .opcode = 0x25, .opmask = 0xFD, .size = 2, .exec = pl330_dmaldp, },
+ { .opcode = 0x20, .opmask = 0xFD, .size = 2, .exec = pl330_dmalp, },
+ /* dmastp must be before dmalpend in this list, because their maps
+ * are overlapping
+ */
+ { .opcode = 0x29, .opmask = 0xFD, .size = 2, .exec = pl330_dmastp, },
+ { .opcode = 0x28, .opmask = 0xE8, .size = 2, .exec = pl330_dmalpend, },
+ { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
+ { .opcode = 0xBC, .opmask = 0xFF, .size = 6, .exec = pl330_dmamov, },
+ { .opcode = 0x18, .opmask = 0xFF, .size = 1, .exec = pl330_dmanop, },
+ { .opcode = 0x12, .opmask = 0xFF, .size = 1, .exec = pl330_dmarmb, },
+ { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
+ { .opcode = 0x08, .opmask = 0xFC, .size = 1, .exec = pl330_dmast, },
+ { .opcode = 0x0C, .opmask = 0xFF, .size = 1, .exec = pl330_dmastz, },
+ { .opcode = 0x36, .opmask = 0xFF, .size = 2, .exec = pl330_dmawfe, },
+ { .opcode = 0x30, .opmask = 0xFC, .size = 2, .exec = pl330_dmawfp, },
+ { .opcode = 0x13, .opmask = 0xFF, .size = 1, .exec = pl330_dmawmb, },
+ { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
+};
+
+/* Instructions which can be issued via debug registers. */
+static const PL330InsnDesc debug_insn_desc[] = {
+ { .opcode = 0xA0, .opmask = 0xFD, .size = 6, .exec = pl330_dmago, },
+ { .opcode = 0x01, .opmask = 0xFF, .size = 1, .exec = pl330_dmakill, },
+ { .opcode = 0x34, .opmask = 0xFF, .size = 2, .exec = pl330_dmasev, },
+ { .opcode = 0x00, .opmask = 0x00, .size = 0, .exec = NULL, }
+};
+
+static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch)
+{
+ uint8_t opcode;
+ int i;
+
+ dma_memory_read(&dma_context_memory, ch->pc, &opcode, 1);
+ for (i = 0; insn_desc[i].size; i++) {
+ if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) {
+ return &insn_desc[i];
+ }
+ }
+ return NULL;
+}
+
+static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn)
+{
+ uint8_t buf[PL330_INSN_MAXSIZE];
+
+ assert(insn->size <= PL330_INSN_MAXSIZE);
+ dma_memory_read(&dma_context_memory, ch->pc, buf, insn->size);
+ insn->exec(ch, buf[0], &buf[1], insn->size - 1);
+}
+
+static inline void pl330_update_pc(PL330Chan *ch,
+ const PL330InsnDesc *insn)
+{
+ ch->pc += insn->size;
+}
+
+/* Try to execute current instruction in channel CH. Number of executed
+ instructions is returned (0 or 1). */
+static int pl330_chan_exec(PL330Chan *ch)
+{
+ const PL330InsnDesc *insn;
+
+ if (ch->state != pl330_chan_executing &&
+ ch->state != pl330_chan_waiting_periph &&
+ ch->state != pl330_chan_at_barrier &&
+ ch->state != pl330_chan_waiting_event) {
+ DB_PRINT("%d\n", ch->state);
+ return 0;
+ }
+ ch->stall = 0;
+ insn = pl330_fetch_insn(ch);
+ if (!insn) {
+ DB_PRINT("pl330 undefined instruction\n");
+ pl330_fault(ch, PL330_FAULT_UNDEF_INSTR);
+ return 0;
+ }
+ pl330_exec_insn(ch, insn);
+ if (!ch->stall) {
+ pl330_update_pc(ch, insn);
+ ch->watchdog_timer = 0;
+ return 1;
+ /* WDT only active in exec state */
+ } else if (ch->state == pl330_chan_executing) {
+ ch->watchdog_timer++;
+ if (ch->watchdog_timer >= PL330_WATCHDOG_LIMIT) {
+ pl330_fault(ch, PL330_FAULT_LOCKUP_ERR);
+ }
+ }
+ return 0;
+}
+
+/* Try to execute 1 instruction in each channel, one instruction from read
+ queue and one instruction from write queue. Number of successfully executed
+ instructions is returned. */
+static int pl330_exec_cycle(PL330Chan *channel)
+{
+ PL330State *s = channel->parent;
+ PL330QueueEntry *q;
+ int i;
+ int num_exec = 0;
+ int fifo_res = 0;
+ uint8_t buf[PL330_MAX_BURST_LEN];
+
+ /* Execute one instruction in each channel */
+ num_exec += pl330_chan_exec(channel);
+
+ /* Execute one instruction from read queue */
+ q = pl330_queue_find_insn(&s->read_queue, PL330_UNTAGGED, true);
+ if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) {
+ int len = q->len - (q->addr & (q->len - 1));
+
+ dma_memory_read(&dma_context_memory, q->addr, buf, len);
+ if (PL330_ERR_DEBUG > 1) {
+ DB_PRINT("PL330 read from memory @%08x (size = %08x):\n",
+ q->addr, len);
+ hexdump((char *)buf, stderr, "", len);
+ }
+ fifo_res = pl330_fifo_push(&s->fifo, buf, len, q->tag);
+ if (fifo_res == PL330_FIFO_OK) {
+ if (q->inc) {
+ q->addr += len;
+ }
+ q->n--;
+ if (!q->n) {
+ pl330_queue_remove_insn(&s->read_queue, q);
+ }
+ num_exec++;
+ }
+ }
+
+ /* Execute one instruction from write queue. */
+ q = pl330_queue_find_insn(&s->write_queue, pl330_fifo_tag(&s->fifo), true);
+ if (q != NULL) {
+ int len = q->len - (q->addr & (q->len - 1));
+
+ if (q->z) {
+ for (i = 0; i < len; i++) {
+ buf[i] = 0;
+ }
+ } else {
+ fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag);
+ }
+ if (fifo_res == PL330_FIFO_OK || q->z) {
+ dma_memory_write(&dma_context_memory, q->addr, buf, len);
+ if (PL330_ERR_DEBUG > 1) {
+ DB_PRINT("PL330 read from memory @%08x (size = %08x):\n",
+ q->addr, len);
+ hexdump((char *)buf, stderr, "", len);
+ }
+ if (q->inc) {
+ q->addr += len;
+ }
+ num_exec++;
+ } else if (fifo_res == PL330_FIFO_STALL) {
+ pl330_fault(&channel->parent->chan[q->tag],
+ PL330_FAULT_FIFOEMPTY_ERR);
+ }
+ q->n--;
+ if (!q->n) {
+ pl330_queue_remove_insn(&s->write_queue, q);
+ }
+ }
+
+ return num_exec;
+}
+
+static int pl330_exec_channel(PL330Chan *channel)
+{
+ int insr_exec = 0;
+
+ /* TODO: Is it all right to execute everything or should we do per-cycle
+ simulation? */
+ while (pl330_exec_cycle(channel)) {
+ insr_exec++;
+ }
+
+ /* Detect deadlock */
+ if (channel->state == pl330_chan_executing) {
+ pl330_fault(channel, PL330_FAULT_LOCKUP_ERR);
+ }
+ /* Situation when one of the queues has deadlocked but all channels
+ * have finished their programs should be impossible.
+ */
+
+ return insr_exec;
+}
+
+static inline void pl330_exec(PL330State *s)
+{
+ DB_PRINT("\n");
+ int i, insr_exec;
+ do {
+ insr_exec = pl330_exec_channel(&s->manager);
+
+ for (i = 0; i < s->num_chnls; i++) {
+ insr_exec += pl330_exec_channel(&s->chan[i]);
+ }
+ } while (insr_exec);
+}
+
+static void pl330_exec_cycle_timer(void *opaque)
+{
+ PL330State *s = (PL330State *)opaque;
+ pl330_exec(s);
+}
+
+/* Stop or restore dma operations */
+
+static void pl330_dma_stop_irq(void *opaque, int irq, int level)
+{
+ PL330State *s = (PL330State *)opaque;
+
+ if (s->periph_busy[irq] != level) {
+ s->periph_busy[irq] = level;
+ qemu_mod_timer(s->timer, qemu_get_clock_ns(vm_clock));
+ }
+}
+
+static void pl330_debug_exec(PL330State *s)
+{
+ uint8_t args[5];
+ uint8_t opcode;
+ uint8_t chan_id;
+ int i;
+ PL330Chan *ch;
+ const PL330InsnDesc *insn;
+
+ s->debug_status = 1;
+ chan_id = (s->dbg[0] >> 8) & 0x07;
+ opcode = (s->dbg[0] >> 16) & 0xff;
+ args[0] = (s->dbg[0] >> 24) & 0xff;
+ args[1] = (s->dbg[1] >> 0) & 0xff;
+ args[2] = (s->dbg[1] >> 8) & 0xff;
+ args[3] = (s->dbg[1] >> 16) & 0xff;
+ args[4] = (s->dbg[1] >> 24) & 0xff;
+ DB_PRINT("chan id: %d\n", chan_id);
+ if (s->dbg[0] & 1) {
+ ch = &s->chan[chan_id];
+ } else {
+ ch = &s->manager;
+ }
+ insn = NULL;
+ for (i = 0; debug_insn_desc[i].size; i++) {
+ if ((opcode & debug_insn_desc[i].opmask) == debug_insn_desc[i].opcode) {
+ insn = &debug_insn_desc[i];
+ }
+ }
+ if (!insn) {
+ pl330_fault(ch, PL330_FAULT_UNDEF_INSTR | PL330_FAULT_DBG_INSTR);
+ return ;
+ }
+ ch->stall = 0;
+ insn->exec(ch, opcode, args, insn->size - 1);
+ if (ch->fault_type) {
+ ch->fault_type |= PL330_FAULT_DBG_INSTR;
+ }
+ if (ch->stall) {
+ qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not "
+ "implemented\n");
+ }
+ s->debug_status = 0;
+}
+
+/* IOMEM mapped registers */
+
+static void pl330_iomem_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ PL330State *s = (PL330State *) opaque;
+ uint32_t i;
+
+ DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)value);
+
+ switch (offset) {
+ case PL330_REG_INTEN:
+ s->inten = value;
+ break;
+ case PL330_REG_INTCLR:
+ for (i = 0; i < s->num_events; i++) {
+ if (s->int_status & s->inten & value & (1 << i)) {
+ DB_PRINT("event interrupt lowered %d\n", i);
+ qemu_irq_lower(s->irq[i]);
+ }
+ }
+ s->ev_status &= ~(value & s->inten);
+ s->int_status &= ~(value & s->inten);
+ break;
+ case PL330_REG_DBGCMD:
+ if ((value & 3) == 0) {
+ pl330_debug_exec(s);
+ pl330_exec(s);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
+ "for offset " TARGET_FMT_plx "\n", (unsigned)value,
+ offset);
+ }
+ break;
+ case PL330_REG_DBGINST0:
+ DB_PRINT("s->dbg[0] = %08x\n", (unsigned)value);
+ s->dbg[0] = value;
+ break;
+ case PL330_REG_DBGINST1:
+ DB_PRINT("s->dbg[1] = %08x\n", (unsigned)value);
+ s->dbg[1] = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx
+ "\n", offset);
+ break;
+ }
+}
+
+static inline uint32_t pl330_iomem_read_imp(void *opaque,
+ hwaddr offset)
+{
+ PL330State *s = (PL330State *)opaque;
+ int chan_id;
+ int i;
+ uint32_t res;
+
+ if (offset >= PL330_REG_PERIPH_ID && offset < PL330_REG_PERIPH_ID + 32) {
+ return pl330_id[(offset - PL330_REG_PERIPH_ID) >> 2];
+ }
+ if (offset >= PL330_REG_CR0_BASE && offset < PL330_REG_CR0_BASE + 24) {
+ return s->cfg[(offset - PL330_REG_CR0_BASE) >> 2];
+ }
+ if (offset >= PL330_REG_CHANCTRL && offset < PL330_REG_DBGSTATUS) {
+ offset -= PL330_REG_CHANCTRL;
+ chan_id = offset >> 5;
+ if (chan_id >= s->num_chnls) {
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
+ TARGET_FMT_plx "\n", offset);
+ return 0;
+ }
+ switch (offset & 0x1f) {
+ case 0x00:
+ return s->chan[chan_id].src;
+ case 0x04:
+ return s->chan[chan_id].dst;
+ case 0x08:
+ return s->chan[chan_id].control;
+ case 0x0C:
+ return s->chan[chan_id].lc[0];
+ case 0x10:
+ return s->chan[chan_id].lc[1];
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
+ TARGET_FMT_plx "\n", offset);
+ return 0;
+ }
+ }
+ if (offset >= PL330_REG_CSR_BASE && offset < 0x400) {
+ offset -= PL330_REG_CSR_BASE;
+ chan_id = offset >> 3;
+ if (chan_id >= s->num_chnls) {
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
+ TARGET_FMT_plx "\n", offset);
+ return 0;
+ }
+ switch ((offset >> 2) & 1) {
+ case 0x0:
+ res = (s->chan[chan_id].ns << 21) |
+ (s->chan[chan_id].wakeup << 4) |
+ (s->chan[chan_id].state) |
+ (s->chan[chan_id].wfp_sbp << 14);
+ return res;
+ case 0x1:
+ return s->chan[chan_id].pc;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: read error\n");
+ return 0;
+ }
+ }
+ if (offset >= PL330_REG_FTR_BASE && offset < 0x100) {
+ offset -= PL330_REG_FTR_BASE;
+ chan_id = offset >> 2;
+ if (chan_id >= s->num_chnls) {
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
+ TARGET_FMT_plx "\n", offset);
+ return 0;
+ }
+ return s->chan[chan_id].fault_type;
+ }
+ switch (offset) {
+ case PL330_REG_DSR:
+ return (s->manager.ns << 9) | (s->manager.wakeup << 4) |
+ (s->manager.state & 0xf);
+ case PL330_REG_DPC:
+ return s->manager.pc;
+ case PL330_REG_INTEN:
+ return s->inten;
+ case PL330_REG_INT_EVENT_RIS:
+ return s->ev_status;
+ case PL330_REG_INTMIS:
+ return s->int_status;
+ case PL330_REG_INTCLR:
+ /* Documentation says that we can't read this register
+ * but linux kernel does it
+ */
+ return 0;
+ case PL330_REG_FSRD:
+ return s->manager.state ? 1 : 0;
+ case PL330_REG_FSRC:
+ res = 0;
+ for (i = 0; i < s->num_chnls; i++) {
+ if (s->chan[i].state == pl330_chan_fault ||
+ s->chan[i].state == pl330_chan_fault_completing) {
+ res |= 1 << i;
+ }
+ }
+ return res;
+ case PL330_REG_FTRD:
+ return s->manager.fault_type;
+ case PL330_REG_DBGSTATUS:
+ return s->debug_status;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
+ TARGET_FMT_plx "\n", offset);
+ }
+ return 0;
+}
+
+static uint64_t pl330_iomem_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ int ret = pl330_iomem_read_imp(opaque, offset);
+ DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, ret);
+ return ret;
+}
+
+static const MemoryRegionOps pl330_ops = {
+ .read = pl330_iomem_read,
+ .write = pl330_iomem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+/* Controller logic and initialization */
+
+static void pl330_chan_reset(PL330Chan *ch)
+{
+ ch->src = 0;
+ ch->dst = 0;
+ ch->pc = 0;
+ ch->state = pl330_chan_stopped;
+ ch->watchdog_timer = 0;
+ ch->stall = 0;
+ ch->control = 0;
+ ch->status = 0;
+ ch->fault_type = 0;
+}
+
+static void pl330_reset(DeviceState *d)
+{
+ int i;
+ PL330State *s = PL330(d);
+
+ s->inten = 0;
+ s->int_status = 0;
+ s->ev_status = 0;
+ s->debug_status = 0;
+ s->num_faulting = 0;
+ s->manager.ns = s->mgr_ns_at_rst;
+ pl330_fifo_reset(&s->fifo);
+ pl330_queue_reset(&s->read_queue);
+ pl330_queue_reset(&s->write_queue);
+
+ for (i = 0; i < s->num_chnls; i++) {
+ pl330_chan_reset(&s->chan[i]);
+ }
+ for (i = 0; i < s->num_periph_req; i++) {
+ s->periph_busy[i] = 0;
+ }
+
+ qemu_del_timer(s->timer);
+}
+
+static void pl330_realize(DeviceState *dev, Error **errp)
+{
+ int i;
+ PL330State *s = PL330(dev);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort);
+ memory_region_init_io(&s->iomem, &pl330_ops, s, "dma", PL330_IOMEM_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+
+ s->timer = qemu_new_timer_ns(vm_clock, pl330_exec_cycle_timer, s);
+
+ s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) |
+ (s->num_periph_req > 0 ? 1 : 0) |
+ ((s->num_chnls - 1) & 0x7) << 4 |
+ ((s->num_periph_req - 1) & 0x1f) << 12 |
+ ((s->num_events - 1) & 0x1f) << 17;
+
+ switch (s->i_cache_len) {
+ case (4):
+ s->cfg[1] |= 2;
+ break;
+ case (8):
+ s->cfg[1] |= 3;
+ break;
+ case (16):
+ s->cfg[1] |= 4;
+ break;
+ case (32):
+ s->cfg[1] |= 5;
+ break;
+ default:
+ error_setg(errp, "Bad value for i-cache_len property: %d\n",
+ s->i_cache_len);
+ return;
+ }
+ s->cfg[1] |= ((s->num_i_cache_lines - 1) & 0xf) << 4;
+
+ s->chan = g_new0(PL330Chan, s->num_chnls);
+ s->hi_seqn = g_new0(uint8_t, s->num_chnls);
+ s->lo_seqn = g_new0(uint8_t, s->num_chnls);
+ for (i = 0; i < s->num_chnls; i++) {
+ s->chan[i].parent = s;
+ s->chan[i].tag = (uint8_t)i;
+ }
+ s->manager.parent = s;
+ s->manager.tag = s->num_chnls;
+ s->manager.is_manager = true;
+
+ s->irq = g_new0(qemu_irq, s->num_events);
+ for (i = 0; i < s->num_events; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
+ }
+
+ qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM);
+
+ switch (s->data_width) {
+ case (32):
+ s->cfg[CFG_CRD] |= 0x2;
+ break;
+ case (64):
+ s->cfg[CFG_CRD] |= 0x3;
+ break;
+ case (128):
+ s->cfg[CFG_CRD] |= 0x4;
+ break;
+ default:
+ error_setg(errp, "Bad value for data_width property: %d\n",
+ s->data_width);
+ return;
+ }
+
+ s->cfg[CFG_CRD] |= ((s->wr_cap - 1) & 0x7) << 4 |
+ ((s->wr_q_dep - 1) & 0xf) << 8 |
+ ((s->rd_cap - 1) & 0x7) << 12 |
+ ((s->rd_q_dep - 1) & 0xf) << 16 |
+ ((s->data_buffer_dep - 1) & 0x1ff) << 20;
+
+ pl330_queue_init(&s->read_queue, s->rd_q_dep, s);
+ pl330_queue_init(&s->write_queue, s->wr_q_dep, s);
+ pl330_fifo_init(&s->fifo, s->data_buffer_dep);
+}
+
+static Property pl330_properties[] = {
+ /* CR0 */
+ DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8),
+ DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4),
+ DEFINE_PROP_UINT8("num_events", PL330State, num_events, 16),
+ DEFINE_PROP_UINT8("mgr_ns_at_rst", PL330State, mgr_ns_at_rst, 0),
+ /* CR1 */
+ DEFINE_PROP_UINT8("i-cache_len", PL330State, i_cache_len, 4),
+ DEFINE_PROP_UINT8("num_i-cache_lines", PL330State, num_i_cache_lines, 8),
+ /* CR2-4 */
+ DEFINE_PROP_UINT32("boot_addr", PL330State, cfg[CFG_BOOT_ADDR], 0),
+ DEFINE_PROP_UINT32("INS", PL330State, cfg[CFG_INS], 0),
+ DEFINE_PROP_UINT32("PNS", PL330State, cfg[CFG_PNS], 0),
+ /* CRD */
+ DEFINE_PROP_UINT8("data_width", PL330State, data_width, 64),
+ DEFINE_PROP_UINT8("wr_cap", PL330State, wr_cap, 8),
+ DEFINE_PROP_UINT8("wr_q_dep", PL330State, wr_q_dep, 16),
+ DEFINE_PROP_UINT8("rd_cap", PL330State, rd_cap, 8),
+ DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16),
+ DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pl330_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = pl330_realize;
+ dc->reset = pl330_reset;
+ dc->props = pl330_properties;
+ dc->vmsd = &vmstate_pl330;
+}
+
+static const TypeInfo pl330_type_info = {
+ .name = TYPE_PL330,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PL330State),
+ .class_init = pl330_class_init,
+};
+
+static void pl330_register_types(void)
+{
+ type_register_static(&pl330_type_info);
+}
+
+type_init(pl330_register_types)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f355a9b..7b2a11f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -629,7 +629,7 @@
spapr->rtas_size);
/* Set up the entry state */
- first_cpu_cpu = CPU(first_cpu);
+ first_cpu_cpu = ENV_GET_CPU(first_cpu);
first_cpu->gpr[3] = spapr->fdt_addr;
first_cpu->gpr[5] = 0;
first_cpu_cpu->halted = 0;
@@ -779,6 +779,11 @@
spapr->htab_shift++;
}
+ /* Set up Interrupt Controller before we create the VCPUs */
+ spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads,
+ XICS_IRQS);
+ spapr->next_irq = XICS_IRQ_BASE;
+
/* init CPUs */
if (cpu_model == NULL) {
cpu_model = kvm_enabled() ? "host" : "POWER7";
@@ -791,6 +796,8 @@
}
env = &cpu->env;
+ xics_cpu_setup(spapr->icp, cpu);
+
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ);
@@ -830,11 +837,6 @@
}
g_free(filename);
-
- /* Set up Interrupt Controller */
- spapr->icp = xics_system_init(XICS_IRQS);
- spapr->next_irq = XICS_IRQ_BASE;
-
/* Set up EPOW events infrastructure */
spapr_events_init(spapr);
@@ -856,7 +858,7 @@
/* Set up PCI */
spapr_pci_rtas_init();
- phb = spapr_create_phb(spapr, 0, "pci");
+ phb = spapr_create_phb(spapr, 0);
for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index dd72743..22cfb7e 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -3,39 +3,7 @@
#include "sysemu/sysemu.h"
#include "helper_regs.h"
#include "hw/spapr.h"
-
-#define HPTES_PER_GROUP 8
-
-#define HPTE_V_SSIZE_SHIFT 62
-#define HPTE_V_AVPN_SHIFT 7
-#define HPTE_V_AVPN 0x3fffffffffffff80ULL
-#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
-#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
-#define HPTE_V_BOLTED 0x0000000000000010ULL
-#define HPTE_V_LOCK 0x0000000000000008ULL
-#define HPTE_V_LARGE 0x0000000000000004ULL
-#define HPTE_V_SECONDARY 0x0000000000000002ULL
-#define HPTE_V_VALID 0x0000000000000001ULL
-
-#define HPTE_R_PP0 0x8000000000000000ULL
-#define HPTE_R_TS 0x4000000000000000ULL
-#define HPTE_R_KEY_HI 0x3000000000000000ULL
-#define HPTE_R_RPN_SHIFT 12
-#define HPTE_R_RPN 0x3ffffffffffff000ULL
-#define HPTE_R_FLAGS 0x00000000000003ffULL
-#define HPTE_R_PP 0x0000000000000003ULL
-#define HPTE_R_N 0x0000000000000004ULL
-#define HPTE_R_G 0x0000000000000008ULL
-#define HPTE_R_M 0x0000000000000010ULL
-#define HPTE_R_I 0x0000000000000020ULL
-#define HPTE_R_W 0x0000000000000040ULL
-#define HPTE_R_WIMG 0x0000000000000078ULL
-#define HPTE_R_C 0x0000000000000080ULL
-#define HPTE_R_R 0x0000000000000100ULL
-#define HPTE_R_KEY_LO 0x0000000000000e00ULL
-
-#define HPTE_V_1TB_SEG 0x4000000000000000ULL
-#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
+#include "mmu-hash64.h"
static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
target_ulong pte_index)
@@ -44,17 +12,17 @@
rb = (v & ~0x7fULL) << 16; /* AVA field */
va_low = pte_index >> 3;
- if (v & HPTE_V_SECONDARY) {
+ if (v & HPTE64_V_SECONDARY) {
va_low = ~va_low;
}
/* xor vsid from AVA */
- if (!(v & HPTE_V_1TB_SEG)) {
+ if (!(v & HPTE64_V_1TB_SEG)) {
va_low ^= v >> 12;
} else {
va_low ^= v >> 24;
}
va_low &= 0x7ff;
- if (v & HPTE_V_LARGE) {
+ if (v & HPTE64_V_LARGE) {
rb |= 1; /* L field */
#if 0 /* Disable that P7 specific bit for now */
if (r & 0xff000) {
@@ -84,10 +52,10 @@
target_ulong page_shift = 12;
target_ulong raddr;
target_ulong i;
- uint8_t *hpte;
+ hwaddr hpte;
/* only handle 4k and 16M pages for now */
- if (pteh & HPTE_V_LARGE) {
+ if (pteh & HPTE64_V_LARGE) {
#if 0 /* We don't support 64k pages yet */
if ((ptel & 0xf000) == 0x1000) {
/* 64k page */
@@ -105,11 +73,11 @@
}
}
- raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);
+ raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
if (raddr < spapr->ram_limit) {
/* Regular RAM - should have WIMG=0010 */
- if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
+ if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
return H_PARAMETER;
}
} else {
@@ -117,7 +85,7 @@
/* FIXME: What WIMG combinations could be sensible for IO?
* For now we allow WIMG=010x, but are there others? */
/* FIXME: Should we check against registered IO addresses? */
- if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
+ if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) {
return H_PARAMETER;
}
}
@@ -129,26 +97,26 @@
}
if (likely((flags & H_EXACT) == 0)) {
pte_index &= ~7ULL;
- hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
+ hpte = pte_index * HASH_PTE_SIZE_64;
for (i = 0; ; ++i) {
if (i == 8) {
return H_PTEG_FULL;
}
- if ((ldq_p(hpte) & HPTE_V_VALID) == 0) {
+ if ((ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) == 0) {
break;
}
hpte += HASH_PTE_SIZE_64;
}
} else {
i = 0;
- hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
- if (ldq_p(hpte) & HPTE_V_VALID) {
+ hpte = pte_index * HASH_PTE_SIZE_64;
+ if (ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) {
return H_PTEG_FULL;
}
}
- stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
+ ppc_hash64_store_hpte1(env, hpte, ptel);
/* eieio(); FIXME: need some sort of barrier for smp? */
- stq_p(hpte, pteh);
+ ppc_hash64_store_hpte0(env, hpte, pteh);
args[0] = pte_index + i;
return H_SUCCESS;
@@ -166,26 +134,26 @@
target_ulong flags,
target_ulong *vp, target_ulong *rp)
{
- uint8_t *hpte;
+ hwaddr hpte;
target_ulong v, r, rb;
if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
return REMOVE_PARM;
}
- hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);
+ hpte = ptex * HASH_PTE_SIZE_64;
- v = ldq_p(hpte);
- r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
+ v = ppc_hash64_load_hpte0(env, hpte);
+ r = ppc_hash64_load_hpte1(env, hpte);
- if ((v & HPTE_V_VALID) == 0 ||
+ if ((v & HPTE64_V_VALID) == 0 ||
((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
((flags & H_ANDCOND) && (v & avpn) != 0)) {
return REMOVE_NOT_FOUND;
}
*vp = v;
*rp = r;
- stq_p(hpte, 0);
+ ppc_hash64_store_hpte0(env, hpte, 0);
rb = compute_tlbie_rb(v, r, ptex);
ppc_tlb_invalidate_one(env, rb);
return REMOVE_SUCCESS;
@@ -271,7 +239,7 @@
switch (ret) {
case REMOVE_SUCCESS:
- *tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
+ *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
break;
case REMOVE_PARM:
@@ -292,34 +260,34 @@
target_ulong flags = args[0];
target_ulong pte_index = args[1];
target_ulong avpn = args[2];
- uint8_t *hpte;
+ hwaddr hpte;
target_ulong v, r, rb;
if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
return H_PARAMETER;
}
- hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
+ hpte = pte_index * HASH_PTE_SIZE_64;
- v = ldq_p(hpte);
- r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
+ v = ppc_hash64_load_hpte0(env, hpte);
+ r = ppc_hash64_load_hpte1(env, hpte);
- if ((v & HPTE_V_VALID) == 0 ||
+ if ((v & HPTE64_V_VALID) == 0 ||
((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
return H_NOT_FOUND;
}
- r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
- HPTE_R_KEY_HI | HPTE_R_KEY_LO);
- r |= (flags << 55) & HPTE_R_PP0;
- r |= (flags << 48) & HPTE_R_KEY_HI;
- r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
+ r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
+ HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
+ r |= (flags << 55) & HPTE64_R_PP0;
+ r |= (flags << 48) & HPTE64_R_KEY_HI;
+ r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
rb = compute_tlbie_rb(v, r, pte_index);
- stq_p(hpte, v & ~HPTE_V_VALID);
+ ppc_hash64_store_hpte0(env, hpte, v & ~HPTE64_V_VALID);
ppc_tlb_invalidate_one(env, rb);
- stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
+ ppc_hash64_store_hpte1(env, hpte, r);
/* Don't need a memory barrier, due to qemu's global lock */
- stq_p(hpte, v);
+ ppc_hash64_store_hpte0(env, hpte, v);
return H_SUCCESS;
}
diff --git a/hw/ppc/xics.c b/hw/ppc/xics.c
index c3ef12f..374da5b 100644
--- a/hw/ppc/xics.c
+++ b/hw/ppc/xics.c
@@ -521,46 +521,39 @@
}
}
-struct icp_state *xics_system_init(int nr_irqs)
+void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
{
- CPUPPCState *env;
- CPUState *cpu;
- int max_server_num;
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ struct icp_server_state *ss = &icp->ss[cs->cpu_index];
+
+ assert(cs->cpu_index < icp->nr_servers);
+
+ switch (PPC_INPUT(env)) {
+ case PPC_FLAGS_INPUT_POWER7:
+ ss->output = env->irq_inputs[POWER7_INPUT_INT];
+ break;
+
+ case PPC_FLAGS_INPUT_970:
+ ss->output = env->irq_inputs[PPC970_INPUT_INT];
+ break;
+
+ default:
+ fprintf(stderr, "XICS interrupt controller does not support this CPU "
+ "bus model\n");
+ abort();
+ }
+}
+
+struct icp_state *xics_system_init(int nr_servers, int nr_irqs)
+{
struct icp_state *icp;
struct ics_state *ics;
- max_server_num = -1;
- for (env = first_cpu; env != NULL; env = env->next_cpu) {
- cpu = CPU(ppc_env_get_cpu(env));
- if (cpu->cpu_index > max_server_num) {
- max_server_num = cpu->cpu_index;
- }
- }
-
icp = g_malloc0(sizeof(*icp));
- icp->nr_servers = max_server_num + 1;
+ icp->nr_servers = nr_servers;
icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
- for (env = first_cpu; env != NULL; env = env->next_cpu) {
- cpu = CPU(ppc_env_get_cpu(env));
- struct icp_server_state *ss = &icp->ss[cpu->cpu_index];
-
- switch (PPC_INPUT(env)) {
- case PPC_FLAGS_INPUT_POWER7:
- ss->output = env->irq_inputs[POWER7_INPUT_INT];
- break;
-
- case PPC_FLAGS_INPUT_970:
- ss->output = env->irq_inputs[PPC970_INPUT_INT];
- break;
-
- default:
- hw_error("XICS interrupt model does not support this CPU bus "
- "model\n");
- exit(1);
- }
- }
-
ics = g_malloc0(sizeof(*ics));
ics->nr_irqs = nr_irqs;
ics->offset = XICS_IRQ_BASE;
diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
index 6484d27..f2b0c93 100644
--- a/hw/pxa2xx_lcd.c
+++ b/hw/pxa2xx_lcd.c
@@ -39,7 +39,7 @@
int irqlevel;
int invalidated;
- DisplayState *ds;
+ QemuConsole *con;
drawfn *line_fn[2];
int dest_width;
int xres, yres;
@@ -579,6 +579,7 @@
/* Load new palette for a given DMA channel, convert to internal format */
static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i, n, format, r, g, b, alpha;
uint32_t *dest;
uint8_t *src;
@@ -652,7 +653,7 @@
src += 4;
break;
}
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 8:
*dest = rgb_to_pixel8(r, g, b) | alpha;
break;
@@ -676,6 +677,7 @@
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width)
@@ -693,7 +695,7 @@
dest_width = s->xres * s->dest_width;
*miny = 0;
- framebuffer_update_display(s->ds, s->sysmem,
+ framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, dest_width, s->dest_width,
s->invalidated,
@@ -703,6 +705,7 @@
static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width)
@@ -720,7 +723,7 @@
dest_width = s->yres * s->dest_width;
*miny = 0;
- framebuffer_update_display(s->ds, s->sysmem,
+ framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, s->dest_width, -dest_width,
s->invalidated,
@@ -731,6 +734,7 @@
static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width) {
@@ -751,7 +755,7 @@
dest_width = s->xres * s->dest_width;
*miny = 0;
- framebuffer_update_display(s->ds, s->sysmem,
+ framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, -dest_width, -s->dest_width,
s->invalidated,
@@ -761,6 +765,7 @@
static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
hwaddr addr, int *miny, int *maxy)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int src_width, dest_width;
drawfn fn = NULL;
if (s->dest_width) {
@@ -781,7 +786,7 @@
dest_width = s->yres * s->dest_width;
*miny = 0;
- framebuffer_update_display(s->ds, s->sysmem,
+ framebuffer_update_display(surface, s->sysmem,
addr, s->xres, s->yres,
src_width, -s->dest_width, dest_width,
s->invalidated,
@@ -800,9 +805,9 @@
if (width != s->xres || height != s->yres) {
if (s->orientation == 90 || s->orientation == 270) {
- qemu_console_resize(s->ds, height, width);
+ qemu_console_resize(s->con, height, width);
} else {
- qemu_console_resize(s->ds, width, height);
+ qemu_console_resize(s->con, width, height);
}
s->invalidated = 1;
s->xres = width;
@@ -871,20 +876,20 @@
if (miny >= 0) {
switch (s->orientation) {
case 0:
- dpy_gfx_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
+ dpy_gfx_update(s->con, 0, miny, s->xres, maxy - miny + 1);
break;
case 90:
- dpy_gfx_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
+ dpy_gfx_update(s->con, miny, 0, maxy - miny + 1, s->xres);
break;
case 180:
maxy = s->yres - maxy - 1;
miny = s->yres - miny - 1;
- dpy_gfx_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
+ dpy_gfx_update(s->con, 0, maxy, s->xres, miny - maxy + 1);
break;
case 270:
maxy = s->yres - maxy - 1;
miny = s->yres - miny - 1;
- dpy_gfx_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
+ dpy_gfx_update(s->con, maxy, 0, miny - maxy + 1, s->xres);
break;
}
}
@@ -990,6 +995,7 @@
hwaddr base, qemu_irq irq)
{
PXA2xxLCDState *s;
+ DisplaySurface *surface;
s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
s->invalidated = 1;
@@ -1002,11 +1008,12 @@
"pxa2xx-lcd-controller", 0x00100000);
memory_region_add_subregion(sysmem, base, &s->iomem);
- s->ds = graphic_console_init(pxa2xx_update_display,
- pxa2xx_invalidate_display,
- NULL, NULL, s);
+ s->con = graphic_console_init(pxa2xx_update_display,
+ pxa2xx_invalidate_display,
+ NULL, NULL, s);
+ surface = qemu_console_surface(s->con);
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
s->dest_width = 0;
break;
diff --git a/hw/qdev-addr.c b/hw/qdev-addr.c
index 2398b4a..80a38bb 100644
--- a/hw/qdev-addr.c
+++ b/hw/qdev-addr.c
@@ -42,7 +42,7 @@
int64_t value;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
diff --git a/hw/qdev-core.h b/hw/qdev-core.h
index 2486f36..547fbc7 100644
--- a/hw/qdev-core.h
+++ b/hw/qdev-core.h
@@ -175,6 +175,9 @@
uint8_t bitnr;
uint8_t qtype;
int64_t defval;
+ int arrayoffset;
+ PropertyInfo *arrayinfo;
+ int arrayfieldsize;
};
struct PropertyInfo {
diff --git a/hw/qdev-properties-system.c b/hw/qdev-properties-system.c
index 8795144..28813d3 100644
--- a/hw/qdev-properties-system.c
+++ b/hw/qdev-properties-system.c
@@ -43,7 +43,7 @@
int ret;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -287,7 +287,7 @@
NetClientState *hubport;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
diff --git a/hw/qdev-properties.c b/hw/qdev-properties.c
index 0307a78..168c466 100644
--- a/hw/qdev-properties.c
+++ b/hw/qdev-properties.c
@@ -7,6 +7,20 @@
#include "qapi/visitor.h"
#include "char/char.h"
+void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
+ Error **errp)
+{
+ if (dev->id) {
+ error_setg(errp, "Attempt to set property '%s' on device '%s' "
+ "(type '%s') after it was realized", name, dev->id,
+ object_get_typename(OBJECT(dev)));
+ } else {
+ error_setg(errp, "Attempt to set property '%s' on anonymous device "
+ "(type '%s') after it was realized", name,
+ object_get_typename(OBJECT(dev)));
+ }
+}
+
void *qdev_get_prop_ptr(DeviceState *dev, Property *prop)
{
void *ptr = dev;
@@ -33,7 +47,7 @@
int *ptr = qdev_get_prop_ptr(dev, prop);
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -86,7 +100,7 @@
bool value;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -126,7 +140,7 @@
uint8_t *ptr = qdev_get_prop_ptr(dev, prop);
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -193,7 +207,7 @@
uint16_t *ptr = qdev_get_prop_ptr(dev, prop);
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -226,7 +240,7 @@
uint32_t *ptr = qdev_get_prop_ptr(dev, prop);
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -251,7 +265,7 @@
int32_t *ptr = qdev_get_prop_ptr(dev, prop);
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -324,7 +338,7 @@
uint64_t *ptr = qdev_get_prop_ptr(dev, prop);
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -414,7 +428,7 @@
char *str;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -478,7 +492,7 @@
char *str, *p;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -570,7 +584,7 @@
char *str;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -641,7 +655,7 @@
const int64_t max = 32768;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -709,7 +723,7 @@
unsigned int slot = 0, func = 0;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -779,6 +793,110 @@
.set = set_pci_host_devaddr,
};
+/* --- support for array properties --- */
+
+/* Used as an opaque for the object properties we add for each
+ * array element. Note that the struct Property must be first
+ * in the struct so that a pointer to this works as the opaque
+ * for the underlying element's property hooks as well as for
+ * our own release callback.
+ */
+typedef struct {
+ struct Property prop;
+ char *propname;
+ ObjectPropertyRelease *release;
+} ArrayElementProperty;
+
+/* object property release callback for array element properties:
+ * we call the underlying element's property release hook, and
+ * then free the memory we allocated when we added the property.
+ */
+static void array_element_release(Object *obj, const char *name, void *opaque)
+{
+ ArrayElementProperty *p = opaque;
+ if (p->release) {
+ p->release(obj, name, opaque);
+ }
+ g_free(p->propname);
+ g_free(p);
+}
+
+static void set_prop_arraylen(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+ /* Setter for the property which defines the length of a
+ * variable-sized property array. As well as actually setting the
+ * array-length field in the device struct, we have to create the
+ * array itself and dynamically add the corresponding properties.
+ */
+ DeviceState *dev = DEVICE(obj);
+ Property *prop = opaque;
+ uint32_t *alenptr = qdev_get_prop_ptr(dev, prop);
+ void **arrayptr = (void *)dev + prop->arrayoffset;
+ void *eltptr;
+ const char *arrayname;
+ int i;
+
+ if (dev->realized) {
+ qdev_prop_set_after_realize(dev, name, errp);
+ return;
+ }
+ if (*alenptr) {
+ error_setg(errp, "array size property %s may not be set more than once",
+ name);
+ return;
+ }
+ visit_type_uint32(v, alenptr, name, errp);
+ if (error_is_set(errp)) {
+ return;
+ }
+ if (!*alenptr) {
+ return;
+ }
+
+ /* DEFINE_PROP_ARRAY guarantees that name should start with this prefix;
+ * strip it off so we can get the name of the array itself.
+ */
+ assert(strncmp(name, PROP_ARRAY_LEN_PREFIX,
+ strlen(PROP_ARRAY_LEN_PREFIX)) == 0);
+ arrayname = name + strlen(PROP_ARRAY_LEN_PREFIX);
+
+ /* Note that it is the responsibility of the individual device's deinit
+ * to free the array proper.
+ */
+ *arrayptr = eltptr = g_malloc0(*alenptr * prop->arrayfieldsize);
+ for (i = 0; i < *alenptr; i++, eltptr += prop->arrayfieldsize) {
+ char *propname = g_strdup_printf("%s[%d]", arrayname, i);
+ ArrayElementProperty *arrayprop = g_new0(ArrayElementProperty, 1);
+ arrayprop->release = prop->arrayinfo->release;
+ arrayprop->propname = propname;
+ arrayprop->prop.info = prop->arrayinfo;
+ arrayprop->prop.name = propname;
+ /* This ugly piece of pointer arithmetic sets up the offset so
+ * that when the underlying get/set hooks call qdev_get_prop_ptr
+ * they get the right answer despite the array element not actually
+ * being inside the device struct.
+ */
+ arrayprop->prop.offset = eltptr - (void *)dev;
+ assert(qdev_get_prop_ptr(dev, &arrayprop->prop) == eltptr);
+ object_property_add(obj, propname,
+ arrayprop->prop.info->name,
+ arrayprop->prop.info->get,
+ arrayprop->prop.info->set,
+ array_element_release,
+ arrayprop, errp);
+ if (error_is_set(errp)) {
+ return;
+ }
+ }
+}
+
+PropertyInfo qdev_prop_arraylen = {
+ .name = "uint32",
+ .get = get_uint32,
+ .set = set_prop_arraylen,
+};
+
/* --- public helpers --- */
static Property *qdev_prop_walk(Property *props, const char *name)
diff --git a/hw/qdev-properties.h b/hw/qdev-properties.h
index 0b0465c..a379339 100644
--- a/hw/qdev-properties.h
+++ b/hw/qdev-properties.h
@@ -26,6 +26,7 @@
extern PropertyInfo qdev_prop_pci_devfn;
extern PropertyInfo qdev_prop_blocksize;
extern PropertyInfo qdev_prop_pci_host_devaddr;
+extern PropertyInfo qdev_prop_arraylen;
#define DEFINE_PROP(_name, _state, _field, _prop, _type) { \
.name = (_name), \
@@ -51,6 +52,44 @@
.defval = (bool)_defval, \
}
+#define PROP_ARRAY_LEN_PREFIX "len-"
+
+/**
+ * DEFINE_PROP_ARRAY:
+ * @_name: name of the array
+ * @_state: name of the device state structure type
+ * @_field: uint32_t field in @_state to hold the array length
+ * @_arrayfield: field in @_state (of type '@_arraytype *') which
+ * will point to the array
+ * @_arrayprop: PropertyInfo defining what property the array elements have
+ * @_arraytype: C type of the array elements
+ *
+ * Define device properties for a variable-length array _name. A
+ * static property "len-arrayname" is defined. When the device creator
+ * sets this property to the desired length of array, further dynamic
+ * properties "arrayname[0]", "arrayname[1]", ... are defined so the
+ * device creator can set the array element values. Setting the
+ * "len-arrayname" property more than once is an error.
+ *
+ * When the array length is set, the @_field member of the device
+ * struct is set to the array length, and @_arrayfield is set to point
+ * to (zero-initialised) memory allocated for the array. For a zero
+ * length array, @_field will be set to 0 and @_arrayfield to NULL.
+ * It is the responsibility of the device deinit code to free the
+ * @_arrayfield memory.
+ */
+#define DEFINE_PROP_ARRAY(_name, _state, _field, \
+ _arrayfield, _arrayprop, _arraytype) { \
+ .name = (PROP_ARRAY_LEN_PREFIX _name), \
+ .info = &(qdev_prop_arraylen), \
+ .offset = offsetof(_state, _field) \
+ + type_check(uint32_t, typeof_field(_state, _field)), \
+ .qtype = QTYPE_QINT, \
+ .arrayinfo = &(_arrayprop), \
+ .arrayfieldsize = sizeof(_arraytype), \
+ .arrayoffset = offsetof(_state, _arrayfield), \
+ }
+
#define DEFINE_PROP_UINT8(_n, _s, _f, _d) \
DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint8, uint8_t)
#define DEFINE_PROP_UINT16(_n, _s, _f, _d) \
@@ -128,4 +167,16 @@
*/
void qdev_property_add_static(DeviceState *dev, Property *prop, Error **errp);
+/**
+ * @qdev_prop_set_after_realize:
+ * @dev: device
+ * @name: name of property
+ * @errp: indirect pointer to Error to be set
+ * Set the Error object to report that an attempt was made to set a property
+ * on a device after it has already been realized. This is a utility function
+ * which allows property-setter functions to easily report the error in
+ * a friendly format identifying both the device and the property.
+ */
+void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
+ Error **errp);
#endif
diff --git a/hw/qdev.c b/hw/qdev.c
index 0cdf568..9b0f652 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -119,11 +119,10 @@
if (bus) {
error_report("Unknown device '%s' for bus '%s'", name,
object_get_typename(OBJECT(bus)));
- abort();
} else {
error_report("Unknown device '%s' for default sysbus", name);
- abort();
}
+ abort();
}
return dev;
@@ -565,7 +564,7 @@
int ret;
if (dev->realized) {
- error_set(errp, QERR_PERMISSION_DENIED);
+ qdev_prop_set_after_realize(dev, name, errp);
return;
}
@@ -713,6 +712,7 @@
DeviceState *dev = DEVICE(obj);
ObjectClass *class;
Property *prop;
+ Error *err = NULL;
if (qdev_hotplug) {
dev->hotplugged = 1;
@@ -728,15 +728,18 @@
class = object_get_class(OBJECT(dev));
do {
for (prop = DEVICE_CLASS(class)->props; prop && prop->name; prop++) {
- qdev_property_add_legacy(dev, prop, NULL);
- qdev_property_add_static(dev, prop, NULL);
+ qdev_property_add_legacy(dev, prop, &err);
+ assert_no_error(err);
+ qdev_property_add_static(dev, prop, &err);
+ assert_no_error(err);
}
class = object_class_get_parent(class);
} while (class != object_class_by_name(TYPE_DEVICE));
qdev_prop_set_globals(dev);
object_property_add_link(OBJECT(dev), "parent_bus", TYPE_BUS,
- (Object **)&dev->parent_bus, NULL);
+ (Object **)&dev->parent_bus, &err);
+ assert_no_error(err);
}
/* Unlink device from bus and free the structure. */
diff --git a/hw/qxl-render.c b/hw/qxl-render.c
index d77df42..8cd9be4 100644
--- a/hw/qxl-render.c
+++ b/hw/qxl-render.c
@@ -23,11 +23,12 @@
static void qxl_blit(PCIQXLDevice *qxl, QXLRect *rect)
{
+ DisplaySurface *surface = qemu_console_surface(qxl->vga.con);
+ uint8_t *dst = surface_data(surface);
uint8_t *src;
- uint8_t *dst = ds_get_data(qxl->vga.ds);
int len, i;
- if (is_buffer_shared(qxl->vga.ds->surface)) {
+ if (is_buffer_shared(surface)) {
return;
}
if (!qxl->guest_primary.data) {
@@ -98,6 +99,7 @@
static void qxl_render_update_area_unlocked(PCIQXLDevice *qxl)
{
VGACommonState *vga = &qxl->vga;
+ DisplaySurface *surface;
int i;
if (qxl->guest_primary.resized) {
@@ -112,8 +114,7 @@
qxl->guest_primary.bytes_pp,
qxl->guest_primary.bits_pp);
if (qxl->guest_primary.qxl_stride > 0) {
- qemu_free_displaysurface(vga->ds);
- vga->ds->surface = qemu_create_displaysurface_from
+ surface = qemu_create_displaysurface_from
(qxl->guest_primary.surface.width,
qxl->guest_primary.surface.height,
qxl->guest_primary.bits_pp,
@@ -121,18 +122,18 @@
qxl->guest_primary.data,
false);
} else {
- qemu_resize_displaysurface(vga->ds,
- qxl->guest_primary.surface.width,
- qxl->guest_primary.surface.height);
+ surface = qemu_create_displaysurface
+ (qxl->guest_primary.surface.width,
+ qxl->guest_primary.surface.height);
}
- dpy_gfx_resize(vga->ds);
+ dpy_gfx_replace_surface(vga->con, surface);
}
for (i = 0; i < qxl->num_dirty_rects; i++) {
if (qemu_spice_rect_is_empty(qxl->dirty+i)) {
break;
}
qxl_blit(qxl, qxl->dirty+i);
- dpy_gfx_update(vga->ds,
+ dpy_gfx_update(vga->con,
qxl->dirty[i].left, qxl->dirty[i].top,
qxl->dirty[i].right - qxl->dirty[i].left,
qxl->dirty[i].bottom - qxl->dirty[i].top);
@@ -236,7 +237,7 @@
return 1;
}
- if (!dpy_cursor_define_supported(qxl->ssd.ds)) {
+ if (!dpy_cursor_define_supported(qxl->vga.con)) {
return 0;
}
diff --git a/hw/qxl.c b/hw/qxl.c
index ef69348..b66b414 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -118,8 +118,6 @@
QXL_MODE_EX(3200, 2400),
};
-static PCIQXLDevice *qxl0;
-
static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
static void qxl_reset_memslots(PCIQXLDevice *d);
@@ -1075,8 +1073,8 @@
trace_qxl_enter_vga_mode(d->id);
qemu_spice_create_host_primary(&d->ssd);
d->mode = QXL_MODE_VGA;
- dpy_gfx_resize(d->ssd.ds);
vga_dirty_log_start(&d->vga);
+ vga_hw_update();
}
static void qxl_exit_vga_mode(PCIQXLDevice *d)
@@ -1784,7 +1782,7 @@
case QXL_MODE_COMPAT:
case QXL_MODE_NATIVE:
qxl_render_update(qxl);
- ppm_save(filename, qxl->ssd.ds->surface, errp);
+ ppm_save(filename, qxl->ssd.ds, errp);
break;
case QXL_MODE_VGA:
vga->screen_dump(vga, filename, cswitch, errp);
@@ -1866,35 +1864,45 @@
/* display change listener */
-static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
+static void display_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
{
- if (qxl0->mode == QXL_MODE_VGA) {
- qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
+ PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
+
+ if (qxl->mode == QXL_MODE_VGA) {
+ qemu_spice_display_update(&qxl->ssd, x, y, w, h);
}
}
-static void display_resize(struct DisplayState *ds)
+static void display_switch(DisplayChangeListener *dcl,
+ struct DisplaySurface *surface)
{
- if (qxl0->mode == QXL_MODE_VGA) {
- qemu_spice_display_resize(&qxl0->ssd);
+ PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
+
+ qxl->ssd.ds = surface;
+ if (qxl->mode == QXL_MODE_VGA) {
+ qemu_spice_display_switch(&qxl->ssd, surface);
}
}
-static void display_refresh(struct DisplayState *ds)
+static void display_refresh(DisplayChangeListener *dcl)
{
- if (qxl0->mode == QXL_MODE_VGA) {
- qemu_spice_display_refresh(&qxl0->ssd);
+ PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
+
+ if (qxl->mode == QXL_MODE_VGA) {
+ qemu_spice_display_refresh(&qxl->ssd);
} else {
- qemu_mutex_lock(&qxl0->ssd.lock);
- qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
- qemu_mutex_unlock(&qxl0->ssd.lock);
+ qemu_mutex_lock(&qxl->ssd.lock);
+ qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
+ qemu_mutex_unlock(&qxl->ssd.lock);
}
}
-static DisplayChangeListener display_listener = {
+static DisplayChangeListenerOps display_listener_ops = {
+ .dpy_name = "spice/qxl",
.dpy_gfx_update = display_update,
- .dpy_gfx_resize = display_resize,
- .dpy_refresh = display_refresh,
+ .dpy_gfx_switch = display_switch,
+ .dpy_refresh = display_refresh,
};
static void qxl_init_ramsize(PCIQXLDevice *qxl)
@@ -2055,6 +2063,7 @@
PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
VGACommonState *vga = &qxl->vga;
PortioList *qxl_vga_port_list = g_new(PortioList, 1);
+ DisplayState *ds;
int rc;
qxl->id = 0;
@@ -2065,18 +2074,20 @@
portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
- vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
- qxl_hw_screen_dump, qxl_hw_text_update, qxl);
- qemu_spice_display_init_common(&qxl->ssd, vga->ds);
-
- qxl0 = qxl;
+ vga->con = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
+ qxl_hw_screen_dump, qxl_hw_text_update,
+ qxl);
+ qxl->ssd.con = vga->con,
+ qemu_spice_display_init_common(&qxl->ssd);
rc = qxl_init_common(qxl);
if (rc != 0) {
return rc;
}
- register_displaychangelistener(vga->ds, &display_listener);
+ qxl->ssd.dcl.ops = &display_listener_ops;
+ ds = qemu_console_displaystate(vga->con);
+ register_displaychangelistener(ds, &qxl->ssd.dcl);
return rc;
}
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 786b875..9369507 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -3530,7 +3530,7 @@
k->init = pci_rtl8139_init;
k->exit = pci_rtl8139_uninit;
- k->romfile = "pxe-rtl8139.rom";
+ k->romfile = "efi-rtl8139.rom";
k->vendor_id = PCI_VENDOR_ID_REALTEK;
k->device_id = PCI_DEVICE_ID_REALTEK_8139;
k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
diff --git a/hw/s390x/s390-virtio-bus.c b/hw/s390x/s390-virtio-bus.c
index d9b7f83..8c529c1 100644
--- a/hw/s390x/s390-virtio-bus.c
+++ b/hw/s390x/s390-virtio-bus.c
@@ -162,16 +162,23 @@
return s390_virtio_device_init(dev, vdev);
}
-static int s390_virtio_blk_init(VirtIOS390Device *dev)
+static int s390_virtio_blk_init(VirtIOS390Device *s390_dev)
{
- VirtIODevice *vdev;
-
- vdev = virtio_blk_init((DeviceState *)dev, &dev->blk);
- if (!vdev) {
+ VirtIOBlkS390 *dev = VIRTIO_BLK_S390(s390_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
+ virtio_blk_set_conf(vdev, &(dev->blk));
+ qdev_set_parent_bus(vdev, BUS(&s390_dev->bus));
+ if (qdev_init(vdev) < 0) {
return -1;
}
+ return s390_virtio_device_init(s390_dev, VIRTIO_DEVICE(vdev));
+}
- return s390_virtio_device_init(dev, vdev);
+static void s390_virtio_blk_instance_init(Object *obj)
+{
+ VirtIOBlkS390 *dev = VIRTIO_BLK_S390(obj);
+ object_initialize(OBJECT(&dev->vdev), TYPE_VIRTIO_BLK);
+ object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
}
static int s390_virtio_serial_init(VirtIOS390Device *dev)
@@ -195,16 +202,24 @@
return r;
}
-static int s390_virtio_scsi_init(VirtIOS390Device *dev)
+static int s390_virtio_scsi_init(VirtIOS390Device *s390_dev)
{
- VirtIODevice *vdev;
+ VirtIOSCSIS390 *dev = VIRTIO_SCSI_S390(s390_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
- vdev = virtio_scsi_init((DeviceState *)dev, &dev->scsi);
- if (!vdev) {
+ qdev_set_parent_bus(vdev, BUS(&s390_dev->bus));
+ if (qdev_init(vdev) < 0) {
return -1;
}
- return s390_virtio_device_init(dev, vdev);
+ return s390_virtio_device_init(s390_dev, VIRTIO_DEVICE(vdev));
+}
+
+static void s390_virtio_scsi_instance_init(Object *obj)
+{
+ VirtIOSCSIS390 *dev = VIRTIO_SCSI_S390(obj);
+ object_initialize(OBJECT(&dev->vdev), TYPE_VIRTIO_SCSI);
+ object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
}
static int s390_virtio_rng_init(VirtIOS390Device *dev)
@@ -428,12 +443,7 @@
};
static Property s390_virtio_blk_properties[] = {
- DEFINE_BLOCK_PROPERTIES(VirtIOS390Device, blk.conf),
- DEFINE_BLOCK_CHS_PROPERTIES(VirtIOS390Device, blk.conf),
- DEFINE_PROP_STRING("serial", VirtIOS390Device, blk.serial),
-#ifdef __linux__
- DEFINE_PROP_BIT("scsi", VirtIOS390Device, blk.scsi, 0, true),
-#endif
+ DEFINE_VIRTIO_BLK_PROPERTIES(VirtIOBlkS390, blk),
DEFINE_PROP_END_OF_LIST(),
};
@@ -449,7 +459,8 @@
static const TypeInfo s390_virtio_blk = {
.name = "virtio-blk-s390",
.parent = TYPE_VIRTIO_S390_DEVICE,
- .instance_size = sizeof(VirtIOS390Device),
+ .instance_size = sizeof(VirtIOBlkS390),
+ .instance_init = s390_virtio_blk_instance_init,
.class_init = s390_virtio_blk_class_init,
};
@@ -535,7 +546,8 @@
};
static Property s390_virtio_scsi_properties[] = {
- DEFINE_VIRTIO_SCSI_PROPERTIES(VirtIOS390Device, host_features, scsi),
+ DEFINE_VIRTIO_SCSI_PROPERTIES(VirtIOSCSIS390, vdev.conf),
+ DEFINE_VIRTIO_SCSI_FEATURES(VirtIOS390Device, host_features),
DEFINE_PROP_END_OF_LIST(),
};
@@ -549,9 +561,10 @@
}
static const TypeInfo s390_virtio_scsi = {
- .name = "virtio-scsi-s390",
+ .name = TYPE_VIRTIO_SCSI_S390,
.parent = TYPE_VIRTIO_S390_DEVICE,
- .instance_size = sizeof(VirtIOS390Device),
+ .instance_size = sizeof(VirtIOSCSIS390),
+ .instance_init = s390_virtio_scsi_instance_init,
.class_init = s390_virtio_scsi_class_init,
};
@@ -588,7 +601,7 @@
BusState *qbus;
qbus_create_inplace((BusState *)bus, TYPE_VIRTIO_S390_BUS, qdev, NULL);
qbus = BUS(bus);
- qbus->allow_hotplug = 0;
+ qbus->allow_hotplug = 1;
}
static void virtio_s390_bus_class_init(ObjectClass *klass, void *data)
diff --git a/hw/s390x/s390-virtio-bus.h b/hw/s390x/s390-virtio-bus.h
index 4aacf83..ebe8794 100644
--- a/hw/s390x/s390-virtio-bus.h
+++ b/hw/s390x/s390-virtio-bus.h
@@ -89,12 +89,10 @@
ram_addr_t feat_offs;
uint8_t feat_len;
VirtIODevice *vdev;
- VirtIOBlkConf blk;
NICConf nic;
uint32_t host_features;
virtio_serial_conf serial;
virtio_net_conf net;
- VirtIOSCSIConf scsi;
VirtIORNGConf rng;
VirtioBusState bus;
};
@@ -120,5 +118,27 @@
void s390_virtio_device_sync(VirtIOS390Device *dev);
void s390_virtio_reset_idx(VirtIOS390Device *dev);
+/* virtio-blk-s390 */
+
+#define TYPE_VIRTIO_BLK_S390 "virtio-blk-s390"
+#define VIRTIO_BLK_S390(obj) \
+ OBJECT_CHECK(VirtIOBlkS390, (obj), TYPE_VIRTIO_BLK_S390)
+
+typedef struct VirtIOBlkS390 {
+ VirtIOS390Device parent_obj;
+ VirtIOBlock vdev;
+ VirtIOBlkConf blk;
+} VirtIOBlkS390;
+
+/* virtio-scsi-s390 */
+
+#define TYPE_VIRTIO_SCSI_S390 "virtio-scsi-s390"
+#define VIRTIO_SCSI_S390(obj) \
+ OBJECT_CHECK(VirtIOSCSIS390, (obj), TYPE_VIRTIO_SCSI_S390)
+
+typedef struct VirtIOSCSIS390 {
+ VirtIOS390Device parent_obj;
+ VirtIOSCSI vdev;
+} VirtIOSCSIS390;
#endif
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index d436414..76b63e2 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -31,6 +31,9 @@
if (!sch || !css_subch_visible(sch)) {
return -EINVAL;
}
+ if (queue >= VIRTIO_PCI_QUEUE_MAX) {
+ return -EINVAL;
+ }
virtio_queue_notify(virtio_ccw_get_vdev(sch), queue);
return 0;
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index d4361f6..7e79c57 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -570,22 +570,24 @@
return virtio_ccw_exit(dev);
}
-static int virtio_ccw_blk_init(VirtioCcwDevice *dev)
+static int virtio_ccw_blk_init(VirtioCcwDevice *ccw_dev)
{
- VirtIODevice *vdev;
-
- vdev = virtio_blk_init((DeviceState *)dev, &dev->blk);
- if (!vdev) {
+ VirtIOBlkCcw *dev = VIRTIO_BLK_CCW(ccw_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
+ virtio_blk_set_conf(vdev, &(dev->blk));
+ qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
+ if (qdev_init(vdev) < 0) {
return -1;
}
- return virtio_ccw_device_init(dev, vdev);
+ return virtio_ccw_device_init(ccw_dev, VIRTIO_DEVICE(vdev));
}
-static int virtio_ccw_blk_exit(VirtioCcwDevice *dev)
+static void virtio_ccw_blk_instance_init(Object *obj)
{
- virtio_blk_exit(dev->vdev);
- return virtio_ccw_exit(dev);
+ VirtIOBlkCcw *dev = VIRTIO_BLK_CCW(obj);
+ object_initialize(OBJECT(&dev->vdev), TYPE_VIRTIO_BLK);
+ object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
}
static int virtio_ccw_serial_init(VirtioCcwDevice *dev)
@@ -624,22 +626,24 @@
return virtio_ccw_exit(dev);
}
-static int virtio_ccw_scsi_init(VirtioCcwDevice *dev)
+static int virtio_ccw_scsi_init(VirtioCcwDevice *ccw_dev)
{
- VirtIODevice *vdev;
+ VirtIOSCSICcw *dev = VIRTIO_SCSI_CCW(ccw_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
- vdev = virtio_scsi_init((DeviceState *)dev, &dev->scsi);
- if (!vdev) {
+ qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus));
+ if (qdev_init(vdev) < 0) {
return -1;
}
- return virtio_ccw_device_init(dev, vdev);
+ return virtio_ccw_device_init(ccw_dev, VIRTIO_DEVICE(vdev));
}
-static int virtio_ccw_scsi_exit(VirtioCcwDevice *dev)
+static void virtio_ccw_scsi_instance_init(Object *obj)
{
- virtio_scsi_exit(dev->vdev);
- return virtio_ccw_exit(dev);
+ VirtIOSCSICcw *dev = VIRTIO_SCSI_CCW(obj);
+ object_initialize(OBJECT(&dev->vdev), TYPE_VIRTIO_SCSI);
+ object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
}
static int virtio_ccw_rng_init(VirtioCcwDevice *dev)
@@ -754,12 +758,8 @@
static Property virtio_ccw_blk_properties[] = {
DEFINE_PROP_STRING("devno", VirtioCcwDevice, bus_id),
- DEFINE_BLOCK_PROPERTIES(VirtioCcwDevice, blk.conf),
- DEFINE_PROP_STRING("serial", VirtioCcwDevice, blk.serial),
-#ifdef __linux__
- DEFINE_PROP_BIT("scsi", VirtioCcwDevice, blk.scsi, 0, true),
-#endif
DEFINE_VIRTIO_BLK_FEATURES(VirtioCcwDevice, host_features[0]),
+ DEFINE_VIRTIO_BLK_PROPERTIES(VirtIOBlkCcw, blk),
DEFINE_PROP_END_OF_LIST(),
};
@@ -769,15 +769,16 @@
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->init = virtio_ccw_blk_init;
- k->exit = virtio_ccw_blk_exit;
+ k->exit = virtio_ccw_exit;
dc->reset = virtio_ccw_reset;
dc->props = virtio_ccw_blk_properties;
}
static const TypeInfo virtio_ccw_blk = {
- .name = "virtio-blk-ccw",
+ .name = TYPE_VIRTIO_BLK_CCW,
.parent = TYPE_VIRTIO_CCW_DEVICE,
- .instance_size = sizeof(VirtioCcwDevice),
+ .instance_size = sizeof(VirtIOBlkCcw),
+ .instance_init = virtio_ccw_blk_instance_init,
.class_init = virtio_ccw_blk_class_init,
};
@@ -833,7 +834,8 @@
static Property virtio_ccw_scsi_properties[] = {
DEFINE_PROP_STRING("devno", VirtioCcwDevice, bus_id),
- DEFINE_VIRTIO_SCSI_PROPERTIES(VirtioCcwDevice, host_features[0], scsi),
+ DEFINE_VIRTIO_SCSI_PROPERTIES(VirtIOSCSICcw, vdev.conf),
+ DEFINE_VIRTIO_SCSI_FEATURES(VirtioCcwDevice, host_features[0]),
DEFINE_PROP_END_OF_LIST(),
};
@@ -843,15 +845,16 @@
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->init = virtio_ccw_scsi_init;
- k->exit = virtio_ccw_scsi_exit;
+ k->exit = virtio_ccw_exit;
dc->reset = virtio_ccw_reset;
dc->props = virtio_ccw_scsi_properties;
}
static const TypeInfo virtio_ccw_scsi = {
- .name = "virtio-scsi-ccw",
+ .name = TYPE_VIRTIO_SCSI_CCW,
.parent = TYPE_VIRTIO_CCW_DEVICE,
- .instance_size = sizeof(VirtioCcwDevice),
+ .instance_size = sizeof(VirtIOSCSICcw),
+ .instance_init = virtio_ccw_scsi_instance_init,
.class_init = virtio_ccw_scsi_class_init,
};
@@ -982,7 +985,7 @@
qbus_create_inplace((BusState *)bus, TYPE_VIRTIO_CCW_BUS, qdev, NULL);
qbus = BUS(bus);
- qbus->allow_hotplug = 0;
+ qbus->allow_hotplug = 1;
}
static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data)
diff --git a/hw/s390x/virtio-ccw.h b/hw/s390x/virtio-ccw.h
index 88c46c0..d9f7399 100644
--- a/hw/s390x/virtio-ccw.h
+++ b/hw/s390x/virtio-ccw.h
@@ -72,12 +72,10 @@
SubchDev *sch;
VirtIODevice *vdev;
char *bus_id;
- VirtIOBlkConf blk;
NICConf nic;
uint32_t host_features[VIRTIO_CCW_FEATURE_SIZE];
virtio_serial_conf serial;
virtio_net_conf net;
- VirtIOSCSIConf scsi;
VirtIORNGConf rng;
VirtioBusState bus;
/* Guest provided values: */
@@ -94,6 +92,30 @@
#define VIRTUAL_CSS_BUS(obj) \
OBJECT_CHECK(VirtualCssBus, (obj), TYPE_VIRTUAL_CSS_BUS)
+/* virtio-scsi-ccw */
+
+#define TYPE_VIRTIO_SCSI_CCW "virtio-scsi-ccw"
+#define VIRTIO_SCSI_CCW(obj) \
+ OBJECT_CHECK(VirtIOSCSICcw, (obj), TYPE_VIRTIO_SCSI_CCW)
+
+typedef struct VirtIOSCSICcw {
+ VirtioCcwDevice parent_obj;
+ VirtIOSCSI vdev;
+} VirtIOSCSICcw;
+
+/* virtio-blk-ccw */
+
+#define TYPE_VIRTIO_BLK_CCW "virtio-blk-ccw"
+#define VIRTIO_BLK_CCW(obj) \
+ OBJECT_CHECK(VirtIOBlkCcw, (obj), TYPE_VIRTIO_BLK_CCW)
+
+typedef struct VirtIOBlkCcw {
+ VirtioCcwDevice parent_obj;
+ VirtIOBlock vdev;
+ VirtIOBlkConf blk;
+} VirtIOBlkCcw;
+
+
VirtualCssBus *virtual_css_bus_init(void);
void virtio_ccw_device_update_status(SubchDev *sch);
VirtIODevice *virtio_ccw_get_vdev(SubchDev *sch);
diff --git a/hw/sdhci.c b/hw/sdhci.c
index 93feada..4a29e6c 100644
--- a/hw/sdhci.c
+++ b/hw/sdhci.c
@@ -763,7 +763,7 @@
}
}
- /* we have unfinished bussiness - reschedule to continue ADMA */
+ /* we have unfinished business - reschedule to continue ADMA */
qemu_mod_timer(s->transfer_timer,
qemu_get_clock_ns(vm_clock) + SDHC_TRANSFER_DELAY);
}
diff --git a/hw/serial.c b/hw/serial.c
index 48a5eb6..0ccc499 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -306,7 +306,7 @@
SerialState *s = opaque;
addr &= 7;
- DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
+ DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
switch(addr) {
default:
case 0:
@@ -527,7 +527,7 @@
ret = s->scr;
break;
}
- DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
+ DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
return ret;
}
diff --git a/hw/sm501.c b/hw/sm501.c
index 0e01911..93a06c9 100644
--- a/hw/sm501.c
+++ b/hw/sm501.c
@@ -454,7 +454,7 @@
typedef struct SM501State {
/* graphic console status */
- DisplayState *ds;
+ QemuConsole *con;
/* status & internal resources */
hwaddr base;
@@ -1234,9 +1234,9 @@
draw_hwc_line_16bgr,
};
-static inline int get_depth_index(DisplayState *s)
+static inline int get_depth_index(DisplaySurface *surface)
{
- switch(ds_get_bits_per_pixel(s)) {
+ switch (surface_bits_per_pixel(surface)) {
default:
case 8:
return 0;
@@ -1245,26 +1245,28 @@
case 16:
return 2;
case 32:
- if (is_surface_bgr(s->surface))
- return 4;
- else
- return 3;
+ if (is_surface_bgr(surface)) {
+ return 4;
+ } else {
+ return 3;
+ }
}
}
static void sm501_draw_crt(SM501State * s)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int y;
int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
uint8_t * src = s->local_mem;
int src_bpp = 0;
- int dst_bpp = ds_get_bytes_per_pixel(s->ds) + (ds_get_bits_per_pixel(s->ds) % 8 ? 1 : 0);
+ int dst_bpp = surface_bytes_per_pixel(surface);
uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
- SM501_DC_PANEL_PALETTE];
uint8_t hwc_palette[3 * 3];
- int ds_depth_index = get_depth_index(s->ds);
+ int ds_depth_index = get_depth_index(surface);
draw_line_func * draw_line = NULL;
draw_hwc_line_func * draw_hwc_line = NULL;
int full_update = 0;
@@ -1312,7 +1314,8 @@
/* adjust console size */
if (s->last_width != width || s->last_height != height) {
- qemu_console_resize(s->ds, width, height);
+ qemu_console_resize(s->con, width, height);
+ surface = qemu_console_surface(s->con);
s->last_width = width;
s->last_height = height;
full_update = 1;
@@ -1331,7 +1334,8 @@
/* draw line and change status */
if (update) {
- uint8_t * d = &(ds_get_data(s->ds)[y * width * dst_bpp]);
+ uint8_t *d = surface_data(surface);
+ d += y * width * dst_bpp;
/* draw graphics layer */
draw_line(d, src, width, palette);
@@ -1350,7 +1354,7 @@
} else {
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(s->ds, 0, y_start, width, y - y_start);
+ dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
y_start = -1;
}
}
@@ -1361,7 +1365,7 @@
/* complete flush to display */
if (y_start >= 0)
- dpy_gfx_update(s->ds, 0, y_start, width, y - y_start);
+ dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
/* clear dirty flags */
if (page_min != ~0l) {
@@ -1441,6 +1445,6 @@
}
/* create qemu graphic console */
- s->ds = graphic_console_init(sm501_update_display, NULL,
- NULL, NULL, s);
+ s->con = graphic_console_init(sm501_update_display, NULL,
+ NULL, NULL, s);
}
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 20b9015..3e0d8d1 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -518,6 +518,7 @@
{
sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
PCIHostState *phb = PCI_HOST_BRIDGE(s);
+ const char *busname;
char *namebuf;
int i;
PCIBus *bus;
@@ -575,9 +576,6 @@
}
sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
- if (!sphb->busname) {
- sphb->busname = sphb->dtbusname;
- }
namebuf = alloca(strlen(sphb->dtbusname) + 32);
@@ -621,7 +619,26 @@
&sphb->msiwindow);
}
- bus = pci_register_bus(DEVICE(s), sphb->busname,
+ /*
+ * Selecting a busname is more complex than you'd think, due to
+ * interacting constraints. If the user has specified an id
+ * explicitly for the phb , then we want to use the qdev default
+ * of naming the bus based on the bridge device (so the user can
+ * then assign devices to it in the way they expect). For the
+ * first / default PCI bus (index=0) we want to use just "pci"
+ * because libvirt expects there to be a bus called, simply,
+ * "pci". Otherwise, we use the same name as in the device tree,
+ * since it's unique by construction, and makes the guest visible
+ * BUID clear.
+ */
+ if (s->qdev.id) {
+ busname = NULL;
+ } else if (sphb->index == 0) {
+ busname = "pci";
+ } else {
+ busname = sphb->dtbusname;
+ }
+ bus = pci_register_bus(DEVICE(s), busname,
pci_spapr_set_irq, pci_spapr_map_irq, sphb,
&sphb->memspace, &sphb->iospace,
PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
@@ -663,7 +680,6 @@
}
static Property spapr_phb_properties[] = {
- DEFINE_PROP_STRING("busname", sPAPRPHBState, busname),
DEFINE_PROP_INT32("index", sPAPRPHBState, index, -1),
DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, -1),
DEFINE_PROP_HEX32("liobn", sPAPRPHBState, dma_liobn, -1),
@@ -694,14 +710,12 @@
.class_init = spapr_phb_class_init,
};
-PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
- const char *busname)
+PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index)
{
DeviceState *dev;
dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "index", index);
- qdev_prop_set_string(dev, "busname", busname);
qdev_init_nofail(dev);
return PCI_HOST_BRIDGE(dev);
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index 8bb3c62..8bd8a66 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -39,7 +39,6 @@
int32_t index;
uint64_t buid;
- char *busname;
char *dtbusname;
MemoryRegion memspace, iospace;
@@ -82,8 +81,7 @@
return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
}
-PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index,
- const char *busname);
+PCIHostState *spapr_create_phb(sPAPREnvironment *spapr, int index);
int spapr_populate_pci_dt(sPAPRPHBState *phb,
uint32_t xics_phandle,
diff --git a/hw/ssd0303.c b/hw/ssd0303.c
index db50909..68d1f24 100644
--- a/hw/ssd0303.c
+++ b/hw/ssd0303.c
@@ -43,7 +43,7 @@
typedef struct {
I2CSlave i2c;
- DisplayState *ds;
+ QemuConsole *con;
int row;
int col;
int start_line;
@@ -191,6 +191,7 @@
static void ssd0303_update_display(void *opaque)
{
ssd0303_state *s = (ssd0303_state *)opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *dest;
uint8_t *src;
int x;
@@ -204,7 +205,7 @@
if (!s->redraw)
return;
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 15:
@@ -236,7 +237,7 @@
colors[0] = colortab + dest_width;
colors[1] = colortab;
}
- dest = ds_get_data(s->ds);
+ dest = surface_data(surface);
for (y = 0; y < 16; y++) {
line = (y + s->start_line) & 63;
src = s->framebuffer + 132 * (line >> 3) + 36;
@@ -252,7 +253,7 @@
}
}
s->redraw = 0;
- dpy_gfx_update(s->ds, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY);
+ dpy_gfx_update(s->con, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY);
}
static void ssd0303_invalidate_display(void * opaque)
@@ -287,10 +288,10 @@
{
ssd0303_state *s = FROM_I2C_SLAVE(ssd0303_state, i2c);
- s->ds = graphic_console_init(ssd0303_update_display,
- ssd0303_invalidate_display,
- NULL, NULL, s);
- qemu_console_resize(s->ds, 96 * MAGNIFY, 16 * MAGNIFY);
+ s->con = graphic_console_init(ssd0303_update_display,
+ ssd0303_invalidate_display,
+ NULL, NULL, s);
+ qemu_console_resize(s->con, 96 * MAGNIFY, 16 * MAGNIFY);
return 0;
}
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index 27b4151..5cf2f70 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -45,7 +45,7 @@
typedef struct {
SSISlave ssidev;
- DisplayState *ds;
+ QemuConsole *con;
int cmd_len;
int cmd;
@@ -175,6 +175,7 @@
static void ssd0323_update_display(void *opaque)
{
ssd0323_state *s = (ssd0323_state *)opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *dest;
uint8_t *src;
int x;
@@ -189,7 +190,7 @@
if (!s->redraw)
return;
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 15:
@@ -212,7 +213,7 @@
for (i = 0; i < 16; i++) {
int n;
colors[i] = p;
- switch (ds_get_bits_per_pixel(s->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 15:
n = i * 2 + (i >> 3);
p[0] = n | (n << 5);
@@ -235,7 +236,7 @@
p += dest_width;
}
/* TODO: Implement row/column remapping. */
- dest = ds_get_data(s->ds);
+ dest = surface_data(surface);
for (y = 0; y < 64; y++) {
line = y;
src = s->framebuffer + 64 * line;
@@ -260,7 +261,7 @@
}
}
s->redraw = 0;
- dpy_gfx_update(s->ds, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
+ dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
}
static void ssd0323_invalidate_display(void * opaque)
@@ -336,10 +337,10 @@
s->col_end = 63;
s->row_end = 79;
- s->ds = graphic_console_init(ssd0323_update_display,
- ssd0323_invalidate_display,
- NULL, NULL, s);
- qemu_console_resize(s->ds, 128 * MAGNIFY, 64 * MAGNIFY);
+ s->con = graphic_console_init(ssd0323_update_display,
+ ssd0323_invalidate_display,
+ NULL, NULL, s);
+ qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY);
qdev_init_gpio_in(&dev->qdev, ssd0323_cd, 1);
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index 0755463..79c971b 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -125,7 +125,7 @@
DeviceState *flash;
ECCState ecc;
- DisplayState *ds;
+ QemuConsole *con;
MemoryRegion vram;
uint16_t *vram_ptr;
uint32_t scr_width, scr_height; /* in pixels */
@@ -433,7 +433,9 @@
static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
{
- switch (ds_get_bits_per_pixel(s->ds)) {
+ DisplaySurface *surface = qemu_console_surface(s->con);
+
+ switch (surface_bits_per_pixel(surface)) {
case 8:
tc6393xb_draw_graphic8(s);
break;
@@ -450,34 +452,37 @@
tc6393xb_draw_graphic32(s);
break;
default:
- printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
+ printf("tc6393xb: unknown depth %d\n",
+ surface_bits_per_pixel(surface));
return;
}
- dpy_gfx_update(s->ds, 0, 0, s->scr_width, s->scr_height);
+ dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
}
static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i, w;
uint8_t *d;
if (!full_update)
return;
- w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
- d = ds_get_data(s->ds);
+ w = s->scr_width * surface_bytes_per_pixel(surface);
+ d = surface_data(surface);
for(i = 0; i < s->scr_height; i++) {
memset(d, 0, w);
- d += ds_get_linesize(s->ds);
+ d += surface_stride(surface);
}
- dpy_gfx_update(s->ds, 0, 0, s->scr_width, s->scr_height);
+ dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
}
static void tc6393xb_update_display(void *opaque)
{
TC6393xbState *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
int full_update;
if (s->scr_width == 0 || s->scr_height == 0)
@@ -488,8 +493,9 @@
s->blanked = s->blank;
full_update = 1;
}
- if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
- qemu_console_resize(s->ds, s->scr_width, s->scr_height);
+ if (s->scr_width != surface_width(surface) ||
+ s->scr_height != surface_height(surface)) {
+ qemu_console_resize(s->con, s->scr_width, s->scr_height);
full_update = 1;
}
if (s->blanked)
@@ -577,7 +583,7 @@
memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
s->scr_width = 480;
s->scr_height = 640;
- s->ds = graphic_console_init(tc6393xb_update_display,
+ s->con = graphic_console_init(tc6393xb_update_display,
NULL, /* invalidate */
NULL, /* screen_dump */
NULL, /* text_update */
diff --git a/hw/tc6393xb_template.h b/hw/tc6393xb_template.h
index 4cbbad5..154aafd 100644
--- a/hw/tc6393xb_template.h
+++ b/hw/tc6393xb_template.h
@@ -37,17 +37,18 @@
static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i;
uint16_t *data_buffer;
uint8_t *data_display;
data_buffer = s->vram_ptr;
- data_display = ds_get_data(s->ds);
+ data_display = surface_data(surface);
for(i = 0; i < s->scr_height; i++) {
#if (BITS == 16)
memcpy(data_display, data_buffer, s->scr_width * 2);
data_buffer += s->scr_width;
- data_display += ds_get_linesize(s->ds);
+ data_display += surface_stride(surface);
#else
int j;
for (j = 0; j < s->scr_width; j++, data_display += BITS / 8, data_buffer++) {
diff --git a/hw/tcx.c b/hw/tcx.c
index 896407d..f1edffd 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -38,7 +38,7 @@
typedef struct TCXState {
SysBusDevice busdev;
hwaddr addr;
- DisplayState *ds;
+ QemuConsole *con;
uint8_t *vram;
uint32_t *vram24, *cplane;
MemoryRegion vram_mem;
@@ -75,9 +75,11 @@
static void update_palette_entries(TCXState *s, int start, int end)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i;
- for(i = start; i < end; i++) {
- switch(ds_get_bits_per_pixel(s->ds)) {
+
+ for (i = start; i < end; i++) {
+ switch (surface_bits_per_pixel(surface)) {
default:
case 8:
s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
@@ -89,10 +91,11 @@
s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
break;
case 32:
- if (is_surface_bgr(s->ds->surface))
+ if (is_surface_bgr(surface)) {
s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
- else
+ } else {
s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
+ }
break;
}
}
@@ -151,12 +154,13 @@
const uint32_t *cplane,
const uint32_t *s24)
{
+ DisplaySurface *surface = qemu_console_surface(s1->con);
int x, bgr, r, g, b;
uint8_t val, *p8;
uint32_t *p = (uint32_t *)d;
uint32_t dval;
- bgr = is_surface_bgr(s1->ds->surface);
+ bgr = is_surface_bgr(surface);
for(x = 0; x < width; x++, s++, s24++) {
if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
// 24-bit direct, BGR order
@@ -213,23 +217,26 @@
static void tcx_update_display(void *opaque)
{
TCXState *ts = opaque;
+ DisplaySurface *surface = qemu_console_surface(ts->con);
ram_addr_t page, page_min, page_max;
int y, y_start, dd, ds;
uint8_t *d, *s;
void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
- if (ds_get_bits_per_pixel(ts->ds) == 0)
+ if (surface_bits_per_pixel(surface) == 0) {
return;
+ }
+
page = 0;
y_start = -1;
page_min = -1;
page_max = 0;
- d = ds_get_data(ts->ds);
+ d = surface_data(surface);
s = ts->vram;
- dd = ds_get_linesize(ts->ds);
+ dd = surface_stride(surface);
ds = 1024;
- switch (ds_get_bits_per_pixel(ts->ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 32:
f = tcx_draw_line32;
break;
@@ -269,7 +276,7 @@
} else {
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(ts->ds, 0, y_start,
+ dpy_gfx_update(ts->con, 0, y_start,
ts->width, y - y_start);
y_start = -1;
}
@@ -279,7 +286,7 @@
}
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(ts->ds, 0, y_start,
+ dpy_gfx_update(ts->con, 0, y_start,
ts->width, y - y_start);
}
/* reset modified pages */
@@ -293,24 +300,27 @@
static void tcx24_update_display(void *opaque)
{
TCXState *ts = opaque;
+ DisplaySurface *surface = qemu_console_surface(ts->con);
ram_addr_t page, page_min, page_max, cpage, page24;
int y, y_start, dd, ds;
uint8_t *d, *s;
uint32_t *cptr, *s24;
- if (ds_get_bits_per_pixel(ts->ds) != 32)
+ if (surface_bits_per_pixel(surface) != 32) {
return;
+ }
+
page = 0;
page24 = ts->vram24_offset;
cpage = ts->cplane_offset;
y_start = -1;
page_min = -1;
page_max = 0;
- d = ds_get_data(ts->ds);
+ d = surface_data(surface);
s = ts->vram;
s24 = ts->vram24;
cptr = ts->cplane;
- dd = ds_get_linesize(ts->ds);
+ dd = surface_stride(surface);
ds = 1024;
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
@@ -345,7 +355,7 @@
} else {
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(ts->ds, 0, y_start,
+ dpy_gfx_update(ts->con, 0, y_start,
ts->width, y - y_start);
y_start = -1;
}
@@ -357,7 +367,7 @@
}
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(ts->ds, 0, y_start,
+ dpy_gfx_update(ts->con, 0, y_start,
ts->width, y - y_start);
}
/* reset modified pages */
@@ -371,7 +381,7 @@
TCXState *s = opaque;
tcx_set_dirty(s);
- qemu_console_resize(s->ds, s->width, s->height);
+ qemu_console_resize(s->con, s->width, s->height);
}
static void tcx24_invalidate_display(void *opaque)
@@ -380,7 +390,7 @@
tcx_set_dirty(s);
tcx24_set_dirty(s);
- qemu_console_resize(s->ds, s->width, s->height);
+ qemu_console_resize(s->con, s->width, s->height);
}
static int vmstate_tcx_post_load(void *opaque, int version_id)
@@ -558,21 +568,21 @@
&s->vram_mem, vram_offset, size);
sysbus_init_mmio(dev, &s->vram_cplane);
- s->ds = graphic_console_init(tcx24_update_display,
- tcx24_invalidate_display,
- tcx24_screen_dump, NULL, s);
+ s->con = graphic_console_init(tcx24_update_display,
+ tcx24_invalidate_display,
+ tcx24_screen_dump, NULL, s);
} else {
/* THC 8 bit (dummy) */
memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
TCX_THC_NREGS_8);
sysbus_init_mmio(dev, &s->thc8);
- s->ds = graphic_console_init(tcx_update_display,
- tcx_invalidate_display,
- tcx_screen_dump, NULL, s);
+ s->con = graphic_console_init(tcx_update_display,
+ tcx_invalidate_display,
+ tcx_screen_dump, NULL, s);
}
- qemu_console_resize(s->ds, s->width, s->height);
+ qemu_console_resize(s->con, s->width, s->height);
return 0;
}
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 4aa62bf..02356d4 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -135,8 +135,9 @@
vga_common_init(&s->vga);
vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
- s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
- s->vga.screen_dump, s->vga.text_update, s);
+ s->vga.con = graphic_console_init(s->vga.update, s->vga.invalidate,
+ s->vga.screen_dump, s->vga.text_update,
+ s);
vga_init_vbe(&s->vga, address_space);
return 0;
diff --git a/hw/vga-isa.c b/hw/vga-isa.c
index ffad522..9e29321 100644
--- a/hw/vga-isa.c
+++ b/hw/vga-isa.c
@@ -62,8 +62,8 @@
isa_mem_base + 0x000a0000,
vga_io_memory, 1);
memory_region_set_coalescing(vga_io_memory);
- s->ds = graphic_console_init(s->update, s->invalidate,
- s->screen_dump, s->text_update, s);
+ s->con = graphic_console_init(s->update, s->invalidate,
+ s->screen_dump, s->text_update, s);
vga_init_vbe(s, isa_address_space(dev));
/* ROM BIOS */
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index 18018ff..05fa9bc 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -150,8 +150,8 @@
vga_common_init(s);
vga_init(s, pci_address_space(dev), pci_address_space_io(dev), true);
- s->ds = graphic_console_init(s->update, s->invalidate,
- s->screen_dump, s->text_update, s);
+ s->con = graphic_console_init(s->update, s->invalidate,
+ s->screen_dump, s->text_update, s);
/* XXX: VGA_RAM_SIZE must be a power of two */
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
diff --git a/hw/vga.c b/hw/vga.c
index 2213bc1..59bfb22 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -1174,9 +1174,9 @@
#define NB_DEPTHS 7
-static inline int get_depth_index(DisplayState *s)
+static inline int get_depth_index(DisplaySurface *s)
{
- switch(ds_get_bits_per_pixel(s)) {
+ switch (surface_bits_per_pixel(s)) {
default:
case 8:
return 0;
@@ -1185,10 +1185,11 @@
case 16:
return 2;
case 32:
- if (is_surface_bgr(s->surface))
+ if (is_surface_bgr(s)) {
return 4;
- else
+ } else {
return 3;
+ }
}
}
@@ -1294,6 +1295,7 @@
*/
static void vga_draw_text(VGACommonState *s, int full_update)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
int cx_min, cx_max, linesize, x_incr, line, line1;
uint32_t offset, fgcol, bgcol, v, cursor_offset;
@@ -1345,8 +1347,9 @@
cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
s->last_scr_width = width * cw;
s->last_scr_height = height * cheight;
- qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
- dpy_text_resize(s->ds, width, height);
+ qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
+ surface = qemu_console_surface(s->con);
+ dpy_text_resize(s->con, width, height);
s->last_depth = 0;
s->last_width = width;
s->last_height = height;
@@ -1355,10 +1358,10 @@
full_update = 1;
}
s->rgb_to_pixel =
- rgb_to_pixel_dup_table[get_depth_index(s->ds)];
+ rgb_to_pixel_dup_table[get_depth_index(surface)];
full_update |= update_palette16(s);
palette = s->last_palette;
- x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
+ x_incr = cw * surface_bytes_per_pixel(surface);
if (full_update) {
s->full_update_text = 1;
@@ -1389,15 +1392,15 @@
s->cursor_visible_phase = !s->cursor_visible_phase;
}
- depth_index = get_depth_index(s->ds);
+ depth_index = get_depth_index(surface);
if (cw == 16)
vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
else
vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
- dest = ds_get_data(s->ds);
- linesize = ds_get_linesize(s->ds);
+ dest = surface_data(surface);
+ linesize = surface_stride(surface);
ch_attr_ptr = s->last_ch_attr;
line = 0;
offset = s->start_addr * 4;
@@ -1465,7 +1468,7 @@
ch_attr_ptr++;
}
if (cx_max != -1) {
- dpy_gfx_update(s->ds, cx_min * cw, cy * cheight,
+ dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
(cx_max - cx_min + 1) * cw, cheight);
}
dest += linesize * cheight;
@@ -1636,6 +1639,7 @@
*/
static void vga_draw_graphic(VGACommonState *s, int full_update)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int y1, y, update, linesize, y_start, double_scan, mask, depth;
int width, height, shift_control, line_offset, bwidth, bits;
ram_addr_t page0, page1, page_min, page_max;
@@ -1691,13 +1695,13 @@
height != s->last_height ||
s->last_depth != depth) {
if (depth == 32 || (depth == 16 && !byteswap)) {
- qemu_free_displaysurface(s->ds);
- s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
- s->line_offset,
+ surface = qemu_create_displaysurface_from(disp_width,
+ height, depth, s->line_offset,
s->vram_ptr + (s->start_addr * 4), byteswap);
- dpy_gfx_resize(s->ds);
+ dpy_gfx_replace_surface(s->con, surface);
} else {
- qemu_console_resize(s->ds, disp_width, height);
+ qemu_console_resize(s->con, disp_width, height);
+ surface = qemu_console_surface(s->con);
}
s->last_scr_width = disp_width;
s->last_scr_height = height;
@@ -1706,19 +1710,18 @@
s->last_line_offset = s->line_offset;
s->last_depth = depth;
full_update = 1;
- } else if (is_buffer_shared(s->ds->surface) &&
- (full_update || ds_get_data(s->ds) != s->vram_ptr
+ } else if (is_buffer_shared(surface) &&
+ (full_update || surface_data(surface) != s->vram_ptr
+ (s->start_addr * 4))) {
- qemu_free_displaysurface(s->ds);
- s->ds->surface = qemu_create_displaysurface_from(disp_width,
- height, depth,
- s->line_offset,
+ DisplaySurface *surface;
+ surface = qemu_create_displaysurface_from(disp_width,
+ height, depth, s->line_offset,
s->vram_ptr + (s->start_addr * 4), byteswap);
- dpy_gfx_setdata(s->ds);
+ dpy_gfx_replace_surface(s->con, surface);
}
s->rgb_to_pixel =
- rgb_to_pixel_dup_table[get_depth_index(s->ds)];
+ rgb_to_pixel_dup_table[get_depth_index(surface)];
if (shift_control == 0) {
full_update |= update_palette16(s);
@@ -1767,10 +1770,12 @@
break;
}
}
- vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
+ vga_draw_line = vga_draw_line_table[v * NB_DEPTHS +
+ get_depth_index(surface)];
- if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
+ if (!is_buffer_shared(surface) && s->cursor_invalidate) {
s->cursor_invalidate(s);
+ }
line_offset = s->line_offset;
#if 0
@@ -1783,8 +1788,8 @@
y_start = -1;
page_min = -1;
page_max = 0;
- d = ds_get_data(s->ds);
- linesize = ds_get_linesize(s->ds);
+ d = surface_data(surface);
+ linesize = surface_stride(surface);
y1 = 0;
for(y = 0; y < height; y++) {
addr = addr1;
@@ -1811,7 +1816,7 @@
page_min = page0;
if (page1 > page_max)
page_max = page1;
- if (!(is_buffer_shared(s->ds->surface))) {
+ if (!(is_buffer_shared(surface))) {
vga_draw_line(s, d, s->vram_ptr + addr, width);
if (s->cursor_draw_line)
s->cursor_draw_line(s, d, y);
@@ -1819,7 +1824,7 @@
} else {
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(s->ds, 0, y_start,
+ dpy_gfx_update(s->con, 0, y_start,
disp_width, y - y_start);
y_start = -1;
}
@@ -1840,7 +1845,7 @@
}
if (y_start >= 0) {
/* flush to display */
- dpy_gfx_update(s->ds, 0, y_start,
+ dpy_gfx_update(s->con, 0, y_start,
disp_width, y - y_start);
}
/* reset modified pages */
@@ -1855,6 +1860,7 @@
static void vga_draw_blank(VGACommonState *s, int full_update)
{
+ DisplaySurface *surface = qemu_console_surface(s->con);
int i, w, val;
uint8_t *d;
@@ -1864,18 +1870,19 @@
return;
s->rgb_to_pixel =
- rgb_to_pixel_dup_table[get_depth_index(s->ds)];
- if (ds_get_bits_per_pixel(s->ds) == 8)
+ rgb_to_pixel_dup_table[get_depth_index(surface)];
+ if (surface_bits_per_pixel(surface) == 8) {
val = s->rgb_to_pixel(0, 0, 0);
- else
+ } else {
val = 0;
- w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
- d = ds_get_data(s->ds);
+ }
+ w = s->last_scr_width * surface_bytes_per_pixel(surface);
+ d = surface_data(surface);
for(i = 0; i < s->last_scr_height; i++) {
memset(d, val, w);
- d += ds_get_linesize(s->ds);
+ d += surface_stride(surface);
}
- dpy_gfx_update(s->ds, 0, 0,
+ dpy_gfx_update(s->con, 0, 0,
s->last_scr_width, s->last_scr_height);
}
@@ -1886,11 +1893,12 @@
static void vga_update_display(void *opaque)
{
VGACommonState *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
int full_update, graphic_mode;
qemu_flush_coalesced_mmio_buffer();
- if (ds_get_bits_per_pixel(s->ds) == 0) {
+ if (surface_bits_per_pixel(surface) == 0) {
/* nothing to do */
} else {
full_update = 0;
@@ -2064,8 +2072,8 @@
cw != s->last_cw || cheight != s->last_ch) {
s->last_scr_width = width * cw;
s->last_scr_height = height * cheight;
- qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
- dpy_text_resize(s->ds, width, height);
+ qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
+ dpy_text_resize(s->con, width, height);
s->last_depth = 0;
s->last_width = width;
s->last_height = height;
@@ -2090,11 +2098,11 @@
s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
- dpy_text_cursor(s->ds,
+ dpy_text_cursor(s->con,
TEXTMODE_X(cursor_offset),
TEXTMODE_Y(cursor_offset));
else
- dpy_text_cursor(s->ds, -1, -1);
+ dpy_text_cursor(s->con, -1, -1);
s->cursor_offset = cursor_offset;
s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
@@ -2107,7 +2115,7 @@
for (i = 0; i < size; src ++, dst ++, i ++)
console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
- dpy_text_update(s->ds, 0, 0, width, height);
+ dpy_text_update(s->con, 0, 0, width, height);
} else {
c_max = 0;
@@ -2130,7 +2138,7 @@
if (c_min <= c_max) {
i = TEXTMODE_Y(c_min);
- dpy_text_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
+ dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
}
}
@@ -2155,8 +2163,8 @@
/* Display a message */
s->last_width = 60;
s->last_height = height = 3;
- dpy_text_cursor(s->ds, -1, -1);
- dpy_text_resize(s->ds, s->last_width, height);
+ dpy_text_cursor(s->con, -1, -1);
+ dpy_text_resize(s->con, s->last_width, height);
for (dst = chardata, i = 0; i < s->last_width * height; i ++)
console_write_ch(dst ++, ' ');
@@ -2167,7 +2175,7 @@
for (i = 0; i < size; i ++)
console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
- dpy_text_update(s->ds, 0, 0, s->last_width, height);
+ dpy_text_update(s->con, 0, 0, s->last_width, height);
}
static uint64_t vga_mem_read(void *opaque, hwaddr addr,
@@ -2439,10 +2447,11 @@
Error **errp)
{
VGACommonState *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
if (cswitch) {
vga_invalidate_display(s);
}
vga_hw_update();
- ppm_save(filename, s->ds->surface, errp);
+ ppm_save(filename, surface, errp);
}
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 8d496ea..260f7d6 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -132,7 +132,7 @@
uint32_t vbe_bank_mask;
int vbe_mapped;
/* display refresh support */
- DisplayState *ds;
+ QemuConsole *con;
uint32_t font_offsets[2];
int graphic_mode;
uint8_t shift_control;
diff --git a/hw/virtio-balloon.c b/hw/virtio-balloon.c
index 6bfcddc..54a4372 100644
--- a/hw/virtio-balloon.c
+++ b/hw/virtio-balloon.c
@@ -29,21 +29,6 @@
#include <sys/mman.h>
#endif
-typedef struct VirtIOBalloon
-{
- VirtIODevice vdev;
- VirtQueue *ivq, *dvq, *svq;
- uint32_t num_pages;
- uint32_t actual;
- uint64_t stats[VIRTIO_BALLOON_S_NR];
- VirtQueueElement stats_vq_elem;
- size_t stats_vq_offset;
- QEMUTimer *stats_timer;
- int64_t stats_last_update;
- int64_t stats_poll_interval;
- DeviceState *qdev;
-} VirtIOBalloon;
-
static VirtIOBalloon *to_virtio_balloon(VirtIODevice *vdev)
{
return (VirtIOBalloon *)vdev;
diff --git a/hw/virtio-balloon.h b/hw/virtio-balloon.h
index f37f31b..b007042 100644
--- a/hw/virtio-balloon.h
+++ b/hw/virtio-balloon.h
@@ -52,4 +52,18 @@
uint64_t val;
} QEMU_PACKED VirtIOBalloonStat;
+typedef struct VirtIOBalloon {
+ VirtIODevice vdev;
+ VirtQueue *ivq, *dvq, *svq;
+ uint32_t num_pages;
+ uint32_t actual;
+ uint64_t stats[VIRTIO_BALLOON_S_NR];
+ VirtQueueElement stats_vq_elem;
+ size_t stats_vq_offset;
+ QEMUTimer *stats_timer;
+ int64_t stats_last_update;
+ int64_t stats_poll_interval;
+ DeviceState *qdev;
+} VirtIOBalloon;
+
#endif
diff --git a/hw/virtio-blk.c b/hw/virtio-blk.c
index 6b69236..f2143fd 100644
--- a/hw/virtio-blk.c
+++ b/hw/virtio-blk.c
@@ -17,35 +17,11 @@
#include "hw/block-common.h"
#include "sysemu/blockdev.h"
#include "hw/virtio-blk.h"
-#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
-#include "dataplane/virtio-blk.h"
-#endif
#include "hw/scsi-defs.h"
#ifdef __linux__
# include <scsi/sg.h>
#endif
-
-typedef struct VirtIOBlock
-{
- VirtIODevice vdev;
- BlockDriverState *bs;
- VirtQueue *vq;
- void *rq;
- QEMUBH *bh;
- BlockConf *conf;
- VirtIOBlkConf *blk;
- unsigned short sector_mask;
- DeviceState *qdev;
- VMChangeStateEntry *change;
-#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
- VirtIOBlockDataPlane *dataplane;
-#endif
-} VirtIOBlock;
-
-static VirtIOBlock *to_virtio_blk(VirtIODevice *vdev)
-{
- return (VirtIOBlock *)vdev;
-}
+#include "hw/virtio-bus.h"
typedef struct VirtIOBlockReq
{
@@ -62,12 +38,13 @@
static void virtio_blk_req_complete(VirtIOBlockReq *req, int status)
{
VirtIOBlock *s = req->dev;
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
trace_virtio_blk_req_complete(req, status);
stb_p(&req->in->status, status);
virtqueue_push(s->vq, &req->elem, req->qiov.size + sizeof(*req->in));
- virtio_notify(&s->vdev, s->vq);
+ virtio_notify(vdev, s->vq);
}
static int virtio_blk_handle_rw_error(VirtIOBlockReq *req, int error,
@@ -171,7 +148,7 @@
*/
req->scsi = (void *)req->elem.in_sg[req->elem.in_num - 2].iov_base;
- if (!req->dev->blk->scsi) {
+ if (!req->dev->blk.scsi) {
status = VIRTIO_BLK_S_UNSUPP;
goto fail;
}
@@ -391,7 +368,7 @@
* terminated by '\0' only when shorter than buffer.
*/
strncpy(req->elem.in_sg[0].iov_base,
- s->blk->serial ? s->blk->serial : "",
+ s->blk.serial ? s->blk.serial : "",
MIN(req->elem.in_sg[0].iov_len, VIRTIO_BLK_ID_BYTES));
virtio_blk_req_complete(req, VIRTIO_BLK_S_OK);
g_free(req);
@@ -412,7 +389,7 @@
static void virtio_blk_handle_output(VirtIODevice *vdev, VirtQueue *vq)
{
- VirtIOBlock *s = to_virtio_blk(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
VirtIOBlockReq *req;
MultiReqBuffer mrb = {
.num_writes = 0,
@@ -480,7 +457,7 @@
static void virtio_blk_reset(VirtIODevice *vdev)
{
#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
- VirtIOBlock *s = to_virtio_blk(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
if (s->dataplane) {
virtio_blk_data_plane_stop(s->dataplane);
@@ -498,7 +475,7 @@
*/
static void virtio_blk_update_config(VirtIODevice *vdev, uint8_t *config)
{
- VirtIOBlock *s = to_virtio_blk(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
struct virtio_blk_config blkcfg;
uint64_t capacity;
int blk_size = s->conf->logical_block_size;
@@ -537,7 +514,7 @@
static void virtio_blk_set_config(VirtIODevice *vdev, const uint8_t *config)
{
- VirtIOBlock *s = to_virtio_blk(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
struct virtio_blk_config blkcfg;
memcpy(&blkcfg, config, sizeof(blkcfg));
@@ -546,7 +523,7 @@
static uint32_t virtio_blk_get_features(VirtIODevice *vdev, uint32_t features)
{
- VirtIOBlock *s = to_virtio_blk(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
features |= (1 << VIRTIO_BLK_F_SEG_MAX);
features |= (1 << VIRTIO_BLK_F_GEOMETRY);
@@ -554,7 +531,7 @@
features |= (1 << VIRTIO_BLK_F_BLK_SIZE);
features |= (1 << VIRTIO_BLK_F_SCSI);
- if (s->blk->config_wce) {
+ if (s->blk.config_wce) {
features |= (1 << VIRTIO_BLK_F_CONFIG_WCE);
}
if (bdrv_enable_write_cache(s->bs))
@@ -568,7 +545,7 @@
static void virtio_blk_set_status(VirtIODevice *vdev, uint8_t status)
{
- VirtIOBlock *s = to_virtio_blk(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
uint32_t features;
#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
@@ -589,9 +566,10 @@
static void virtio_blk_save(QEMUFile *f, void *opaque)
{
VirtIOBlock *s = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
VirtIOBlockReq *req = s->rq;
- virtio_save(&s->vdev, f);
+ virtio_save(vdev, f);
while (req) {
qemu_put_sbyte(f, 1);
@@ -604,12 +582,13 @@
static int virtio_blk_load(QEMUFile *f, void *opaque, int version_id)
{
VirtIOBlock *s = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
int ret;
if (version_id != 2)
return -EINVAL;
- ret = virtio_load(&s->vdev, f);
+ ret = virtio_load(vdev, f);
if (ret) {
return ret;
}
@@ -631,80 +610,120 @@
static void virtio_blk_resize(void *opaque)
{
- VirtIOBlock *s = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(opaque);
- virtio_notify_config(&s->vdev);
+ virtio_notify_config(vdev);
}
static const BlockDevOps virtio_block_ops = {
.resize_cb = virtio_blk_resize,
};
-VirtIODevice *virtio_blk_init(DeviceState *dev, VirtIOBlkConf *blk)
+void virtio_blk_set_conf(DeviceState *dev, VirtIOBlkConf *blk)
{
- VirtIOBlock *s;
+ VirtIOBlock *s = VIRTIO_BLK(dev);
+ memcpy(&(s->blk), blk, sizeof(struct VirtIOBlkConf));
+}
+
+static int virtio_blk_device_init(VirtIODevice *vdev)
+{
+ DeviceState *qdev = DEVICE(vdev);
+ VirtIOBlock *s = VIRTIO_BLK(vdev);
+ VirtIOBlkConf *blk = &(s->blk);
static int virtio_blk_id;
if (!blk->conf.bs) {
error_report("drive property not set");
- return NULL;
+ return -1;
}
if (!bdrv_is_inserted(blk->conf.bs)) {
error_report("Device needs media, but drive is empty");
- return NULL;
+ return -1;
}
blkconf_serial(&blk->conf, &blk->serial);
if (blkconf_geometry(&blk->conf, NULL, 65535, 255, 255) < 0) {
- return NULL;
+ return -1;
}
- s = (VirtIOBlock *)virtio_common_init("virtio-blk", VIRTIO_ID_BLOCK,
- sizeof(struct virtio_blk_config),
- sizeof(VirtIOBlock));
+ virtio_init(vdev, "virtio-blk", VIRTIO_ID_BLOCK,
+ sizeof(struct virtio_blk_config));
- s->vdev.get_config = virtio_blk_update_config;
- s->vdev.set_config = virtio_blk_set_config;
- s->vdev.get_features = virtio_blk_get_features;
- s->vdev.set_status = virtio_blk_set_status;
- s->vdev.reset = virtio_blk_reset;
+ vdev->get_config = virtio_blk_update_config;
+ vdev->set_config = virtio_blk_set_config;
+ vdev->get_features = virtio_blk_get_features;
+ vdev->set_status = virtio_blk_set_status;
+ vdev->reset = virtio_blk_reset;
s->bs = blk->conf.bs;
s->conf = &blk->conf;
- s->blk = blk;
+ memcpy(&(s->blk), blk, sizeof(struct VirtIOBlkConf));
s->rq = NULL;
s->sector_mask = (s->conf->logical_block_size / BDRV_SECTOR_SIZE) - 1;
- s->vq = virtio_add_queue(&s->vdev, 128, virtio_blk_handle_output);
+ s->vq = virtio_add_queue(vdev, 128, virtio_blk_handle_output);
#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
- if (!virtio_blk_data_plane_create(&s->vdev, blk, &s->dataplane)) {
- virtio_cleanup(&s->vdev);
- return NULL;
+ if (!virtio_blk_data_plane_create(vdev, blk, &s->dataplane)) {
+ virtio_common_cleanup(vdev);
+ return -1;
}
#endif
s->change = qemu_add_vm_change_state_handler(virtio_blk_dma_restart_cb, s);
- s->qdev = dev;
- register_savevm(dev, "virtio-blk", virtio_blk_id++, 2,
+ register_savevm(qdev, "virtio-blk", virtio_blk_id++, 2,
virtio_blk_save, virtio_blk_load, s);
bdrv_set_dev_ops(s->bs, &virtio_block_ops, s);
bdrv_set_buffer_alignment(s->bs, s->conf->logical_block_size);
bdrv_iostatus_enable(s->bs);
- add_boot_device_path(s->conf->bootindex, dev, "/disk@0,0");
- return &s->vdev;
+ add_boot_device_path(s->conf->bootindex, qdev, "/disk@0,0");
+ return 0;
}
-void virtio_blk_exit(VirtIODevice *vdev)
+static int virtio_blk_device_exit(DeviceState *dev)
{
- VirtIOBlock *s = to_virtio_blk(vdev);
-
+ VirtIODevice *vdev = VIRTIO_DEVICE(dev);
+ VirtIOBlock *s = VIRTIO_BLK(dev);
#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
virtio_blk_data_plane_destroy(s->dataplane);
s->dataplane = NULL;
#endif
qemu_del_vm_change_state_handler(s->change);
- unregister_savevm(s->qdev, "virtio-blk", s);
+ unregister_savevm(dev, "virtio-blk", s);
blockdev_mark_auto_del(s->bs);
- virtio_cleanup(vdev);
+ virtio_common_cleanup(vdev);
+ return 0;
}
+
+static Property virtio_blk_properties[] = {
+ DEFINE_VIRTIO_BLK_PROPERTIES(VirtIOBlock, blk),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void virtio_blk_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
+ dc->exit = virtio_blk_device_exit;
+ dc->props = virtio_blk_properties;
+ vdc->init = virtio_blk_device_init;
+ vdc->get_config = virtio_blk_update_config;
+ vdc->set_config = virtio_blk_set_config;
+ vdc->get_features = virtio_blk_get_features;
+ vdc->set_status = virtio_blk_set_status;
+ vdc->reset = virtio_blk_reset;
+}
+
+static const TypeInfo virtio_device_info = {
+ .name = TYPE_VIRTIO_BLK,
+ .parent = TYPE_VIRTIO_DEVICE,
+ .instance_size = sizeof(VirtIOBlock),
+ .class_init = virtio_blk_class_init,
+};
+
+static void virtio_register_types(void)
+{
+ type_register_static(&virtio_device_info);
+}
+
+type_init(virtio_register_types)
diff --git a/hw/virtio-blk.h b/hw/virtio-blk.h
index 7ef2f35..8c6c78b 100644
--- a/hw/virtio-blk.h
+++ b/hw/virtio-blk.h
@@ -16,6 +16,13 @@
#include "hw/virtio.h"
#include "hw/block-common.h"
+#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
+#include "dataplane/virtio-blk.h"
+#endif
+
+#define TYPE_VIRTIO_BLK "virtio-blk"
+#define VIRTIO_BLK(obj) \
+ OBJECT_CHECK(VirtIOBlock, (obj), TYPE_VIRTIO_BLK)
/* from Linux's linux/virtio_blk.h */
@@ -108,7 +115,39 @@
uint32_t data_plane;
};
+typedef struct VirtIOBlock {
+ VirtIODevice parent_obj;
+ BlockDriverState *bs;
+ VirtQueue *vq;
+ void *rq;
+ QEMUBH *bh;
+ BlockConf *conf;
+ VirtIOBlkConf blk;
+ unsigned short sector_mask;
+ VMChangeStateEntry *change;
+#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
+ VirtIOBlockDataPlane *dataplane;
+#endif
+} VirtIOBlock;
+
#define DEFINE_VIRTIO_BLK_FEATURES(_state, _field) \
DEFINE_VIRTIO_COMMON_FEATURES(_state, _field)
+#ifdef __linux__
+#define DEFINE_VIRTIO_BLK_PROPERTIES(_state, _field) \
+ DEFINE_BLOCK_PROPERTIES(_state, _field.conf), \
+ DEFINE_BLOCK_CHS_PROPERTIES(_state, _field.conf), \
+ DEFINE_PROP_STRING("serial", _state, _field.serial), \
+ DEFINE_PROP_BIT("config-wce", _state, _field.config_wce, 0, true), \
+ DEFINE_PROP_BIT("scsi", _state, _field.scsi, 0, true)
+#else
+#define DEFINE_VIRTIO_BLK_PROPERTIES(_state, _field) \
+ DEFINE_BLOCK_PROPERTIES(_state, _field.conf), \
+ DEFINE_BLOCK_CHS_PROPERTIES(_state, _field.conf), \
+ DEFINE_PROP_STRING("serial", _state, _field.serial), \
+ DEFINE_PROP_BIT("config-wce", _state, _field.config_wce, 0, true)
+#endif /* __linux__ */
+
+void virtio_blk_set_conf(DeviceState *dev, VirtIOBlkConf *blk);
+
#endif
diff --git a/hw/virtio-net.c b/hw/virtio-net.c
index 4590557..5917740 100644
--- a/hw/virtio-net.c
+++ b/hw/virtio-net.c
@@ -26,56 +26,6 @@
#define MAC_TABLE_ENTRIES 64
#define MAX_VLAN (1 << 12) /* Per 802.1Q definition */
-typedef struct VirtIONetQueue {
- VirtQueue *rx_vq;
- VirtQueue *tx_vq;
- QEMUTimer *tx_timer;
- QEMUBH *tx_bh;
- int tx_waiting;
- struct {
- VirtQueueElement elem;
- ssize_t len;
- } async_tx;
- struct VirtIONet *n;
-} VirtIONetQueue;
-
-typedef struct VirtIONet
-{
- VirtIODevice vdev;
- uint8_t mac[ETH_ALEN];
- uint16_t status;
- VirtIONetQueue *vqs;
- VirtQueue *ctrl_vq;
- NICState *nic;
- uint32_t tx_timeout;
- int32_t tx_burst;
- uint32_t has_vnet_hdr;
- size_t host_hdr_len;
- size_t guest_hdr_len;
- uint8_t has_ufo;
- int mergeable_rx_bufs;
- uint8_t promisc;
- uint8_t allmulti;
- uint8_t alluni;
- uint8_t nomulti;
- uint8_t nouni;
- uint8_t nobcast;
- uint8_t vhost_started;
- struct {
- int in_use;
- int first_multi;
- uint8_t multi_overflow;
- uint8_t uni_overflow;
- uint8_t *macs;
- } mac_table;
- uint32_t *vlans;
- DeviceState *qdev;
- int multiqueue;
- uint16_t max_queues;
- uint16_t curr_queues;
- size_t config_size;
-} VirtIONet;
-
/*
* Calculate the number of bytes up to and including the given 'field' of
* 'container'.
diff --git a/hw/virtio-net.h b/hw/virtio-net.h
index 0c83ca5..4d1a8cd 100644
--- a/hw/virtio-net.h
+++ b/hw/virtio-net.h
@@ -134,6 +134,56 @@
uint32_t entries;
uint8_t macs[][ETH_ALEN];
};
+
+typedef struct VirtIONetQueue {
+ VirtQueue *rx_vq;
+ VirtQueue *tx_vq;
+ QEMUTimer *tx_timer;
+ QEMUBH *tx_bh;
+ int tx_waiting;
+ struct {
+ VirtQueueElement elem;
+ ssize_t len;
+ } async_tx;
+ struct VirtIONet *n;
+} VirtIONetQueue;
+
+typedef struct VirtIONet {
+ VirtIODevice vdev;
+ uint8_t mac[ETH_ALEN];
+ uint16_t status;
+ VirtIONetQueue *vqs;
+ VirtQueue *ctrl_vq;
+ NICState *nic;
+ uint32_t tx_timeout;
+ int32_t tx_burst;
+ uint32_t has_vnet_hdr;
+ size_t host_hdr_len;
+ size_t guest_hdr_len;
+ uint8_t has_ufo;
+ int mergeable_rx_bufs;
+ uint8_t promisc;
+ uint8_t allmulti;
+ uint8_t alluni;
+ uint8_t nomulti;
+ uint8_t nouni;
+ uint8_t nobcast;
+ uint8_t vhost_started;
+ struct {
+ int in_use;
+ int first_multi;
+ uint8_t multi_overflow;
+ uint8_t uni_overflow;
+ uint8_t *macs;
+ } mac_table;
+ uint32_t *vlans;
+ DeviceState *qdev;
+ int multiqueue;
+ uint16_t max_queues;
+ uint16_t curr_queues;
+ size_t config_size;
+} VirtIONet;
+
#define VIRTIO_NET_CTRL_MAC 1
#define VIRTIO_NET_CTRL_MAC_TABLE_SET 0
#define VIRTIO_NET_CTRL_MAC_ADDR_SET 1
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index 19965e5..736a9bf 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -933,26 +933,6 @@
proxy->host_features = vdev->get_features(vdev, proxy->host_features);
}
-static int virtio_blk_init_pci(PCIDevice *pci_dev)
-{
- VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
- VirtIODevice *vdev;
-
- if (proxy->class_code != PCI_CLASS_STORAGE_SCSI &&
- proxy->class_code != PCI_CLASS_STORAGE_OTHER)
- proxy->class_code = PCI_CLASS_STORAGE_SCSI;
-
- vdev = virtio_blk_init(&pci_dev->qdev, &proxy->blk);
- if (!vdev) {
- return -1;
- }
- vdev->nvectors = proxy->nvectors;
- virtio_init_pci(proxy, vdev);
- /* make the actual value visible */
- proxy->nvectors = vdev->nvectors;
- return 0;
-}
-
static void virtio_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
@@ -961,15 +941,6 @@
msix_uninit_exclusive_bar(pci_dev);
}
-static void virtio_blk_exit_pci(PCIDevice *pci_dev)
-{
- VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
-
- virtio_pci_stop_ioeventfd(proxy);
- virtio_blk_exit(proxy->vdev);
- virtio_exit_pci(pci_dev);
-}
-
static int virtio_serial_init_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
@@ -1091,46 +1062,6 @@
virtio_exit_pci(pci_dev);
}
-static Property virtio_blk_properties[] = {
- DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
- DEFINE_BLOCK_PROPERTIES(VirtIOPCIProxy, blk.conf),
- DEFINE_BLOCK_CHS_PROPERTIES(VirtIOPCIProxy, blk.conf),
- DEFINE_PROP_STRING("serial", VirtIOPCIProxy, blk.serial),
-#ifdef __linux__
- DEFINE_PROP_BIT("scsi", VirtIOPCIProxy, blk.scsi, 0, true),
-#endif
- DEFINE_PROP_BIT("config-wce", VirtIOPCIProxy, blk.config_wce, 0, true),
- DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
-#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
- DEFINE_PROP_BIT("x-data-plane", VirtIOPCIProxy, blk.data_plane, 0, false),
-#endif
- DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
- DEFINE_VIRTIO_BLK_FEATURES(VirtIOPCIProxy, host_features),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void virtio_blk_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->init = virtio_blk_init_pci;
- k->exit = virtio_blk_exit_pci;
- k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
- k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
- k->revision = VIRTIO_PCI_ABI_VERSION;
- k->class_id = PCI_CLASS_STORAGE_SCSI;
- dc->reset = virtio_pci_reset;
- dc->props = virtio_blk_properties;
-}
-
-static const TypeInfo virtio_blk_info = {
- .name = "virtio-blk-pci",
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(VirtIOPCIProxy),
- .class_init = virtio_blk_class_init,
-};
-
static Property virtio_net_properties[] = {
DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false),
DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
@@ -1149,7 +1080,7 @@
k->init = virtio_net_init_pci;
k->exit = virtio_net_exit_pci;
- k->romfile = "pxe-virtio.rom";
+ k->romfile = "efi-virtio.rom";
k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
k->device_id = PCI_DEVICE_ID_VIRTIO_NET;
k->revision = VIRTIO_PCI_ABI_VERSION;
@@ -1268,63 +1199,6 @@
.class_init = virtio_rng_class_init,
};
-static int virtio_scsi_init_pci(PCIDevice *pci_dev)
-{
- VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
- VirtIODevice *vdev;
-
- vdev = virtio_scsi_init(&pci_dev->qdev, &proxy->scsi);
- if (!vdev) {
- return -EINVAL;
- }
-
- vdev->nvectors = proxy->nvectors == DEV_NVECTORS_UNSPECIFIED
- ? proxy->scsi.num_queues + 3
- : proxy->nvectors;
- virtio_init_pci(proxy, vdev);
-
- /* make the actual value visible */
- proxy->nvectors = vdev->nvectors;
- return 0;
-}
-
-static void virtio_scsi_exit_pci(PCIDevice *pci_dev)
-{
- VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
-
- virtio_scsi_exit(proxy->vdev);
- virtio_exit_pci(pci_dev);
-}
-
-static Property virtio_scsi_properties[] = {
- DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
- DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED),
- DEFINE_VIRTIO_SCSI_PROPERTIES(VirtIOPCIProxy, host_features, scsi),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void virtio_scsi_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->init = virtio_scsi_init_pci;
- k->exit = virtio_scsi_exit_pci;
- k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
- k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
- k->revision = 0x00;
- k->class_id = PCI_CLASS_STORAGE_SCSI;
- dc->reset = virtio_pci_reset;
- dc->props = virtio_scsi_properties;
-}
-
-static const TypeInfo virtio_scsi_info = {
- .name = "virtio-scsi-pci",
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(VirtIOPCIProxy),
- .class_init = virtio_scsi_class_init,
-};
-
#ifdef CONFIG_VIRTFS
static int virtio_9p_init_pci(PCIDevice *pci_dev)
{
@@ -1421,13 +1295,6 @@
proxy->host_features);
}
-/* This is called by virtio-bus just before the device is unplugged. */
-static void virtio_pci_device_unplug(DeviceState *d)
-{
- VirtIOPCIProxy *dev = VIRTIO_PCI(d);
- virtio_pci_stop_ioeventfd(dev);
-}
-
static int virtio_pci_init(PCIDevice *pci_dev)
{
VirtIOPCIProxy *dev = VIRTIO_PCI(pci_dev);
@@ -1442,10 +1309,7 @@
static void virtio_pci_exit(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
- VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
- BusState *qbus = BUS(&proxy->bus);
- virtio_bus_destroy_device(bus);
- qbus_free(qbus);
+ virtio_pci_stop_ioeventfd(proxy);
virtio_exit_pci(pci_dev);
}
@@ -1485,6 +1349,118 @@
.abstract = true,
};
+/* virtio-blk-pci */
+
+static Property virtio_blk_pci_properties[] = {
+ DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
+ DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
+ DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
+#ifdef CONFIG_VIRTIO_BLK_DATA_PLANE
+ DEFINE_PROP_BIT("x-data-plane", VirtIOBlkPCI, blk.data_plane, 0, false),
+#endif
+ DEFINE_VIRTIO_BLK_FEATURES(VirtIOPCIProxy, host_features),
+ DEFINE_VIRTIO_BLK_PROPERTIES(VirtIOBlkPCI, blk),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static int virtio_blk_pci_init(VirtIOPCIProxy *vpci_dev)
+{
+ VirtIOBlkPCI *dev = VIRTIO_BLK_PCI(vpci_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
+ virtio_blk_set_conf(vdev, &(dev->blk));
+ qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
+ if (qdev_init(vdev) < 0) {
+ return -1;
+ }
+ return 0;
+}
+
+static void virtio_blk_pci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
+ PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
+
+ dc->props = virtio_blk_pci_properties;
+ k->init = virtio_blk_pci_init;
+ pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
+ pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
+ pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
+ pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
+}
+
+static void virtio_blk_pci_instance_init(Object *obj)
+{
+ VirtIOBlkPCI *dev = VIRTIO_BLK_PCI(obj);
+ object_initialize(OBJECT(&dev->vdev), TYPE_VIRTIO_BLK);
+ object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
+}
+
+static const TypeInfo virtio_blk_pci_info = {
+ .name = TYPE_VIRTIO_BLK_PCI,
+ .parent = TYPE_VIRTIO_PCI,
+ .instance_size = sizeof(VirtIOBlkPCI),
+ .instance_init = virtio_blk_pci_instance_init,
+ .class_init = virtio_blk_pci_class_init,
+};
+
+/* virtio-scsi-pci */
+
+static Property virtio_scsi_pci_properties[] = {
+ DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
+ DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
+ DEV_NVECTORS_UNSPECIFIED),
+ DEFINE_VIRTIO_SCSI_FEATURES(VirtIOPCIProxy, host_features),
+ DEFINE_VIRTIO_SCSI_PROPERTIES(VirtIOSCSIPCI, vdev.conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static int virtio_scsi_pci_init_pci(VirtIOPCIProxy *vpci_dev)
+{
+ VirtIOSCSIPCI *dev = VIRTIO_SCSI_PCI(vpci_dev);
+ DeviceState *vdev = DEVICE(&dev->vdev);
+
+ if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
+ vpci_dev->nvectors = dev->vdev.conf.num_queues + 3;
+ }
+
+ qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
+ if (qdev_init(vdev) < 0) {
+ return -1;
+ }
+ return 0;
+}
+
+static void virtio_scsi_pci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
+ PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
+ k->init = virtio_scsi_pci_init_pci;
+ dc->props = virtio_scsi_pci_properties;
+ pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
+ pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
+ pcidev_k->revision = 0x00;
+ pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
+}
+
+static void virtio_scsi_pci_instance_init(Object *obj)
+{
+ VirtIOSCSIPCI *dev = VIRTIO_SCSI_PCI(obj);
+ object_initialize(OBJECT(&dev->vdev), TYPE_VIRTIO_SCSI);
+ object_property_add_child(obj, "virtio-backend", OBJECT(&dev->vdev), NULL);
+}
+
+static const TypeInfo virtio_scsi_pci_info = {
+ .name = TYPE_VIRTIO_SCSI_PCI,
+ .parent = TYPE_VIRTIO_PCI,
+ .instance_size = sizeof(VirtIOSCSIPCI),
+ .instance_init = virtio_scsi_pci_instance_init,
+ .class_init = virtio_scsi_pci_class_init,
+};
+
/* virtio-pci-bus */
void virtio_pci_bus_new(VirtioBusState *bus, VirtIOPCIProxy *dev)
@@ -1493,7 +1469,7 @@
BusState *qbus;
qbus_create_inplace((BusState *)bus, TYPE_VIRTIO_PCI_BUS, qdev, NULL);
qbus = BUS(bus);
- qbus->allow_hotplug = 0;
+ qbus->allow_hotplug = 1;
}
static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
@@ -1512,7 +1488,6 @@
k->set_guest_notifiers = virtio_pci_set_guest_notifiers;
k->vmstate_change = virtio_pci_vmstate_change;
k->device_plugged = virtio_pci_device_plugged;
- k->device_unplug = virtio_pci_device_unplug;
}
static const TypeInfo virtio_pci_bus_info = {
@@ -1524,17 +1499,17 @@
static void virtio_pci_register_types(void)
{
- type_register_static(&virtio_blk_info);
type_register_static(&virtio_net_info);
type_register_static(&virtio_serial_info);
type_register_static(&virtio_balloon_info);
- type_register_static(&virtio_scsi_info);
type_register_static(&virtio_rng_info);
type_register_static(&virtio_pci_bus_info);
type_register_static(&virtio_pci_info);
#ifdef CONFIG_VIRTFS
type_register_static(&virtio_9p_info);
#endif
+ type_register_static(&virtio_blk_pci_info);
+ type_register_static(&virtio_scsi_pci_info);
}
type_init(virtio_pci_register_types)
diff --git a/hw/virtio-pci.h b/hw/virtio-pci.h
index 2ae96f8..bfe7a8e 100644
--- a/hw/virtio-pci.h
+++ b/hw/virtio-pci.h
@@ -25,6 +25,8 @@
#include "hw/9pfs/virtio-9p-device.h"
typedef struct VirtIOPCIProxy VirtIOPCIProxy;
+typedef struct VirtIOBlkPCI VirtIOBlkPCI;
+typedef struct VirtIOSCSIPCI VirtIOSCSIPCI;
/* virtio-pci-bus */
@@ -73,7 +75,6 @@
uint32_t flags;
uint32_t class_code;
uint32_t nvectors;
- VirtIOBlkConf blk;
NICConf nic;
uint32_t host_features;
#ifdef CONFIG_VIRTFS
@@ -81,7 +82,6 @@
#endif
virtio_serial_conf serial;
virtio_net_conf net;
- VirtIOSCSIConf scsi;
VirtIORNGConf rng;
bool ioeventfd_disabled;
bool ioeventfd_started;
@@ -90,6 +90,32 @@
VirtioBusState bus;
};
+
+/*
+ * virtio-scsi-pci: This extends VirtioPCIProxy.
+ */
+#define TYPE_VIRTIO_SCSI_PCI "virtio-scsi-pci"
+#define VIRTIO_SCSI_PCI(obj) \
+ OBJECT_CHECK(VirtIOSCSIPCI, (obj), TYPE_VIRTIO_SCSI_PCI)
+
+struct VirtIOSCSIPCI {
+ VirtIOPCIProxy parent_obj;
+ VirtIOSCSI vdev;
+};
+
+/*
+ * virtio-blk-pci: This extends VirtioPCIProxy.
+ */
+#define TYPE_VIRTIO_BLK_PCI "virtio-blk-pci"
+#define VIRTIO_BLK_PCI(obj) \
+ OBJECT_CHECK(VirtIOBlkPCI, (obj), TYPE_VIRTIO_BLK_PCI)
+
+struct VirtIOBlkPCI {
+ VirtIOPCIProxy parent_obj;
+ VirtIOBlock vdev;
+ VirtIOBlkConf blk;
+};
+
void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev);
void virtio_pci_bus_new(VirtioBusState *bus, VirtIOPCIProxy *dev);
diff --git a/hw/virtio-rng.c b/hw/virtio-rng.c
index 54c1421..fa8e8f3 100644
--- a/hw/virtio-rng.c
+++ b/hw/virtio-rng.c
@@ -16,25 +16,6 @@
#include "hw/virtio-rng.h"
#include "qemu/rng.h"
-typedef struct VirtIORNG {
- VirtIODevice vdev;
-
- DeviceState *qdev;
-
- /* Only one vq - guest puts buffer(s) on it when it needs entropy */
- VirtQueue *vq;
-
- VirtIORNGConf *conf;
-
- RngBackend *rng;
-
- /* We purposefully don't migrate this state. The quota will reset on the
- * destination as a result. Rate limiting is host state, not guest state.
- */
- QEMUTimer *rate_limit_timer;
- int64_t quota_remaining;
-} VirtIORNG;
-
static bool is_guest_ready(VirtIORNG *vrng)
{
if (virtio_queue_ready(vrng->vq)
diff --git a/hw/virtio-rng.h b/hw/virtio-rng.h
index f42d748..3711c97 100644
--- a/hw/virtio-rng.h
+++ b/hw/virtio-rng.h
@@ -25,4 +25,23 @@
RndRandom *default_backend;
};
+typedef struct VirtIORNG {
+ VirtIODevice vdev;
+
+ DeviceState *qdev;
+
+ /* Only one vq - guest puts buffer(s) on it when it needs entropy */
+ VirtQueue *vq;
+
+ VirtIORNGConf *conf;
+
+ RngBackend *rng;
+
+ /* We purposefully don't migrate this state. The quota will reset on the
+ * destination as a result. Rate limiting is host state, not guest state.
+ */
+ QEMUTimer *rate_limit_timer;
+ int64_t quota_remaining;
+} VirtIORNG;
+
#endif
diff --git a/hw/virtio-scsi.c b/hw/virtio-scsi.c
index 72cc519..06a58a6 100644
--- a/hw/virtio-scsi.c
+++ b/hw/virtio-scsi.c
@@ -17,6 +17,7 @@
#include "qemu/error-report.h"
#include <hw/scsi.h>
#include <hw/scsi-defs.h>
+#include "hw/virtio-bus.h"
#define VIRTIO_SCSI_VQ_SIZE 128
#define VIRTIO_SCSI_CDB_SIZE 32
@@ -130,21 +131,6 @@
uint32_t max_lun;
} QEMU_PACKED VirtIOSCSIConfig;
-typedef struct {
- VirtIODevice vdev;
- DeviceState *qdev;
- VirtIOSCSIConf *conf;
-
- SCSIBus bus;
- uint32_t sense_size;
- uint32_t cdb_size;
- int resetting;
- bool events_dropped;
- VirtQueue *ctrl_vq;
- VirtQueue *event_vq;
- VirtQueue *cmd_vqs[0];
-} VirtIOSCSI;
-
typedef struct VirtIOSCSIReq {
VirtIOSCSI *dev;
VirtQueue *vq;
@@ -186,6 +172,7 @@
{
VirtIOSCSI *s = req->dev;
VirtQueue *vq = req->vq;
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
virtqueue_push(vq, &req->elem, req->qsgl.size + req->elem.in_sg[0].iov_len);
qemu_sglist_destroy(&req->qsgl);
if (req->sreq) {
@@ -193,7 +180,7 @@
scsi_req_unref(req->sreq);
}
g_free(req);
- virtio_notify(&s->vdev, vq);
+ virtio_notify(vdev, vq);
}
static void virtio_scsi_bad_req(void)
@@ -252,7 +239,7 @@
VirtIOSCSIReq *req = sreq->hba_private;
uint32_t n = virtio_queue_get_id(req->vq) - 2;
- assert(n < req->dev->conf->num_queues);
+ assert(n < req->dev->conf.num_queues);
qemu_put_be32s(f, &n);
qemu_put_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
}
@@ -266,7 +253,7 @@
req = g_malloc(sizeof(*req));
qemu_get_be32s(f, &n);
- assert(n < s->conf->num_queues);
+ assert(n < s->conf.num_queues);
qemu_get_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
virtio_scsi_parse_req(s, s->cmd_vqs[n], req);
@@ -528,10 +515,10 @@
VirtIOSCSIConfig *scsiconf = (VirtIOSCSIConfig *)config;
VirtIOSCSI *s = (VirtIOSCSI *)vdev;
- stl_raw(&scsiconf->num_queues, s->conf->num_queues);
+ stl_raw(&scsiconf->num_queues, s->conf.num_queues);
stl_raw(&scsiconf->seg_max, 128 - 2);
- stl_raw(&scsiconf->max_sectors, s->conf->max_sectors);
- stl_raw(&scsiconf->cmd_per_lun, s->conf->cmd_per_lun);
+ stl_raw(&scsiconf->max_sectors, s->conf.max_sectors);
+ stl_raw(&scsiconf->cmd_per_lun, s->conf.cmd_per_lun);
stl_raw(&scsiconf->event_info_size, sizeof(VirtIOSCSIEvent));
stl_raw(&scsiconf->sense_size, s->sense_size);
stl_raw(&scsiconf->cdb_size, s->cdb_size);
@@ -580,16 +567,16 @@
*/
static void virtio_scsi_save(QEMUFile *f, void *opaque)
{
- VirtIOSCSI *s = opaque;
- virtio_save(&s->vdev, f);
+ VirtIODevice *vdev = VIRTIO_DEVICE(opaque);
+ virtio_save(vdev, f);
}
static int virtio_scsi_load(QEMUFile *f, void *opaque, int version_id)
{
- VirtIOSCSI *s = opaque;
+ VirtIODevice *vdev = VIRTIO_DEVICE(opaque);
int ret;
- ret = virtio_load(&s->vdev, f);
+ ret = virtio_load(vdev, f);
if (ret) {
return ret;
}
@@ -601,9 +588,10 @@
{
VirtIOSCSIReq *req = virtio_scsi_pop_req(s, s->event_vq);
VirtIOSCSIEvent *evt;
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
int in_size;
- if (!(s->vdev.status & VIRTIO_CONFIG_S_DRIVER_OK)) {
+ if (!(vdev->status & VIRTIO_CONFIG_S_DRIVER_OK)) {
return;
}
@@ -647,7 +635,7 @@
static void virtio_scsi_handle_event(VirtIODevice *vdev, VirtQueue *vq)
{
- VirtIOSCSI *s = (VirtIOSCSI *)vdev;
+ VirtIOSCSI *s = VIRTIO_SCSI(vdev);
if (s->events_dropped) {
virtio_scsi_push_event(s, NULL, VIRTIO_SCSI_T_NO_EVENT, 0);
@@ -657,8 +645,9 @@
static void virtio_scsi_change(SCSIBus *bus, SCSIDevice *dev, SCSISense sense)
{
VirtIOSCSI *s = container_of(bus, VirtIOSCSI, bus);
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
- if (((s->vdev.guest_features >> VIRTIO_SCSI_F_CHANGE) & 1) &&
+ if (((vdev->guest_features >> VIRTIO_SCSI_F_CHANGE) & 1) &&
dev->type != TYPE_ROM) {
virtio_scsi_push_event(s, dev, VIRTIO_SCSI_T_PARAM_CHANGE,
sense.asc | (sense.ascq << 8));
@@ -668,8 +657,9 @@
static void virtio_scsi_hotplug(SCSIBus *bus, SCSIDevice *dev)
{
VirtIOSCSI *s = container_of(bus, VirtIOSCSI, bus);
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
- if ((s->vdev.guest_features >> VIRTIO_SCSI_F_HOTPLUG) & 1) {
+ if ((vdev->guest_features >> VIRTIO_SCSI_F_HOTPLUG) & 1) {
virtio_scsi_push_event(s, dev, VIRTIO_SCSI_T_TRANSPORT_RESET,
VIRTIO_SCSI_EVT_RESET_RESCAN);
}
@@ -678,8 +668,9 @@
static void virtio_scsi_hot_unplug(SCSIBus *bus, SCSIDevice *dev)
{
VirtIOSCSI *s = container_of(bus, VirtIOSCSI, bus);
+ VirtIODevice *vdev = VIRTIO_DEVICE(s);
- if ((s->vdev.guest_features >> VIRTIO_SCSI_F_HOTPLUG) & 1) {
+ if ((vdev->guest_features >> VIRTIO_SCSI_F_HOTPLUG) & 1) {
virtio_scsi_push_event(s, dev, VIRTIO_SCSI_T_TRANSPORT_RESET,
VIRTIO_SCSI_EVT_RESET_REMOVED);
}
@@ -701,49 +692,83 @@
.load_request = virtio_scsi_load_request,
};
-VirtIODevice *virtio_scsi_init(DeviceState *dev, VirtIOSCSIConf *proxyconf)
+static int virtio_scsi_device_init(VirtIODevice *vdev)
{
- VirtIOSCSI *s;
+ DeviceState *qdev = DEVICE(vdev);
+ VirtIOSCSI *s = VIRTIO_SCSI(vdev);
static int virtio_scsi_id;
- size_t sz;
int i;
- sz = sizeof(VirtIOSCSI) + proxyconf->num_queues * sizeof(VirtQueue *);
- s = (VirtIOSCSI *)virtio_common_init("virtio-scsi", VIRTIO_ID_SCSI,
- sizeof(VirtIOSCSIConfig), sz);
+ virtio_init(VIRTIO_DEVICE(s), "virtio-scsi", VIRTIO_ID_SCSI,
+ sizeof(VirtIOSCSIConfig));
- s->qdev = dev;
- s->conf = proxyconf;
+ s->cmd_vqs = g_malloc0(s->conf.num_queues * sizeof(VirtQueue *));
/* TODO set up vdev function pointers */
- s->vdev.get_config = virtio_scsi_get_config;
- s->vdev.set_config = virtio_scsi_set_config;
- s->vdev.get_features = virtio_scsi_get_features;
- s->vdev.reset = virtio_scsi_reset;
+ vdev->get_config = virtio_scsi_get_config;
+ vdev->set_config = virtio_scsi_set_config;
+ vdev->get_features = virtio_scsi_get_features;
+ vdev->reset = virtio_scsi_reset;
- s->ctrl_vq = virtio_add_queue(&s->vdev, VIRTIO_SCSI_VQ_SIZE,
- virtio_scsi_handle_ctrl);
- s->event_vq = virtio_add_queue(&s->vdev, VIRTIO_SCSI_VQ_SIZE,
+ s->ctrl_vq = virtio_add_queue(vdev, VIRTIO_SCSI_VQ_SIZE,
+ virtio_scsi_handle_ctrl);
+ s->event_vq = virtio_add_queue(vdev, VIRTIO_SCSI_VQ_SIZE,
virtio_scsi_handle_event);
- for (i = 0; i < s->conf->num_queues; i++) {
- s->cmd_vqs[i] = virtio_add_queue(&s->vdev, VIRTIO_SCSI_VQ_SIZE,
+ for (i = 0; i < s->conf.num_queues; i++) {
+ s->cmd_vqs[i] = virtio_add_queue(vdev, VIRTIO_SCSI_VQ_SIZE,
virtio_scsi_handle_cmd);
}
- scsi_bus_new(&s->bus, dev, &virtio_scsi_scsi_info);
- if (!dev->hotplugged) {
+ scsi_bus_new(&s->bus, qdev, &virtio_scsi_scsi_info);
+ if (!qdev->hotplugged) {
scsi_bus_legacy_handle_cmdline(&s->bus);
}
- register_savevm(dev, "virtio-scsi", virtio_scsi_id++, 1,
+ register_savevm(qdev, "virtio-scsi", virtio_scsi_id++, 1,
virtio_scsi_save, virtio_scsi_load, s);
- return &s->vdev;
+ return 0;
}
-void virtio_scsi_exit(VirtIODevice *vdev)
+static int virtio_scsi_device_exit(DeviceState *qdev)
{
- VirtIOSCSI *s = (VirtIOSCSI *)vdev;
- unregister_savevm(s->qdev, "virtio-scsi", s);
- virtio_cleanup(vdev);
+ VirtIOSCSI *s = VIRTIO_SCSI(qdev);
+ VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
+
+ unregister_savevm(qdev, "virtio-scsi", s);
+ g_free(s->cmd_vqs);
+ virtio_common_cleanup(vdev);
+ return 0;
}
+
+static Property virtio_scsi_properties[] = {
+ DEFINE_VIRTIO_SCSI_PROPERTIES(VirtIOSCSI, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void virtio_scsi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
+ dc->exit = virtio_scsi_device_exit;
+ dc->props = virtio_scsi_properties;
+ vdc->init = virtio_scsi_device_init;
+ vdc->get_config = virtio_scsi_get_config;
+ vdc->set_config = virtio_scsi_set_config;
+ vdc->get_features = virtio_scsi_get_features;
+ vdc->reset = virtio_scsi_reset;
+}
+
+static const TypeInfo virtio_scsi_info = {
+ .name = TYPE_VIRTIO_SCSI,
+ .parent = TYPE_VIRTIO_DEVICE,
+ .instance_size = sizeof(VirtIOSCSI),
+ .class_init = virtio_scsi_class_init,
+};
+
+static void virtio_register_types(void)
+{
+ type_register_static(&virtio_scsi_info);
+}
+
+type_init(virtio_register_types)
diff --git a/hw/virtio-scsi.h b/hw/virtio-scsi.h
index 81b3279..31e97bb 100644
--- a/hw/virtio-scsi.h
+++ b/hw/virtio-scsi.h
@@ -16,6 +16,12 @@
#include "hw/virtio.h"
#include "hw/pci/pci.h"
+#include "hw/scsi.h"
+
+#define TYPE_VIRTIO_SCSI "virtio-scsi"
+#define VIRTIO_SCSI(obj) \
+ OBJECT_CHECK(VirtIOSCSI, (obj), TYPE_VIRTIO_SCSI)
+
/* The ID for virtio_scsi */
#define VIRTIO_ID_SCSI 8
@@ -31,12 +37,30 @@
uint32_t cmd_per_lun;
};
-#define DEFINE_VIRTIO_SCSI_PROPERTIES(_state, _features_field, _conf_field) \
- DEFINE_VIRTIO_COMMON_FEATURES(_state, _features_field), \
- DEFINE_PROP_UINT32("num_queues", _state, _conf_field.num_queues, 1), \
- DEFINE_PROP_UINT32("max_sectors", _state, _conf_field.max_sectors, 0xFFFF), \
- DEFINE_PROP_UINT32("cmd_per_lun", _state, _conf_field.cmd_per_lun, 128), \
- DEFINE_PROP_BIT("hotplug", _state, _features_field, VIRTIO_SCSI_F_HOTPLUG, true), \
- DEFINE_PROP_BIT("param_change", _state, _features_field, VIRTIO_SCSI_F_CHANGE, true)
+typedef struct VirtIOSCSI {
+ VirtIODevice parent_obj;
+ VirtIOSCSIConf conf;
+
+ SCSIBus bus;
+ uint32_t sense_size;
+ uint32_t cdb_size;
+ int resetting;
+ bool events_dropped;
+ VirtQueue *ctrl_vq;
+ VirtQueue *event_vq;
+ VirtQueue **cmd_vqs;
+} VirtIOSCSI;
+
+#define DEFINE_VIRTIO_SCSI_PROPERTIES(_state, _conf_field) \
+ DEFINE_PROP_UINT32("num_queues", _state, _conf_field.num_queues, 1), \
+ DEFINE_PROP_UINT32("max_sectors", _state, _conf_field.max_sectors, 0xFFFF),\
+ DEFINE_PROP_UINT32("cmd_per_lun", _state, _conf_field.cmd_per_lun, 128)
+
+#define DEFINE_VIRTIO_SCSI_FEATURES(_state, _feature_field) \
+ DEFINE_VIRTIO_COMMON_FEATURES(_state, _feature_field), \
+ DEFINE_PROP_BIT("hotplug", _state, _feature_field, VIRTIO_SCSI_F_HOTPLUG, \
+ true), \
+ DEFINE_PROP_BIT("param_change", _state, _feature_field, \
+ VIRTIO_SCSI_F_CHANGE, true)
#endif /* _QEMU_VIRTIO_SCSI_H */
diff --git a/hw/virtio-serial-bus.c b/hw/virtio-serial-bus.c
index 7d0515f..ab7168e 100644
--- a/hw/virtio-serial-bus.c
+++ b/hw/virtio-serial-bus.c
@@ -25,47 +25,6 @@
#include "trace.h"
#include "hw/virtio-serial.h"
-/* The virtio-serial bus on top of which the ports will ride as devices */
-struct VirtIOSerialBus {
- BusState qbus;
-
- /* This is the parent device that provides the bus for ports. */
- VirtIOSerial *vser;
-
- /* The maximum number of ports that can ride on top of this bus */
- uint32_t max_nr_ports;
-};
-
-typedef struct VirtIOSerialPostLoad {
- QEMUTimer *timer;
- uint32_t nr_active_ports;
- struct {
- VirtIOSerialPort *port;
- uint8_t host_connected;
- } *connected;
-} VirtIOSerialPostLoad;
-
-struct VirtIOSerial {
- VirtIODevice vdev;
-
- VirtQueue *c_ivq, *c_ovq;
- /* Arrays of ivqs and ovqs: one per port */
- VirtQueue **ivqs, **ovqs;
-
- VirtIOSerialBus bus;
-
- DeviceState *qdev;
-
- QTAILQ_HEAD(, VirtIOSerialPort) ports;
-
- /* bitmap for identifying active ports */
- uint32_t *ports_map;
-
- struct virtio_console_config config;
-
- struct VirtIOSerialPostLoad *post_load;
-};
-
static VirtIOSerialPort *find_port_by_id(VirtIOSerial *vser, uint32_t id)
{
VirtIOSerialPort *port;
diff --git a/hw/virtio-serial.h b/hw/virtio-serial.h
index d2d9fb7..484dcfe 100644
--- a/hw/virtio-serial.h
+++ b/hw/virtio-serial.h
@@ -173,6 +173,47 @@
bool throttled;
};
+/* The virtio-serial bus on top of which the ports will ride as devices */
+struct VirtIOSerialBus {
+ BusState qbus;
+
+ /* This is the parent device that provides the bus for ports. */
+ VirtIOSerial *vser;
+
+ /* The maximum number of ports that can ride on top of this bus */
+ uint32_t max_nr_ports;
+};
+
+typedef struct VirtIOSerialPostLoad {
+ QEMUTimer *timer;
+ uint32_t nr_active_ports;
+ struct {
+ VirtIOSerialPort *port;
+ uint8_t host_connected;
+ } *connected;
+} VirtIOSerialPostLoad;
+
+struct VirtIOSerial {
+ VirtIODevice vdev;
+
+ VirtQueue *c_ivq, *c_ovq;
+ /* Arrays of ivqs and ovqs: one per port */
+ VirtQueue **ivqs, **ovqs;
+
+ VirtIOSerialBus bus;
+
+ DeviceState *qdev;
+
+ QTAILQ_HEAD(, VirtIOSerialPort) ports;
+
+ /* bitmap for identifying active ports */
+ uint32_t *ports_map;
+
+ struct virtio_console_config config;
+
+ struct VirtIOSerialPostLoad *post_load;
+};
+
/* Interface to the virtio-serial bus */
/*
diff --git a/hw/virtio.h b/hw/virtio.h
index ca43fd7..fdbe931 100644
--- a/hw/virtio.h
+++ b/hw/virtio.h
@@ -240,7 +240,6 @@
/* Base devices. */
typedef struct VirtIOBlkConf VirtIOBlkConf;
-VirtIODevice *virtio_blk_init(DeviceState *dev, VirtIOBlkConf *blk);
struct virtio_net_conf;
VirtIODevice *virtio_net_init(DeviceState *dev, NICConf *conf,
struct virtio_net_conf *net,
@@ -258,7 +257,6 @@
void virtio_net_exit(VirtIODevice *vdev);
-void virtio_blk_exit(VirtIODevice *vdev);
void virtio_serial_exit(VirtIODevice *vdev);
void virtio_balloon_exit(VirtIODevice *vdev);
void virtio_scsi_exit(VirtIODevice *vdev);
diff --git a/hw/vmware_utils.h b/hw/vmware_utils.h
new file mode 100644
index 0000000..5307e2c
--- /dev/null
+++ b/hw/vmware_utils.h
@@ -0,0 +1,143 @@
+/*
+ * QEMU VMWARE paravirtual devices - auxiliary code
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef VMWARE_UTILS_H
+#define VMWARE_UTILS_H
+
+#include "qemu/range.h"
+
+#ifndef VMW_SHPRN
+#define VMW_SHPRN(fmt, ...) do {} while (0)
+#endif
+
+/*
+ * Shared memory access functions with byte swap support
+ * Each function contains printout for reverse-engineering needs
+ *
+ */
+static inline void
+vmw_shmem_read(hwaddr addr, void *buf, int len)
+{
+ VMW_SHPRN("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf);
+ cpu_physical_memory_read(addr, buf, len);
+}
+
+static inline void
+vmw_shmem_write(hwaddr addr, void *buf, int len)
+{
+ VMW_SHPRN("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf);
+ cpu_physical_memory_write(addr, buf, len);
+}
+
+static inline void
+vmw_shmem_rw(hwaddr addr, void *buf, int len, int is_write)
+{
+ VMW_SHPRN("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d",
+ addr, len, buf, is_write);
+
+ cpu_physical_memory_rw(addr, buf, len, is_write);
+}
+
+static inline void
+vmw_shmem_set(hwaddr addr, uint8 val, int len)
+{
+ int i;
+ VMW_SHPRN("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val);
+
+ for (i = 0; i < len; i++) {
+ cpu_physical_memory_write(addr + i, &val, 1);
+ }
+}
+
+static inline uint32_t
+vmw_shmem_ld8(hwaddr addr)
+{
+ uint8_t res = ldub_phys(addr);
+ VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res);
+ return res;
+}
+
+static inline void
+vmw_shmem_st8(hwaddr addr, uint8_t value)
+{
+ VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
+ stb_phys(addr, value);
+}
+
+static inline uint32_t
+vmw_shmem_ld16(hwaddr addr)
+{
+ uint16_t res = lduw_le_phys(addr);
+ VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
+ return res;
+}
+
+static inline void
+vmw_shmem_st16(hwaddr addr, uint16_t value)
+{
+ VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
+ stw_le_phys(addr, value);
+}
+
+static inline uint32_t
+vmw_shmem_ld32(hwaddr addr)
+{
+ uint32_t res = ldl_le_phys(addr);
+ VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
+ return res;
+}
+
+static inline void
+vmw_shmem_st32(hwaddr addr, uint32_t value)
+{
+ VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
+ stl_le_phys(addr, value);
+}
+
+static inline uint64_t
+vmw_shmem_ld64(hwaddr addr)
+{
+ uint64_t res = ldq_le_phys(addr);
+ VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res);
+ return res;
+}
+
+static inline void
+vmw_shmem_st64(hwaddr addr, uint64_t value)
+{
+ VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
+ stq_le_phys(addr, value);
+}
+
+/* Macros for simplification of operations on array-style registers */
+
+/*
+ * Whether <addr> lies inside of array-style register defined by <base>,
+ * number of elements (<cnt>) and element size (<regsize>)
+ *
+*/
+#define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \
+ range_covers_byte(base, cnt * regsize, addr)
+
+/*
+ * Returns index of given register (<addr>) in array-style register defined by
+ * <base> and element size (<regsize>)
+ *
+*/
+#define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \
+ (((addr) - (base)) / (regsize))
+
+#endif
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index db2f187..5b9ce8f 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -57,9 +57,6 @@
int new_height;
uint32_t guest;
uint32_t svgaid;
- uint32_t wred;
- uint32_t wgreen;
- uint32_t wblue;
int syncing;
MemoryRegion fifo_ram;
@@ -289,6 +286,7 @@
static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
int x, int y, int w, int h)
{
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
int line;
int bypl;
int width;
@@ -305,11 +303,11 @@
fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w);
w = 0;
}
- if (x + w > ds_get_width(s->vga.ds)) {
+ if (x + w > surface_width(surface)) {
fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
__func__, x, w);
- x = MIN(x, ds_get_width(s->vga.ds));
- w = ds_get_width(s->vga.ds) - x;
+ x = MIN(x, surface_width(surface));
+ w = surface_width(surface) - x;
}
if (y < 0) {
@@ -321,23 +319,23 @@
fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h);
h = 0;
}
- if (y + h > ds_get_height(s->vga.ds)) {
+ if (y + h > surface_height(surface)) {
fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
__func__, y, h);
- y = MIN(y, ds_get_height(s->vga.ds));
- h = ds_get_height(s->vga.ds) - y;
+ y = MIN(y, surface_height(surface));
+ h = surface_height(surface) - y;
}
- bypl = ds_get_linesize(s->vga.ds);
- width = ds_get_bytes_per_pixel(s->vga.ds) * w;
- start = ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y;
+ bypl = surface_stride(surface);
+ width = surface_bytes_per_pixel(surface) * w;
+ start = surface_bytes_per_pixel(surface) * x + bypl * y;
src = s->vga.vram_ptr + start;
- dst = ds_get_data(s->vga.ds) + start;
+ dst = surface_data(surface) + start;
for (line = h; line > 0; line--, src += bypl, dst += bypl) {
memcpy(dst, src, width);
}
- dpy_gfx_update(s->vga.ds, x, y, w, h);
+ dpy_gfx_update(s->vga.con, x, y, w, h);
}
static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
@@ -373,9 +371,10 @@
static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
int x0, int y0, int x1, int y1, int w, int h)
{
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
uint8_t *vram = s->vga.vram_ptr;
- int bypl = ds_get_linesize(s->vga.ds);
- int bypp = ds_get_bytes_per_pixel(s->vga.ds);
+ int bypl = surface_stride(surface);
+ int bypp = surface_bytes_per_pixel(surface);
int width = bypp * w;
int line = h;
uint8_t *ptr[2];
@@ -402,8 +401,9 @@
static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
uint32_t c, int x, int y, int w, int h)
{
- int bypl = ds_get_linesize(s->vga.ds);
- int width = ds_get_bytes_per_pixel(s->vga.ds) * w;
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
+ int bypl = surface_stride(surface);
+ int width = surface_bytes_per_pixel(surface) * w;
int line = h;
int column;
uint8_t *fst;
@@ -416,14 +416,14 @@
col[2] = c >> 16;
col[3] = c >> 24;
- fst = s->vga.vram_ptr + ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y;
+ fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
if (line--) {
dst = fst;
src = col;
for (column = width; column > 0; column--) {
*(dst++) = *(src++);
- if (src - col == ds_get_bytes_per_pixel(s->vga.ds)) {
+ if (src - col == surface_bytes_per_pixel(surface)) {
src = col;
}
}
@@ -490,7 +490,7 @@
qc = cursor_builtin_left_ptr();
}
- dpy_cursor_define(s->vga.ds, qc);
+ dpy_cursor_define(s->vga.con, qc);
cursor_put(qc);
}
#endif
@@ -720,6 +720,7 @@
{
uint32_t caps;
struct vmsvga_state_s *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
switch (s->index) {
case SVGA_REG_ID:
@@ -729,10 +730,10 @@
return s->enable;
case SVGA_REG_WIDTH:
- return ds_get_width(s->vga.ds);
+ return surface_width(surface);
case SVGA_REG_HEIGHT:
- return ds_get_height(s->vga.ds);
+ return surface_height(surface);
case SVGA_REG_MAX_WIDTH:
return SVGA_MAX_WIDTH;
@@ -750,13 +751,13 @@
return 0x0;
case SVGA_REG_RED_MASK:
- return s->wred;
+ return surface->pf.rmask;
case SVGA_REG_GREEN_MASK:
- return s->wgreen;
+ return surface->pf.gmask;
case SVGA_REG_BLUE_MASK:
- return s->wblue;
+ return surface->pf.bmask;
case SVGA_REG_BYTES_PER_LINE:
return s->bypp * s->new_width;
@@ -785,7 +786,7 @@
caps |= SVGA_CAP_RECT_FILL;
#endif
#ifdef HW_MOUSE_ACCEL
- if (dpy_cursor_define_supported(s->vga.ds)) {
+ if (dpy_cursor_define_supported(s->vga.con)) {
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
SVGA_CAP_CURSOR_BYPASS;
}
@@ -947,7 +948,7 @@
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
#ifdef HW_MOUSE_ACCEL
if (value <= SVGA_CURSOR_ON_SHOW) {
- dpy_mouse_set(s->vga.ds, s->cursor.x, s->cursor.y, s->cursor.on);
+ dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
}
#endif
break;
@@ -982,9 +983,11 @@
static inline void vmsvga_check_size(struct vmsvga_state_s *s)
{
- if (s->new_width != ds_get_width(s->vga.ds) ||
- s->new_height != ds_get_height(s->vga.ds)) {
- qemu_console_resize(s->vga.ds, s->new_width, s->new_height);
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
+
+ if (s->new_width != surface_width(surface) ||
+ s->new_height != surface_height(surface)) {
+ qemu_console_resize(s->vga.con, s->new_width, s->new_height);
s->invalidated = 1;
}
}
@@ -992,6 +995,7 @@
static void vmsvga_update_display(void *opaque)
{
struct vmsvga_state_s *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
bool dirty = false;
if (!s->enable) {
@@ -1011,19 +1015,19 @@
if (memory_region_is_logging(&s->vga.vram)) {
vga_sync_dirty_bitmap(&s->vga);
dirty = memory_region_get_dirty(&s->vga.vram, 0,
- ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds),
+ surface_stride(surface) * surface_height(surface),
DIRTY_MEMORY_VGA);
}
if (s->invalidated || dirty) {
s->invalidated = 0;
- memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
- ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds));
- dpy_gfx_update(s->vga.ds, 0, 0,
- ds_get_width(s->vga.ds), ds_get_height(s->vga.ds));
+ memcpy(surface_data(surface), s->vga.vram_ptr,
+ surface_stride(surface) * surface_height(surface));
+ dpy_gfx_update(s->vga.con, 0, 0,
+ surface_width(surface), surface_height(surface));
}
if (dirty) {
memory_region_reset_dirty(&s->vga.vram, 0,
- ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds),
+ surface_stride(surface) * surface_height(surface),
DIRTY_MEMORY_VGA);
}
}
@@ -1063,17 +1067,19 @@
Error **errp)
{
struct vmsvga_state_s *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->vga.con);
+
if (!s->enable) {
s->vga.screen_dump(&s->vga, filename, cswitch, errp);
return;
}
- if (ds_get_bits_per_pixel(s->vga.ds) == 32) {
+ if (surface_bits_per_pixel(surface) == 32) {
DisplaySurface *ds = qemu_create_displaysurface_from(
- ds_get_width(s->vga.ds),
- ds_get_height(s->vga.ds),
+ surface_width(surface),
+ surface_height(surface),
32,
- ds_get_linesize(s->vga.ds),
+ surface_stride(surface),
s->vga.vram_ptr, false);
ppm_save(filename, ds, errp);
g_free(ds);
@@ -1143,14 +1149,16 @@
static void vmsvga_init(struct vmsvga_state_s *s,
MemoryRegion *address_space, MemoryRegion *io)
{
+ DisplaySurface *surface;
+
s->scratch_size = SVGA_SCRATCH_SIZE;
s->scratch = g_malloc(s->scratch_size * 4);
- s->vga.ds = graphic_console_init(vmsvga_update_display,
- vmsvga_invalidate_display,
- vmsvga_screen_dump,
- vmsvga_text_update, s);
-
+ s->vga.con = graphic_console_init(vmsvga_update_display,
+ vmsvga_invalidate_display,
+ vmsvga_screen_dump,
+ vmsvga_text_update, s);
+ surface = qemu_console_surface(s->vga.con);
s->fifo_size = SVGA_FIFO_SIZE;
memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
@@ -1162,11 +1170,8 @@
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
/* Save some values here in case they are changed later.
* This is suspicious and needs more though why it is needed. */
- s->depth = ds_get_bits_per_pixel(s->vga.ds);
- s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
- s->wred = ds_get_rmask(s->vga.ds);
- s->wgreen = ds_get_gmask(s->vga.ds);
- s->wblue = ds_get_bmask(s->vga.ds);
+ s->depth = surface_bits_per_pixel(surface);
+ s->bypp = surface_bytes_per_pixel(surface);
}
static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
diff --git a/hw/vmxnet3.c b/hw/vmxnet3.c
new file mode 100644
index 0000000..925be80
--- /dev/null
+++ b/hw/vmxnet3.c
@@ -0,0 +1,2461 @@
+/*
+ * QEMU VMWARE VMXNET3 paravirtual NIC
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "hw.h"
+#include "pci/pci.h"
+#include "net/net.h"
+#include "virtio-net.h"
+#include "net/tap.h"
+#include "net/checksum.h"
+#include "sysemu/sysemu.h"
+#include "qemu-common.h"
+#include "qemu/bswap.h"
+#include "pci/msix.h"
+#include "pci/msi.h"
+
+#include "vmxnet3.h"
+#include "vmxnet_debug.h"
+#include "vmware_utils.h"
+#include "vmxnet_tx_pkt.h"
+#include "vmxnet_rx_pkt.h"
+
+#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
+#define VMXNET3_MSIX_BAR_SIZE 0x2000
+
+#define VMXNET3_BAR0_IDX (0)
+#define VMXNET3_BAR1_IDX (1)
+#define VMXNET3_MSIX_BAR_IDX (2)
+
+#define VMXNET3_OFF_MSIX_TABLE (0x000)
+#define VMXNET3_OFF_MSIX_PBA (0x800)
+
+/* Link speed in Mbps should be shifted by 16 */
+#define VMXNET3_LINK_SPEED (1000 << 16)
+
+/* Link status: 1 - up, 0 - down. */
+#define VMXNET3_LINK_STATUS_UP 0x1
+
+/* Least significant bit should be set for revision and version */
+#define VMXNET3_DEVICE_VERSION 0x1
+#define VMXNET3_DEVICE_REVISION 0x1
+
+/* Macros for rings descriptors access */
+#define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
+ (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
+
+#define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
+ (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
+
+#define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
+ (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
+
+#define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
+ (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
+
+#define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
+ (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
+
+#define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
+ (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
+
+#define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
+ (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
+
+#define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
+ (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
+
+#define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
+ (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
+
+#define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
+ (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
+
+/* Macros for guest driver shared area access */
+#define VMXNET3_READ_DRV_SHARED64(shpa, field) \
+ (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
+
+#define VMXNET3_READ_DRV_SHARED32(shpa, field) \
+ (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
+
+#define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
+ (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
+
+#define VMXNET3_READ_DRV_SHARED16(shpa, field) \
+ (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
+
+#define VMXNET3_READ_DRV_SHARED8(shpa, field) \
+ (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
+
+#define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
+ (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
+
+#define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
+
+#define TYPE_VMXNET3 "vmxnet3"
+#define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
+
+/* Cyclic ring abstraction */
+typedef struct {
+ hwaddr pa;
+ size_t size;
+ size_t cell_size;
+ size_t next;
+ uint8_t gen;
+} Vmxnet3Ring;
+
+static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,
+ hwaddr pa,
+ size_t size,
+ size_t cell_size,
+ bool zero_region)
+{
+ ring->pa = pa;
+ ring->size = size;
+ ring->cell_size = cell_size;
+ ring->gen = VMXNET3_INIT_GEN;
+ ring->next = 0;
+
+ if (zero_region) {
+ vmw_shmem_set(pa, 0, size * cell_size);
+ }
+}
+
+#define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
+ macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \
+ (ring_name), (ridx), \
+ (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
+
+static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
+{
+ if (++ring->next >= ring->size) {
+ ring->next = 0;
+ ring->gen ^= 1;
+ }
+}
+
+static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
+{
+ if (ring->next-- == 0) {
+ ring->next = ring->size - 1;
+ ring->gen ^= 1;
+ }
+}
+
+static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
+{
+ return ring->pa + ring->next * ring->cell_size;
+}
+
+static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)
+{
+ vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
+}
+
+static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)
+{
+ vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
+}
+
+static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
+{
+ return ring->next;
+}
+
+static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
+{
+ return ring->gen;
+}
+
+/* Debug trace-related functions */
+static inline void
+vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
+{
+ VMW_PKPRN("TX DESCR: "
+ "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
+ "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
+ "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
+ le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
+ descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
+ descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
+}
+
+static inline void
+vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
+{
+ VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
+ "csum_start: %d, csum_offset: %d",
+ vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
+ vhdr->csum_start, vhdr->csum_offset);
+}
+
+static inline void
+vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
+{
+ VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
+ "dtype: %d, ext1: %d, btype: %d",
+ le64_to_cpu(descr->addr), descr->len, descr->gen,
+ descr->rsvd, descr->dtype, descr->ext1, descr->btype);
+}
+
+/* Device state and helper functions */
+#define VMXNET3_RX_RINGS_PER_QUEUE (2)
+
+typedef struct {
+ Vmxnet3Ring tx_ring;
+ Vmxnet3Ring comp_ring;
+
+ uint8_t intr_idx;
+ hwaddr tx_stats_pa;
+ struct UPT1_TxStats txq_stats;
+} Vmxnet3TxqDescr;
+
+typedef struct {
+ Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
+ Vmxnet3Ring comp_ring;
+ uint8_t intr_idx;
+ hwaddr rx_stats_pa;
+ struct UPT1_RxStats rxq_stats;
+} Vmxnet3RxqDescr;
+
+typedef struct {
+ bool is_masked;
+ bool is_pending;
+ bool is_asserted;
+} Vmxnet3IntState;
+
+typedef struct {
+ PCIDevice parent_obj;
+ NICState *nic;
+ NICConf conf;
+ MemoryRegion bar0;
+ MemoryRegion bar1;
+ MemoryRegion msix_bar;
+
+ Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
+ Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
+
+ /* Whether MSI-X support was installed successfully */
+ bool msix_used;
+ /* Whether MSI support was installed successfully */
+ bool msi_used;
+ hwaddr drv_shmem;
+ hwaddr temp_shared_guest_driver_memory;
+
+ uint8_t txq_num;
+
+ /* This boolean tells whether RX packet being indicated has to */
+ /* be split into head and body chunks from different RX rings */
+ bool rx_packets_compound;
+
+ bool rx_vlan_stripping;
+ bool lro_supported;
+
+ uint8_t rxq_num;
+
+ /* Network MTU */
+ uint32_t mtu;
+
+ /* Maximum number of fragments for indicated TX packets */
+ uint32_t max_tx_frags;
+
+ /* Maximum number of fragments for indicated RX packets */
+ uint16_t max_rx_frags;
+
+ /* Index for events interrupt */
+ uint8_t event_int_idx;
+
+ /* Whether automatic interrupts masking enabled */
+ bool auto_int_masking;
+
+ bool peer_has_vhdr;
+
+ /* TX packets to QEMU interface */
+ struct VmxnetTxPkt *tx_pkt;
+ uint32_t offload_mode;
+ uint32_t cso_or_gso_size;
+ uint16_t tci;
+ bool needs_vlan;
+
+ struct VmxnetRxPkt *rx_pkt;
+
+ bool tx_sop;
+ bool skip_current_tx_pkt;
+
+ uint32_t device_active;
+ uint32_t last_command;
+
+ uint32_t link_status_and_speed;
+
+ Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
+
+ uint32_t temp_mac; /* To store the low part first */
+
+ MACAddr perm_mac;
+ uint32_t vlan_table[VMXNET3_VFT_SIZE];
+ uint32_t rx_mode;
+ MACAddr *mcast_list;
+ uint32_t mcast_list_len;
+ uint32_t mcast_list_buff_size; /* needed for live migration. */
+} VMXNET3State;
+
+/* Interrupt management */
+
+/*
+ *This function returns sign whether interrupt line is in asserted state
+ * This depends on the type of interrupt used. For INTX interrupt line will
+ * be asserted until explicit deassertion, for MSI(X) interrupt line will
+ * be deasserted automatically due to notification semantics of the MSI(X)
+ * interrupts
+ */
+static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+
+ if (s->msix_used && msix_enabled(d)) {
+ VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
+ msix_notify(d, int_idx);
+ return false;
+ }
+ if (s->msi_used && msi_enabled(d)) {
+ VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
+ msi_notify(d, int_idx);
+ return false;
+ }
+
+ VMW_IRPRN("Asserting line for interrupt %u", int_idx);
+ qemu_set_irq(d->irq[int_idx], 1);
+ return true;
+}
+
+static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+
+ /*
+ * This function should never be called for MSI(X) interrupts
+ * because deassertion never required for message interrupts
+ */
+ assert(!s->msix_used || !msix_enabled(d));
+ /*
+ * This function should never be called for MSI(X) interrupts
+ * because deassertion never required for message interrupts
+ */
+ assert(!s->msi_used || !msi_enabled(d));
+
+ VMW_IRPRN("Deasserting line for interrupt %u", lidx);
+ qemu_set_irq(d->irq[lidx], 0);
+}
+
+static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
+{
+ if (!s->interrupt_states[lidx].is_pending &&
+ s->interrupt_states[lidx].is_asserted) {
+ VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
+ _vmxnet3_deassert_interrupt_line(s, lidx);
+ s->interrupt_states[lidx].is_asserted = false;
+ return;
+ }
+
+ if (s->interrupt_states[lidx].is_pending &&
+ !s->interrupt_states[lidx].is_masked &&
+ !s->interrupt_states[lidx].is_asserted) {
+ VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
+ s->interrupt_states[lidx].is_asserted =
+ _vmxnet3_assert_interrupt_line(s, lidx);
+ s->interrupt_states[lidx].is_pending = false;
+ return;
+ }
+}
+
+static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+ s->interrupt_states[lidx].is_pending = true;
+ vmxnet3_update_interrupt_line_state(s, lidx);
+
+ if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
+ goto do_automask;
+ }
+
+ if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {
+ goto do_automask;
+ }
+
+ return;
+
+do_automask:
+ s->interrupt_states[lidx].is_masked = true;
+ vmxnet3_update_interrupt_line_state(s, lidx);
+}
+
+static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
+{
+ return s->interrupt_states[lidx].is_asserted;
+}
+
+static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
+{
+ s->interrupt_states[int_idx].is_pending = false;
+ if (s->auto_int_masking) {
+ s->interrupt_states[int_idx].is_masked = true;
+ }
+ vmxnet3_update_interrupt_line_state(s, int_idx);
+}
+
+static void
+vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
+{
+ s->interrupt_states[lidx].is_masked = is_masked;
+ vmxnet3_update_interrupt_line_state(s, lidx);
+}
+
+static bool vmxnet3_verify_driver_magic(hwaddr dshmem)
+{
+ return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);
+}
+
+#define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
+#define VMXNET3_MAKE_BYTE(byte_num, val) \
+ (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
+
+static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
+{
+ s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
+ s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
+ s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
+ s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
+ s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
+ s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
+
+ VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
+
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
+}
+
+static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
+{
+ return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
+ VMXNET3_MAKE_BYTE(1, addr->a[1]) |
+ VMXNET3_MAKE_BYTE(2, addr->a[2]) |
+ VMXNET3_MAKE_BYTE(3, addr->a[3]);
+}
+
+static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
+{
+ return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
+ VMXNET3_MAKE_BYTE(1, addr->a[5]);
+}
+
+static void
+vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
+{
+ vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
+}
+
+static inline void
+vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
+{
+ vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
+}
+
+static inline void
+vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
+{
+ vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
+}
+
+static void
+vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
+{
+ vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
+}
+
+static void
+vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
+{
+ vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
+}
+
+static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32 tx_ridx)
+{
+ struct Vmxnet3_TxCompDesc txcq_descr;
+
+ VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
+
+ txcq_descr.txdIdx = tx_ridx;
+ txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
+
+ vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);
+
+ /* Flush changes in TX descriptor before changing the counter value */
+ smp_wmb();
+
+ vmxnet3_inc_tx_completion_counter(s, qidx);
+ vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
+}
+
+static bool
+vmxnet3_setup_tx_offloads(VMXNET3State *s)
+{
+ switch (s->offload_mode) {
+ case VMXNET3_OM_NONE:
+ vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
+ break;
+
+ case VMXNET3_OM_CSUM:
+ vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
+ VMW_PKPRN("L4 CSO requested\n");
+ break;
+
+ case VMXNET3_OM_TSO:
+ vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,
+ s->cso_or_gso_size);
+ vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);
+ VMW_PKPRN("GSO offload requested.");
+ break;
+
+ default:
+ assert(false);
+ return false;
+ }
+
+ return true;
+}
+
+static void
+vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
+ const struct Vmxnet3_TxDesc *txd)
+{
+ s->offload_mode = txd->om;
+ s->cso_or_gso_size = txd->msscof;
+ s->tci = txd->tci;
+ s->needs_vlan = txd->ti;
+}
+
+typedef enum {
+ VMXNET3_PKT_STATUS_OK,
+ VMXNET3_PKT_STATUS_ERROR,
+ VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
+ VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
+} Vmxnet3PktStatus;
+
+static void
+vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
+ Vmxnet3PktStatus status)
+{
+ size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);
+ struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
+
+ switch (status) {
+ case VMXNET3_PKT_STATUS_OK:
+ switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {
+ case ETH_PKT_BCAST:
+ stats->bcastPktsTxOK++;
+ stats->bcastBytesTxOK += tot_len;
+ break;
+ case ETH_PKT_MCAST:
+ stats->mcastPktsTxOK++;
+ stats->mcastBytesTxOK += tot_len;
+ break;
+ case ETH_PKT_UCAST:
+ stats->ucastPktsTxOK++;
+ stats->ucastBytesTxOK += tot_len;
+ break;
+ default:
+ assert(false);
+ }
+
+ if (s->offload_mode == VMXNET3_OM_TSO) {
+ /*
+ * According to VMWARE headers this statistic is a number
+ * of packets after segmentation but since we don't have
+ * this information in QEMU model, the best we can do is to
+ * provide number of non-segmented packets
+ */
+ stats->TSOPktsTxOK++;
+ stats->TSOBytesTxOK += tot_len;
+ }
+ break;
+
+ case VMXNET3_PKT_STATUS_DISCARD:
+ stats->pktsTxDiscard++;
+ break;
+
+ case VMXNET3_PKT_STATUS_ERROR:
+ stats->pktsTxError++;
+ break;
+
+ default:
+ assert(false);
+ }
+}
+
+static void
+vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
+ int qidx,
+ Vmxnet3PktStatus status)
+{
+ struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
+ size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
+
+ switch (status) {
+ case VMXNET3_PKT_STATUS_OUT_OF_BUF:
+ stats->pktsRxOutOfBuf++;
+ break;
+
+ case VMXNET3_PKT_STATUS_ERROR:
+ stats->pktsRxError++;
+ break;
+ case VMXNET3_PKT_STATUS_OK:
+ switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
+ case ETH_PKT_BCAST:
+ stats->bcastPktsRxOK++;
+ stats->bcastBytesRxOK += tot_len;
+ break;
+ case ETH_PKT_MCAST:
+ stats->mcastPktsRxOK++;
+ stats->mcastBytesRxOK += tot_len;
+ break;
+ case ETH_PKT_UCAST:
+ stats->ucastPktsRxOK++;
+ stats->ucastBytesRxOK += tot_len;
+ break;
+ default:
+ assert(false);
+ }
+
+ if (tot_len > s->mtu) {
+ stats->LROPktsRxOK++;
+ stats->LROBytesRxOK += tot_len;
+ }
+ break;
+ default:
+ assert(false);
+ }
+}
+
+static inline bool
+vmxnet3_pop_next_tx_descr(VMXNET3State *s,
+ int qidx,
+ struct Vmxnet3_TxDesc *txd,
+ uint32_t *descr_idx)
+{
+ Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
+
+ vmxnet3_ring_read_curr_cell(ring, txd);
+ if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
+ /* Only read after generation field verification */
+ smp_rmb();
+ /* Re-read to be sure we got the latest version */
+ vmxnet3_ring_read_curr_cell(ring, txd);
+ VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
+ *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
+ vmxnet3_inc_tx_consumption_counter(s, qidx);
+ return true;
+ }
+
+ return false;
+}
+
+static bool
+vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
+{
+ Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
+
+ if (!vmxnet3_setup_tx_offloads(s)) {
+ status = VMXNET3_PKT_STATUS_ERROR;
+ goto func_exit;
+ }
+
+ /* debug prints */
+ vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));
+ vmxnet_tx_pkt_dump(s->tx_pkt);
+
+ if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
+ status = VMXNET3_PKT_STATUS_DISCARD;
+ goto func_exit;
+ }
+
+func_exit:
+ vmxnet3_on_tx_done_update_stats(s, qidx, status);
+ return (status == VMXNET3_PKT_STATUS_OK);
+}
+
+static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
+{
+ struct Vmxnet3_TxDesc txd;
+ uint32_t txd_idx;
+ uint32_t data_len;
+ hwaddr data_pa;
+
+ for (;;) {
+ if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
+ break;
+ }
+
+ vmxnet3_dump_tx_descr(&txd);
+
+ if (!s->skip_current_tx_pkt) {
+ data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
+ data_pa = le64_to_cpu(txd.addr);
+
+ if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
+ data_pa,
+ data_len)) {
+ s->skip_current_tx_pkt = true;
+ }
+ }
+
+ if (s->tx_sop) {
+ vmxnet3_tx_retrieve_metadata(s, &txd);
+ s->tx_sop = false;
+ }
+
+ if (txd.eop) {
+ if (!s->skip_current_tx_pkt) {
+ vmxnet_tx_pkt_parse(s->tx_pkt);
+
+ if (s->needs_vlan) {
+ vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
+ }
+
+ vmxnet3_send_packet(s, qidx);
+ } else {
+ vmxnet3_on_tx_done_update_stats(s, qidx,
+ VMXNET3_PKT_STATUS_ERROR);
+ }
+
+ vmxnet3_complete_packet(s, qidx, txd_idx);
+ s->tx_sop = true;
+ s->skip_current_tx_pkt = false;
+ vmxnet_tx_pkt_reset(s->tx_pkt);
+ }
+ }
+}
+
+static inline void
+vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
+ struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
+{
+ Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
+ *didx = vmxnet3_ring_curr_cell_idx(ring);
+ vmxnet3_ring_read_curr_cell(ring, dbuf);
+}
+
+static inline uint8_t
+vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
+{
+ return s->rxq_descr[qidx].rx_ring[ridx].gen;
+}
+
+static inline hwaddr
+vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
+{
+ uint8_t ring_gen;
+ struct Vmxnet3_RxCompDesc rxcd;
+
+ hwaddr daddr =
+ vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
+
+ cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
+ ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
+
+ if (rxcd.gen != ring_gen) {
+ *descr_gen = ring_gen;
+ vmxnet3_inc_rx_completion_counter(s, qidx);
+ return daddr;
+ }
+
+ return 0;
+}
+
+static inline void
+vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
+{
+ vmxnet3_dec_rx_completion_counter(s, qidx);
+}
+
+#define RXQ_IDX (0)
+#define RX_HEAD_BODY_RING (0)
+#define RX_BODY_ONLY_RING (1)
+
+static bool
+vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
+ struct Vmxnet3_RxDesc *descr_buf,
+ uint32_t *descr_idx,
+ uint32_t *ridx)
+{
+ for (;;) {
+ uint32_t ring_gen;
+ vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
+ descr_buf, descr_idx);
+
+ /* If no more free descriptors - return */
+ ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
+ if (descr_buf->gen != ring_gen) {
+ return false;
+ }
+
+ /* Only read after generation field verification */
+ smp_rmb();
+ /* Re-read to be sure we got the latest version */
+ vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
+ descr_buf, descr_idx);
+
+ /* Mark current descriptor as used/skipped */
+ vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
+
+ /* If this is what we are looking for - return */
+ if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
+ *ridx = RX_HEAD_BODY_RING;
+ return true;
+ }
+ }
+}
+
+static bool
+vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
+ struct Vmxnet3_RxDesc *d,
+ uint32_t *didx,
+ uint32_t *ridx)
+{
+ vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
+
+ /* Try to find corresponding descriptor in head/body ring */
+ if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
+ /* Only read after generation field verification */
+ smp_rmb();
+ /* Re-read to be sure we got the latest version */
+ vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
+ if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
+ vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
+ *ridx = RX_HEAD_BODY_RING;
+ return true;
+ }
+ }
+
+ /*
+ * If there is no free descriptors on head/body ring or next free
+ * descriptor is a head descriptor switch to body only ring
+ */
+ vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
+
+ /* If no more free descriptors - return */
+ if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
+ /* Only read after generation field verification */
+ smp_rmb();
+ /* Re-read to be sure we got the latest version */
+ vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
+ assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
+ *ridx = RX_BODY_ONLY_RING;
+ vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool
+vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
+ struct Vmxnet3_RxDesc *descr_buf,
+ uint32_t *descr_idx,
+ uint32_t *ridx)
+{
+ if (is_head || !s->rx_packets_compound) {
+ return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
+ } else {
+ return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
+ }
+}
+
+static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
+ struct Vmxnet3_RxCompDesc *rxcd)
+{
+ int csum_ok, is_gso;
+ bool isip4, isip6, istcp, isudp;
+ struct virtio_net_hdr *vhdr;
+ uint8_t offload_type;
+
+ if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
+ rxcd->ts = 1;
+ rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
+ }
+
+ if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
+ goto nocsum;
+ }
+
+ vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
+ /*
+ * Checksum is valid when lower level tell so or when lower level
+ * requires checksum offload telling that packet produced/bridged
+ * locally and did travel over network after last checksum calculation
+ * or production
+ */
+ csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
+ VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
+
+ offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
+ is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
+
+ if (!csum_ok && !is_gso) {
+ goto nocsum;
+ }
+
+ vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
+ if ((!istcp && !isudp) || (!isip4 && !isip6)) {
+ goto nocsum;
+ }
+
+ rxcd->cnc = 0;
+ rxcd->v4 = isip4 ? 1 : 0;
+ rxcd->v6 = isip6 ? 1 : 0;
+ rxcd->tcp = istcp ? 1 : 0;
+ rxcd->udp = isudp ? 1 : 0;
+ rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
+ return;
+
+nocsum:
+ rxcd->cnc = 1;
+ return;
+}
+
+static void
+vmxnet3_physical_memory_writev(const struct iovec *iov,
+ size_t start_iov_off,
+ hwaddr target_addr,
+ size_t bytes_to_copy)
+{
+ size_t curr_off = 0;
+ size_t copied = 0;
+
+ while (bytes_to_copy) {
+ if (start_iov_off < (curr_off + iov->iov_len)) {
+ size_t chunk_len =
+ MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
+
+ cpu_physical_memory_write(target_addr + copied,
+ iov->iov_base + start_iov_off - curr_off,
+ chunk_len);
+
+ copied += chunk_len;
+ start_iov_off += chunk_len;
+ curr_off = start_iov_off;
+ bytes_to_copy -= chunk_len;
+ } else {
+ curr_off += iov->iov_len;
+ }
+ iov++;
+ }
+}
+
+static bool
+vmxnet3_indicate_packet(VMXNET3State *s)
+{
+ struct Vmxnet3_RxDesc rxd;
+ bool is_head = true;
+ uint32_t rxd_idx;
+ uint32_t rx_ridx;
+
+ struct Vmxnet3_RxCompDesc rxcd;
+ uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
+ hwaddr new_rxcd_pa = 0;
+ hwaddr ready_rxcd_pa = 0;
+ struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);
+ size_t bytes_copied = 0;
+ size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
+ uint16_t num_frags = 0;
+ size_t chunk_size;
+
+ vmxnet_rx_pkt_dump(s->rx_pkt);
+
+ while (bytes_left > 0) {
+
+ /* cannot add more frags to packet */
+ if (num_frags == s->max_rx_frags) {
+ break;
+ }
+
+ new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
+ if (!new_rxcd_pa) {
+ break;
+ }
+
+ if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
+ break;
+ }
+
+ chunk_size = MIN(bytes_left, rxd.len);
+ vmxnet3_physical_memory_writev(data, bytes_copied,
+ le64_to_cpu(rxd.addr), chunk_size);
+ bytes_copied += chunk_size;
+ bytes_left -= chunk_size;
+
+ vmxnet3_dump_rx_descr(&rxd);
+
+ if (0 != ready_rxcd_pa) {
+ cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
+ }
+
+ memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
+ rxcd.rxdIdx = rxd_idx;
+ rxcd.len = chunk_size;
+ rxcd.sop = is_head;
+ rxcd.gen = new_rxcd_gen;
+ rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
+
+ if (0 == bytes_left) {
+ vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
+ }
+
+ VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
+ "sop %d csum_correct %lu",
+ (unsigned long) rx_ridx,
+ (unsigned long) rxcd.rxdIdx,
+ (unsigned long) rxcd.len,
+ (int) rxcd.sop,
+ (unsigned long) rxcd.tuc);
+
+ is_head = false;
+ ready_rxcd_pa = new_rxcd_pa;
+ new_rxcd_pa = 0;
+ }
+
+ if (0 != ready_rxcd_pa) {
+ rxcd.eop = 1;
+ rxcd.err = (0 != bytes_left);
+ cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
+
+ /* Flush RX descriptor changes */
+ smp_wmb();
+ }
+
+ if (0 != new_rxcd_pa) {
+ vmxnet3_revert_rxc_descr(s, RXQ_IDX);
+ }
+
+ vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
+
+ if (bytes_left == 0) {
+ vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
+ return true;
+ } else if (num_frags == s->max_rx_frags) {
+ vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
+ return false;
+ } else {
+ vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
+ VMXNET3_PKT_STATUS_OUT_OF_BUF);
+ return false;
+ }
+}
+
+static void
+vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ VMXNET3State *s = opaque;
+
+ if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
+ VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
+ int tx_queue_idx =
+ VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
+ VMXNET3_REG_ALIGN);
+ assert(tx_queue_idx <= s->txq_num);
+ vmxnet3_process_tx_queue(s, tx_queue_idx);
+ return;
+ }
+
+ if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
+ VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
+ int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
+ VMXNET3_REG_ALIGN);
+
+ VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
+
+ vmxnet3_on_interrupt_mask_changed(s, l, val);
+ return;
+ }
+
+ if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
+ VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
+ VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
+ VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
+ return;
+ }
+
+ VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
+ (uint64_t) addr, val, size);
+}
+
+static uint64_t
+vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
+{
+ if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
+ VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
+ assert(false);
+ }
+
+ VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
+ return 0;
+}
+
+static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
+ s->interrupt_states[i].is_asserted = false;
+ s->interrupt_states[i].is_pending = false;
+ s->interrupt_states[i].is_masked = true;
+ }
+}
+
+static void vmxnet3_reset_mac(VMXNET3State *s)
+{
+ memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
+ VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
+}
+
+static void vmxnet3_deactivate_device(VMXNET3State *s)
+{
+ VMW_CBPRN("Deactivating vmxnet3...");
+ s->device_active = false;
+}
+
+static void vmxnet3_reset(VMXNET3State *s)
+{
+ VMW_CBPRN("Resetting vmxnet3...");
+
+ vmxnet3_deactivate_device(s);
+ vmxnet3_reset_interrupt_states(s);
+ vmxnet_tx_pkt_reset(s->tx_pkt);
+ s->drv_shmem = 0;
+ s->tx_sop = true;
+ s->skip_current_tx_pkt = false;
+}
+
+static void vmxnet3_update_rx_mode(VMXNET3State *s)
+{
+ s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
+ devRead.rxFilterConf.rxMode);
+ VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
+}
+
+static void vmxnet3_update_vlan_filters(VMXNET3State *s)
+{
+ int i;
+
+ /* Copy configuration from shared memory */
+ VMXNET3_READ_DRV_SHARED(s->drv_shmem,
+ devRead.rxFilterConf.vfTable,
+ s->vlan_table,
+ sizeof(s->vlan_table));
+
+ /* Invert byte order when needed */
+ for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
+ s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
+ }
+
+ /* Dump configuration for debugging purposes */
+ VMW_CFPRN("Configured VLANs:");
+ for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
+ if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
+ VMW_CFPRN("\tVLAN %d is present", i);
+ }
+ }
+}
+
+static void vmxnet3_update_mcast_filters(VMXNET3State *s)
+{
+ uint16_t list_bytes =
+ VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
+ devRead.rxFilterConf.mfTableLen);
+
+ s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
+
+ s->mcast_list = g_realloc(s->mcast_list, list_bytes);
+ if (NULL == s->mcast_list) {
+ if (0 == s->mcast_list_len) {
+ VMW_CFPRN("Current multicast list is empty");
+ } else {
+ VMW_ERPRN("Failed to allocate multicast list of %d elements",
+ s->mcast_list_len);
+ }
+ s->mcast_list_len = 0;
+ } else {
+ int i;
+ hwaddr mcast_list_pa =
+ VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
+ devRead.rxFilterConf.mfTablePA);
+
+ cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
+ VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
+ for (i = 0; i < s->mcast_list_len; i++) {
+ VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
+ }
+ }
+}
+
+static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
+{
+ vmxnet3_update_rx_mode(s);
+ vmxnet3_update_vlan_filters(s);
+ vmxnet3_update_mcast_filters(s);
+}
+
+static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
+{
+ uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
+ VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
+ return interrupt_mode;
+}
+
+static void vmxnet3_fill_stats(VMXNET3State *s)
+{
+ int i;
+ for (i = 0; i < s->txq_num; i++) {
+ cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
+ &s->txq_descr[i].txq_stats,
+ sizeof(s->txq_descr[i].txq_stats));
+ }
+
+ for (i = 0; i < s->rxq_num; i++) {
+ cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
+ &s->rxq_descr[i].rxq_stats,
+ sizeof(s->rxq_descr[i].rxq_stats));
+ }
+}
+
+static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
+{
+ struct Vmxnet3_GOSInfo gos;
+
+ VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
+ &gos, sizeof(gos));
+ s->rx_packets_compound =
+ (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
+
+ VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
+}
+
+static void
+vmxnet3_dump_conf_descr(const char *name,
+ struct Vmxnet3_VariableLenConfDesc *pm_descr)
+{
+ VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
+ name, pm_descr->confVer, pm_descr->confLen);
+
+};
+
+static void vmxnet3_update_pm_state(VMXNET3State *s)
+{
+ struct Vmxnet3_VariableLenConfDesc pm_descr;
+
+ pm_descr.confLen =
+ VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
+ pm_descr.confVer =
+ VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
+ pm_descr.confPA =
+ VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
+
+ vmxnet3_dump_conf_descr("PM State", &pm_descr);
+}
+
+static void vmxnet3_update_features(VMXNET3State *s)
+{
+ uint32_t guest_features;
+ int rxcso_supported;
+
+ guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
+ devRead.misc.uptFeatures);
+
+ rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
+ s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
+ s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
+
+ VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
+ s->lro_supported, rxcso_supported,
+ s->rx_vlan_stripping);
+ if (s->peer_has_vhdr) {
+ tap_set_offload(qemu_get_queue(s->nic)->peer,
+ rxcso_supported,
+ s->lro_supported,
+ s->lro_supported,
+ 0,
+ 0);
+ }
+}
+
+static void vmxnet3_activate_device(VMXNET3State *s)
+{
+ int i;
+ static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
+ hwaddr qdescr_table_pa;
+ uint64_t pa;
+ uint32_t size;
+
+ /* Verify configuration consistency */
+ if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {
+ VMW_ERPRN("Device configuration received from driver is invalid");
+ return;
+ }
+
+ vmxnet3_adjust_by_guest_type(s);
+ vmxnet3_update_features(s);
+ vmxnet3_update_pm_state(s);
+ vmxnet3_setup_rx_filtering(s);
+ /* Cache fields from shared memory */
+ s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);
+ VMW_CFPRN("MTU is %u", s->mtu);
+
+ s->max_rx_frags =
+ VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);
+
+ VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
+
+ s->event_int_idx =
+ VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
+ VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
+
+ s->auto_int_masking =
+ VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);
+ VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
+
+ s->txq_num =
+ VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);
+ s->rxq_num =
+ VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
+
+ VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
+ assert(s->txq_num <= VMXNET3_DEVICE_MAX_TX_QUEUES);
+
+ qdescr_table_pa =
+ VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);
+ VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
+
+ /*
+ * Worst-case scenario is a packet that holds all TX rings space so
+ * we calculate total size of all TX rings for max TX fragments number
+ */
+ s->max_tx_frags = 0;
+
+ /* TX queues */
+ for (i = 0; i < s->txq_num; i++) {
+ hwaddr qdescr_pa =
+ qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
+
+ /* Read interrupt number for this TX queue */
+ s->txq_descr[i].intr_idx =
+ VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
+
+ VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
+
+ /* Read rings memory locations for TX queues */
+ pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);
+ size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);
+
+ vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,
+ sizeof(struct Vmxnet3_TxDesc), false);
+ VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
+
+ s->max_tx_frags += size;
+
+ /* TXC ring */
+ pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);
+ size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);
+ vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,
+ sizeof(struct Vmxnet3_TxCompDesc), true);
+ VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
+
+ s->txq_descr[i].tx_stats_pa =
+ qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
+
+ memset(&s->txq_descr[i].txq_stats, 0,
+ sizeof(s->txq_descr[i].txq_stats));
+
+ /* Fill device-managed parameters for queues */
+ VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa,
+ ctrl.txThreshold,
+ VMXNET3_DEF_TX_THRESHOLD);
+ }
+
+ /* Preallocate TX packet wrapper */
+ VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
+ vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
+ vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
+
+ /* Read rings memory locations for RX queues */
+ for (i = 0; i < s->rxq_num; i++) {
+ int j;
+ hwaddr qd_pa =
+ qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
+ i * sizeof(struct Vmxnet3_RxQueueDesc);
+
+ /* Read interrupt number for this RX queue */
+ s->rxq_descr[i].intr_idx =
+ VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
+
+ VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
+
+ /* Read rings memory locations */
+ for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
+ /* RX rings */
+ pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]);
+ size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]);
+ vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size,
+ sizeof(struct Vmxnet3_RxDesc), false);
+ VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
+ i, j, pa, size);
+ }
+
+ /* RXC ring */
+ pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA);
+ size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize);
+ vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size,
+ sizeof(struct Vmxnet3_RxCompDesc), true);
+ VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
+
+ s->rxq_descr[i].rx_stats_pa =
+ qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
+ memset(&s->rxq_descr[i].rxq_stats, 0,
+ sizeof(s->rxq_descr[i].rxq_stats));
+ }
+
+ /* Make sure everything is in place before device activation */
+ smp_wmb();
+
+ vmxnet3_reset_mac(s);
+
+ s->device_active = true;
+}
+
+static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
+{
+ s->last_command = cmd;
+
+ switch (cmd) {
+ case VMXNET3_CMD_GET_PERM_MAC_HI:
+ VMW_CBPRN("Set: Get upper part of permanent MAC");
+ break;
+
+ case VMXNET3_CMD_GET_PERM_MAC_LO:
+ VMW_CBPRN("Set: Get lower part of permanent MAC");
+ break;
+
+ case VMXNET3_CMD_GET_STATS:
+ VMW_CBPRN("Set: Get device statistics");
+ vmxnet3_fill_stats(s);
+ break;
+
+ case VMXNET3_CMD_ACTIVATE_DEV:
+ VMW_CBPRN("Set: Activating vmxnet3 device");
+ vmxnet3_activate_device(s);
+ break;
+
+ case VMXNET3_CMD_UPDATE_RX_MODE:
+ VMW_CBPRN("Set: Update rx mode");
+ vmxnet3_update_rx_mode(s);
+ break;
+
+ case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
+ VMW_CBPRN("Set: Update VLAN filters");
+ vmxnet3_update_vlan_filters(s);
+ break;
+
+ case VMXNET3_CMD_UPDATE_MAC_FILTERS:
+ VMW_CBPRN("Set: Update MAC filters");
+ vmxnet3_update_mcast_filters(s);
+ break;
+
+ case VMXNET3_CMD_UPDATE_FEATURE:
+ VMW_CBPRN("Set: Update features");
+ vmxnet3_update_features(s);
+ break;
+
+ case VMXNET3_CMD_UPDATE_PMCFG:
+ VMW_CBPRN("Set: Update power management config");
+ vmxnet3_update_pm_state(s);
+ break;
+
+ case VMXNET3_CMD_GET_LINK:
+ VMW_CBPRN("Set: Get link");
+ break;
+
+ case VMXNET3_CMD_RESET_DEV:
+ VMW_CBPRN("Set: Reset device");
+ vmxnet3_reset(s);
+ break;
+
+ case VMXNET3_CMD_QUIESCE_DEV:
+ VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
+ vmxnet3_deactivate_device(s);
+ break;
+
+ case VMXNET3_CMD_GET_CONF_INTR:
+ VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
+ break;
+
+ default:
+ VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
+ break;
+ }
+}
+
+static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
+{
+ uint64_t ret;
+
+ switch (s->last_command) {
+ case VMXNET3_CMD_ACTIVATE_DEV:
+ ret = (s->device_active) ? 0 : -1;
+ VMW_CFPRN("Device active: %" PRIx64, ret);
+ break;
+
+ case VMXNET3_CMD_GET_LINK:
+ ret = s->link_status_and_speed;
+ VMW_CFPRN("Link and speed: %" PRIx64, ret);
+ break;
+
+ case VMXNET3_CMD_GET_PERM_MAC_LO:
+ ret = vmxnet3_get_mac_low(&s->perm_mac);
+ break;
+
+ case VMXNET3_CMD_GET_PERM_MAC_HI:
+ ret = vmxnet3_get_mac_high(&s->perm_mac);
+ break;
+
+ case VMXNET3_CMD_GET_CONF_INTR:
+ ret = vmxnet3_get_interrupt_config(s);
+ break;
+
+ default:
+ VMW_WRPRN("Received request for unknown command: %x", s->last_command);
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
+{
+ uint32_t events;
+
+ VMW_CBPRN("Setting events: 0x%x", val);
+ events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
+ VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
+}
+
+static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
+{
+ uint32_t events;
+
+ VMW_CBPRN("Clearing events: 0x%x", val);
+ events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
+ VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
+}
+
+static void
+vmxnet3_io_bar1_write(void *opaque,
+ hwaddr addr,
+ uint64_t val,
+ unsigned size)
+{
+ VMXNET3State *s = opaque;
+
+ switch (addr) {
+ /* Vmxnet3 Revision Report Selection */
+ case VMXNET3_REG_VRRS:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
+ val, size);
+ break;
+
+ /* UPT Version Report Selection */
+ case VMXNET3_REG_UVRS:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
+ val, size);
+ break;
+
+ /* Driver Shared Address Low */
+ case VMXNET3_REG_DSAL:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
+ val, size);
+ /*
+ * Guest driver will first write the low part of the shared
+ * memory address. We save it to temp variable and set the
+ * shared address only after we get the high part
+ */
+ if (0 == val) {
+ s->device_active = false;
+ }
+ s->temp_shared_guest_driver_memory = val;
+ s->drv_shmem = 0;
+ break;
+
+ /* Driver Shared Address High */
+ case VMXNET3_REG_DSAH:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
+ val, size);
+ /*
+ * Set the shared memory between guest driver and device.
+ * We already should have low address part.
+ */
+ s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
+ break;
+
+ /* Command */
+ case VMXNET3_REG_CMD:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
+ val, size);
+ vmxnet3_handle_command(s, val);
+ break;
+
+ /* MAC Address Low */
+ case VMXNET3_REG_MACL:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
+ val, size);
+ s->temp_mac = val;
+ break;
+
+ /* MAC Address High */
+ case VMXNET3_REG_MACH:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
+ val, size);
+ vmxnet3_set_variable_mac(s, val, s->temp_mac);
+ break;
+
+ /* Interrupt Cause Register */
+ case VMXNET3_REG_ICR:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
+ val, size);
+ assert(false);
+ break;
+
+ /* Event Cause Register */
+ case VMXNET3_REG_ECR:
+ VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
+ val, size);
+ vmxnet3_ack_events(s, val);
+ break;
+
+ default:
+ VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
+ addr, val, size);
+ break;
+ }
+}
+
+static uint64_t
+vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
+{
+ VMXNET3State *s = opaque;
+ uint64_t ret = 0;
+
+ switch (addr) {
+ /* Vmxnet3 Revision Report Selection */
+ case VMXNET3_REG_VRRS:
+ VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
+ ret = VMXNET3_DEVICE_REVISION;
+ break;
+
+ /* UPT Version Report Selection */
+ case VMXNET3_REG_UVRS:
+ VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
+ ret = VMXNET3_DEVICE_VERSION;
+ break;
+
+ /* Command */
+ case VMXNET3_REG_CMD:
+ VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
+ ret = vmxnet3_get_command_status(s);
+ break;
+
+ /* MAC Address Low */
+ case VMXNET3_REG_MACL:
+ VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
+ ret = vmxnet3_get_mac_low(&s->conf.macaddr);
+ break;
+
+ /* MAC Address High */
+ case VMXNET3_REG_MACH:
+ VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
+ ret = vmxnet3_get_mac_high(&s->conf.macaddr);
+ break;
+
+ /*
+ * Interrupt Cause Register
+ * Used for legacy interrupts only so interrupt index always 0
+ */
+ case VMXNET3_REG_ICR:
+ VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
+ if (vmxnet3_interrupt_asserted(s, 0)) {
+ vmxnet3_clear_interrupt(s, 0);
+ ret = true;
+ } else {
+ ret = false;
+ }
+ break;
+
+ default:
+ VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
+ break;
+ }
+
+ return ret;
+}
+
+static int
+vmxnet3_can_receive(NetClientState *nc)
+{
+ VMXNET3State *s = qemu_get_nic_opaque(nc);
+ return s->device_active &&
+ VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
+}
+
+static inline bool
+vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
+{
+ uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
+ if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
+ return true;
+ }
+
+ return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
+}
+
+static bool
+vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
+{
+ int i;
+ for (i = 0; i < s->mcast_list_len; i++) {
+ if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
+ return true;
+ }
+ }
+ return false;
+}
+
+static bool
+vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
+ size_t size)
+{
+ struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
+
+ if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
+ return true;
+ }
+
+ if (!vmxnet3_is_registered_vlan(s, data)) {
+ return false;
+ }
+
+ switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
+ case ETH_PKT_UCAST:
+ if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
+ return false;
+ }
+ if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
+ return false;
+ }
+ break;
+
+ case ETH_PKT_BCAST:
+ if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
+ return false;
+ }
+ break;
+
+ case ETH_PKT_MCAST:
+ if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
+ return true;
+ }
+ if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
+ return false;
+ }
+ if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
+ return false;
+ }
+ break;
+
+ default:
+ assert(false);
+ }
+
+ return true;
+}
+
+static ssize_t
+vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
+{
+ VMXNET3State *s = qemu_get_nic_opaque(nc);
+ size_t bytes_indicated;
+
+ if (!vmxnet3_can_receive(nc)) {
+ VMW_PKPRN("Cannot receive now");
+ return -1;
+ }
+
+ if (s->peer_has_vhdr) {
+ vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
+ buf += sizeof(struct virtio_net_hdr);
+ size -= sizeof(struct virtio_net_hdr);
+ }
+
+ vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
+ get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
+
+ if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
+ vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
+ bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
+ if (bytes_indicated < size) {
+ VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size);
+ }
+ } else {
+ VMW_PKPRN("Packet dropped by RX filter");
+ bytes_indicated = size;
+ }
+
+ assert(size > 0);
+ assert(bytes_indicated != 0);
+ return bytes_indicated;
+}
+
+static void vmxnet3_cleanup(NetClientState *nc)
+{
+ VMXNET3State *s = qemu_get_nic_opaque(nc);
+ s->nic = NULL;
+}
+
+static void vmxnet3_set_link_status(NetClientState *nc)
+{
+ VMXNET3State *s = qemu_get_nic_opaque(nc);
+
+ if (nc->link_down) {
+ s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
+ } else {
+ s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
+ }
+
+ vmxnet3_set_events(s, VMXNET3_ECR_LINK);
+ vmxnet3_trigger_interrupt(s, s->event_int_idx);
+}
+
+static NetClientInfo net_vmxnet3_info = {
+ .type = NET_CLIENT_OPTIONS_KIND_NIC,
+ .size = sizeof(NICState),
+ .can_receive = vmxnet3_can_receive,
+ .receive = vmxnet3_receive,
+ .cleanup = vmxnet3_cleanup,
+ .link_status_changed = vmxnet3_set_link_status,
+};
+
+static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
+{
+ NetClientState *peer = qemu_get_queue(s->nic)->peer;
+
+ if ((NULL != peer) &&
+ (peer->info->type == NET_CLIENT_OPTIONS_KIND_TAP) &&
+ tap_has_vnet_hdr(peer)) {
+ return true;
+ }
+
+ VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
+ return false;
+}
+
+static void vmxnet3_net_uninit(VMXNET3State *s)
+{
+ g_free(s->mcast_list);
+ vmxnet_tx_pkt_reset(s->tx_pkt);
+ vmxnet_tx_pkt_uninit(s->tx_pkt);
+ vmxnet_rx_pkt_uninit(s->rx_pkt);
+ qemu_del_net_client(qemu_get_queue(s->nic));
+}
+
+static void vmxnet3_net_init(VMXNET3State *s)
+{
+ DeviceState *d = DEVICE(s);
+
+ VMW_CBPRN("vmxnet3_net_init called...");
+
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
+
+ /* Windows guest will query the address that was set on init */
+ memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
+
+ s->mcast_list = NULL;
+ s->mcast_list_len = 0;
+
+ s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
+
+ VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
+
+ s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
+ object_get_typename(OBJECT(s)),
+ d->id, s);
+
+ s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
+ s->tx_sop = true;
+ s->skip_current_tx_pkt = false;
+ s->tx_pkt = NULL;
+ s->rx_pkt = NULL;
+ s->rx_vlan_stripping = false;
+ s->lro_supported = false;
+
+ if (s->peer_has_vhdr) {
+ tap_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
+ sizeof(struct virtio_net_hdr));
+
+ tap_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
+ }
+
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
+}
+
+static void
+vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+ int i;
+ for (i = 0; i < num_vectors; i++) {
+ msix_vector_unuse(d, i);
+ }
+}
+
+static bool
+vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+ int i;
+ for (i = 0; i < num_vectors; i++) {
+ int res = msix_vector_use(d, i);
+ if (0 > res) {
+ VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
+ vmxnet3_unuse_msix_vectors(s, i);
+ return false;
+ }
+ }
+ return true;
+}
+
+static bool
+vmxnet3_init_msix(VMXNET3State *s)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+ int res = msix_init(d, VMXNET3_MAX_INTRS,
+ &s->msix_bar,
+ VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
+ &s->msix_bar,
+ VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
+ 0);
+
+ if (0 > res) {
+ VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
+ s->msix_used = false;
+ } else {
+ if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
+ VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
+ msix_uninit(d, &s->msix_bar, &s->msix_bar);
+ s->msix_used = false;
+ } else {
+ s->msix_used = true;
+ }
+ }
+ return s->msix_used;
+}
+
+static void
+vmxnet3_cleanup_msix(VMXNET3State *s)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+
+ if (s->msix_used) {
+ msix_vector_unuse(d, VMXNET3_MAX_INTRS);
+ msix_uninit(d, &s->msix_bar, &s->msix_bar);
+ }
+}
+
+#define VMXNET3_MSI_NUM_VECTORS (1)
+#define VMXNET3_MSI_OFFSET (0x50)
+#define VMXNET3_USE_64BIT (true)
+#define VMXNET3_PER_VECTOR_MASK (false)
+
+static bool
+vmxnet3_init_msi(VMXNET3State *s)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+ int res;
+
+ res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MSI_NUM_VECTORS,
+ VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
+ if (0 > res) {
+ VMW_WRPRN("Failed to initialize MSI, error %d", res);
+ s->msi_used = false;
+ } else {
+ s->msi_used = true;
+ }
+
+ return s->msi_used;
+}
+
+static void
+vmxnet3_cleanup_msi(VMXNET3State *s)
+{
+ PCIDevice *d = PCI_DEVICE(s);
+
+ if (s->msi_used) {
+ msi_uninit(d);
+ }
+}
+
+static void
+vmxnet3_msix_save(QEMUFile *f, void *opaque)
+{
+ PCIDevice *d = PCI_DEVICE(opaque);
+ msix_save(d, f);
+}
+
+static int
+vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
+{
+ PCIDevice *d = PCI_DEVICE(opaque);
+ msix_load(d, f);
+ return 0;
+}
+
+static const MemoryRegionOps b0_ops = {
+ .read = vmxnet3_io_bar0_read,
+ .write = vmxnet3_io_bar0_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static const MemoryRegionOps b1_ops = {
+ .read = vmxnet3_io_bar1_read,
+ .write = vmxnet3_io_bar1_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static int vmxnet3_pci_init(PCIDevice *pci_dev)
+{
+ DeviceState *dev = DEVICE(pci_dev);
+ VMXNET3State *s = VMXNET3(pci_dev);
+
+ VMW_CBPRN("Starting init...");
+
+ memory_region_init_io(&s->bar0, &b0_ops, s,
+ "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
+ pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
+
+ memory_region_init_io(&s->bar1, &b1_ops, s,
+ "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
+ pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
+
+ memory_region_init(&s->msix_bar, "vmxnet3-msix-bar",
+ VMXNET3_MSIX_BAR_SIZE);
+ pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
+
+ vmxnet3_reset_interrupt_states(s);
+
+ /* Interrupt pin A */
+ pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
+
+ if (!vmxnet3_init_msix(s)) {
+ VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
+ }
+
+ if (!vmxnet3_init_msi(s)) {
+ VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
+ }
+
+ vmxnet3_net_init(s);
+
+ register_savevm(dev, "vmxnet3-msix", -1, 1,
+ vmxnet3_msix_save, vmxnet3_msix_load, s);
+
+ add_boot_device_path(s->conf.bootindex, dev, "/ethernet-phy@0");
+
+ return 0;
+}
+
+
+static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
+{
+ DeviceState *dev = DEVICE(pci_dev);
+ VMXNET3State *s = VMXNET3(pci_dev);
+
+ VMW_CBPRN("Starting uninit...");
+
+ unregister_savevm(dev, "vmxnet3-msix", s);
+
+ vmxnet3_net_uninit(s);
+
+ vmxnet3_cleanup_msix(s);
+
+ vmxnet3_cleanup_msi(s);
+
+ memory_region_destroy(&s->bar0);
+ memory_region_destroy(&s->bar1);
+ memory_region_destroy(&s->msix_bar);
+}
+
+static void vmxnet3_qdev_reset(DeviceState *dev)
+{
+ PCIDevice *d = PCI_DEVICE(dev);
+ VMXNET3State *s = VMXNET3(d);
+
+ VMW_CBPRN("Starting QDEV reset...");
+ vmxnet3_reset(s);
+}
+
+static bool vmxnet3_mc_list_needed(void *opaque)
+{
+ return true;
+}
+
+static int vmxnet3_mcast_list_pre_load(void *opaque)
+{
+ VMXNET3State *s = opaque;
+
+ s->mcast_list = g_malloc(s->mcast_list_buff_size);
+
+ return 0;
+}
+
+
+static void vmxnet3_pre_save(void *opaque)
+{
+ VMXNET3State *s = opaque;
+
+ s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
+}
+
+static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
+ .name = "vmxnet3/mcast_list",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .pre_load = vmxnet3_mcast_list_pre_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0,
+ mcast_list_buff_size),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r)
+{
+ r->pa = qemu_get_be64(f);
+ r->size = qemu_get_be32(f);
+ r->cell_size = qemu_get_be32(f);
+ r->next = qemu_get_be32(f);
+ r->gen = qemu_get_byte(f);
+}
+
+static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r)
+{
+ qemu_put_be64(f, r->pa);
+ qemu_put_be32(f, r->size);
+ qemu_put_be32(f, r->cell_size);
+ qemu_put_be32(f, r->next);
+ qemu_put_byte(f, r->gen);
+}
+
+static void vmxnet3_get_tx_stats_from_file(QEMUFile *f,
+ struct UPT1_TxStats *tx_stat)
+{
+ tx_stat->TSOPktsTxOK = qemu_get_be64(f);
+ tx_stat->TSOBytesTxOK = qemu_get_be64(f);
+ tx_stat->ucastPktsTxOK = qemu_get_be64(f);
+ tx_stat->ucastBytesTxOK = qemu_get_be64(f);
+ tx_stat->mcastPktsTxOK = qemu_get_be64(f);
+ tx_stat->mcastBytesTxOK = qemu_get_be64(f);
+ tx_stat->bcastPktsTxOK = qemu_get_be64(f);
+ tx_stat->bcastBytesTxOK = qemu_get_be64(f);
+ tx_stat->pktsTxError = qemu_get_be64(f);
+ tx_stat->pktsTxDiscard = qemu_get_be64(f);
+}
+
+static void vmxnet3_put_tx_stats_to_file(QEMUFile *f,
+ struct UPT1_TxStats *tx_stat)
+{
+ qemu_put_be64(f, tx_stat->TSOPktsTxOK);
+ qemu_put_be64(f, tx_stat->TSOBytesTxOK);
+ qemu_put_be64(f, tx_stat->ucastPktsTxOK);
+ qemu_put_be64(f, tx_stat->ucastBytesTxOK);
+ qemu_put_be64(f, tx_stat->mcastPktsTxOK);
+ qemu_put_be64(f, tx_stat->mcastBytesTxOK);
+ qemu_put_be64(f, tx_stat->bcastPktsTxOK);
+ qemu_put_be64(f, tx_stat->bcastBytesTxOK);
+ qemu_put_be64(f, tx_stat->pktsTxError);
+ qemu_put_be64(f, tx_stat->pktsTxDiscard);
+}
+
+static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size)
+{
+ Vmxnet3TxqDescr *r = pv;
+
+ vmxnet3_get_ring_from_file(f, &r->tx_ring);
+ vmxnet3_get_ring_from_file(f, &r->comp_ring);
+ r->intr_idx = qemu_get_byte(f);
+ r->tx_stats_pa = qemu_get_be64(f);
+
+ vmxnet3_get_tx_stats_from_file(f, &r->txq_stats);
+
+ return 0;
+}
+
+static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size)
+{
+ Vmxnet3TxqDescr *r = pv;
+
+ vmxnet3_put_ring_to_file(f, &r->tx_ring);
+ vmxnet3_put_ring_to_file(f, &r->comp_ring);
+ qemu_put_byte(f, r->intr_idx);
+ qemu_put_be64(f, r->tx_stats_pa);
+ vmxnet3_put_tx_stats_to_file(f, &r->txq_stats);
+}
+
+const VMStateInfo txq_descr_info = {
+ .name = "txq_descr",
+ .get = vmxnet3_get_txq_descr,
+ .put = vmxnet3_put_txq_descr
+};
+
+static void vmxnet3_get_rx_stats_from_file(QEMUFile *f,
+ struct UPT1_RxStats *rx_stat)
+{
+ rx_stat->LROPktsRxOK = qemu_get_be64(f);
+ rx_stat->LROBytesRxOK = qemu_get_be64(f);
+ rx_stat->ucastPktsRxOK = qemu_get_be64(f);
+ rx_stat->ucastBytesRxOK = qemu_get_be64(f);
+ rx_stat->mcastPktsRxOK = qemu_get_be64(f);
+ rx_stat->mcastBytesRxOK = qemu_get_be64(f);
+ rx_stat->bcastPktsRxOK = qemu_get_be64(f);
+ rx_stat->bcastBytesRxOK = qemu_get_be64(f);
+ rx_stat->pktsRxOutOfBuf = qemu_get_be64(f);
+ rx_stat->pktsRxError = qemu_get_be64(f);
+}
+
+static void vmxnet3_put_rx_stats_to_file(QEMUFile *f,
+ struct UPT1_RxStats *rx_stat)
+{
+ qemu_put_be64(f, rx_stat->LROPktsRxOK);
+ qemu_put_be64(f, rx_stat->LROBytesRxOK);
+ qemu_put_be64(f, rx_stat->ucastPktsRxOK);
+ qemu_put_be64(f, rx_stat->ucastBytesRxOK);
+ qemu_put_be64(f, rx_stat->mcastPktsRxOK);
+ qemu_put_be64(f, rx_stat->mcastBytesRxOK);
+ qemu_put_be64(f, rx_stat->bcastPktsRxOK);
+ qemu_put_be64(f, rx_stat->bcastBytesRxOK);
+ qemu_put_be64(f, rx_stat->pktsRxOutOfBuf);
+ qemu_put_be64(f, rx_stat->pktsRxError);
+}
+
+static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size)
+{
+ Vmxnet3RxqDescr *r = pv;
+ int i;
+
+ for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
+ vmxnet3_get_ring_from_file(f, &r->rx_ring[i]);
+ }
+
+ vmxnet3_get_ring_from_file(f, &r->comp_ring);
+ r->intr_idx = qemu_get_byte(f);
+ r->rx_stats_pa = qemu_get_be64(f);
+
+ vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats);
+
+ return 0;
+}
+
+static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size)
+{
+ Vmxnet3RxqDescr *r = pv;
+ int i;
+
+ for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
+ vmxnet3_put_ring_to_file(f, &r->rx_ring[i]);
+ }
+
+ vmxnet3_put_ring_to_file(f, &r->comp_ring);
+ qemu_put_byte(f, r->intr_idx);
+ qemu_put_be64(f, r->rx_stats_pa);
+ vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats);
+}
+
+static int vmxnet3_post_load(void *opaque, int version_id)
+{
+ VMXNET3State *s = opaque;
+ PCIDevice *d = PCI_DEVICE(s);
+
+ vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
+ vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
+
+ if (s->msix_used) {
+ if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
+ VMW_WRPRN("Failed to re-use MSI-X vectors");
+ msix_uninit(d, &s->msix_bar, &s->msix_bar);
+ s->msix_used = false;
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+const VMStateInfo rxq_descr_info = {
+ .name = "rxq_descr",
+ .get = vmxnet3_get_rxq_descr,
+ .put = vmxnet3_put_rxq_descr
+};
+
+static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size)
+{
+ Vmxnet3IntState *r = pv;
+
+ r->is_masked = qemu_get_byte(f);
+ r->is_pending = qemu_get_byte(f);
+ r->is_asserted = qemu_get_byte(f);
+
+ return 0;
+}
+
+static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size)
+{
+ Vmxnet3IntState *r = pv;
+
+ qemu_put_byte(f, r->is_masked);
+ qemu_put_byte(f, r->is_pending);
+ qemu_put_byte(f, r->is_asserted);
+}
+
+const VMStateInfo int_state_info = {
+ .name = "int_state",
+ .get = vmxnet3_get_int_state,
+ .put = vmxnet3_put_int_state
+};
+
+static const VMStateDescription vmstate_vmxnet3 = {
+ .name = "vmxnet3",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .pre_save = vmxnet3_pre_save,
+ .post_load = vmxnet3_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
+ VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
+ VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
+ VMSTATE_BOOL(lro_supported, VMXNET3State),
+ VMSTATE_UINT32(rx_mode, VMXNET3State),
+ VMSTATE_UINT32(mcast_list_len, VMXNET3State),
+ VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
+ VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
+ VMSTATE_UINT32(mtu, VMXNET3State),
+ VMSTATE_UINT16(max_rx_frags, VMXNET3State),
+ VMSTATE_UINT32(max_tx_frags, VMXNET3State),
+ VMSTATE_UINT8(event_int_idx, VMXNET3State),
+ VMSTATE_BOOL(auto_int_masking, VMXNET3State),
+ VMSTATE_UINT8(txq_num, VMXNET3State),
+ VMSTATE_UINT8(rxq_num, VMXNET3State),
+ VMSTATE_UINT32(device_active, VMXNET3State),
+ VMSTATE_UINT32(last_command, VMXNET3State),
+ VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
+ VMSTATE_UINT32(temp_mac, VMXNET3State),
+ VMSTATE_UINT64(drv_shmem, VMXNET3State),
+ VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
+
+ VMSTATE_ARRAY(txq_descr, VMXNET3State,
+ VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info,
+ Vmxnet3TxqDescr),
+ VMSTATE_ARRAY(rxq_descr, VMXNET3State,
+ VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info,
+ Vmxnet3RxqDescr),
+ VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS,
+ 0, int_state_info, Vmxnet3IntState),
+
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (VMStateSubsection[]) {
+ {
+ .vmsd = &vmxstate_vmxnet3_mcast_list,
+ .needed = vmxnet3_mc_list_needed
+ },
+ {
+ /* empty element. */
+ }
+ }
+};
+
+static void
+vmxnet3_write_config(PCIDevice *pci_dev, uint32_t addr, uint32_t val, int len)
+{
+ pci_default_write_config(pci_dev, addr, val, len);
+ msix_write_config(pci_dev, addr, val, len);
+ msi_write_config(pci_dev, addr, val, len);
+}
+
+static Property vmxnet3_properties[] = {
+ DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void vmxnet3_class_init(ObjectClass *class, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(class);
+ PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
+
+ c->init = vmxnet3_pci_init;
+ c->exit = vmxnet3_pci_uninit;
+ c->vendor_id = PCI_VENDOR_ID_VMWARE;
+ c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
+ c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
+ c->class_id = PCI_CLASS_NETWORK_ETHERNET;
+ c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
+ c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
+ c->config_write = vmxnet3_write_config,
+ dc->desc = "VMWare Paravirtualized Ethernet v3";
+ dc->reset = vmxnet3_qdev_reset;
+ dc->vmsd = &vmstate_vmxnet3;
+ dc->props = vmxnet3_properties;
+}
+
+static const TypeInfo vmxnet3_info = {
+ .name = TYPE_VMXNET3,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(VMXNET3State),
+ .class_init = vmxnet3_class_init,
+};
+
+static void vmxnet3_register_types(void)
+{
+ VMW_CBPRN("vmxnet3_register_types called...");
+ type_register_static(&vmxnet3_info);
+}
+
+type_init(vmxnet3_register_types)
diff --git a/hw/vmxnet3.h b/hw/vmxnet3.h
new file mode 100644
index 0000000..7db0c8f
--- /dev/null
+++ b/hw/vmxnet3.h
@@ -0,0 +1,760 @@
+/*
+ * QEMU VMWARE VMXNET3 paravirtual NIC interface definitions
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef _QEMU_VMXNET3_H
+#define _QEMU_VMXNET3_H
+
+#define VMXNET3_DEVICE_MAX_TX_QUEUES 8
+#define VMXNET3_DEVICE_MAX_RX_QUEUES 8 /* Keep this value as a power of 2 */
+
+/*
+ * VMWARE headers we got from Linux kernel do not fully comply QEMU coding
+ * standards in sense of types and defines used.
+ * Since we didn't want to change VMWARE code, following set of typedefs
+ * and defines needed to compile these headers with QEMU introduced.
+ */
+#define u64 uint64_t
+#define u32 uint32_t
+#define u16 uint16_t
+#define u8 uint8_t
+#define __le16 uint16_t
+#define __le32 uint32_t
+#define __le64 uint64_t
+#define __packed QEMU_PACKED
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define const_cpu_to_le64(x) bswap_64(x)
+#define __BIG_ENDIAN_BITFIELD
+#else
+#define const_cpu_to_le64(x) (x)
+#endif
+
+/*
+ * Following is an interface definition for
+ * VMXNET3 device as provided by VMWARE
+ * See original copyright from Linux kernel v3.2.8
+ * header file drivers/net/vmxnet3/vmxnet3_defs.h below.
+ */
+
+/*
+ * Linux driver for VMware's vmxnet3 ethernet NIC.
+ *
+ * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License and no later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
+ *
+ */
+
+struct UPT1_TxStats {
+ u64 TSOPktsTxOK; /* TSO pkts post-segmentation */
+ u64 TSOBytesTxOK;
+ u64 ucastPktsTxOK;
+ u64 ucastBytesTxOK;
+ u64 mcastPktsTxOK;
+ u64 mcastBytesTxOK;
+ u64 bcastPktsTxOK;
+ u64 bcastBytesTxOK;
+ u64 pktsTxError;
+ u64 pktsTxDiscard;
+};
+
+struct UPT1_RxStats {
+ u64 LROPktsRxOK; /* LRO pkts */
+ u64 LROBytesRxOK; /* bytes from LRO pkts */
+ /* the following counters are for pkts from the wire, i.e., pre-LRO */
+ u64 ucastPktsRxOK;
+ u64 ucastBytesRxOK;
+ u64 mcastPktsRxOK;
+ u64 mcastBytesRxOK;
+ u64 bcastPktsRxOK;
+ u64 bcastBytesRxOK;
+ u64 pktsRxOutOfBuf;
+ u64 pktsRxError;
+};
+
+/* interrupt moderation level */
+enum {
+ UPT1_IML_NONE = 0, /* no interrupt moderation */
+ UPT1_IML_HIGHEST = 7, /* least intr generated */
+ UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */
+};
+/* values for UPT1_RSSConf.hashFunc */
+enum {
+ UPT1_RSS_HASH_TYPE_NONE = 0x0,
+ UPT1_RSS_HASH_TYPE_IPV4 = 0x01,
+ UPT1_RSS_HASH_TYPE_TCP_IPV4 = 0x02,
+ UPT1_RSS_HASH_TYPE_IPV6 = 0x04,
+ UPT1_RSS_HASH_TYPE_TCP_IPV6 = 0x08,
+};
+
+enum {
+ UPT1_RSS_HASH_FUNC_NONE = 0x0,
+ UPT1_RSS_HASH_FUNC_TOEPLITZ = 0x01,
+};
+
+#define UPT1_RSS_MAX_KEY_SIZE 40
+#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
+
+struct UPT1_RSSConf {
+ u16 hashType;
+ u16 hashFunc;
+ u16 hashKeySize;
+ u16 indTableSize;
+ u8 hashKey[UPT1_RSS_MAX_KEY_SIZE];
+ u8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE];
+};
+
+/* features */
+enum {
+ UPT1_F_RXCSUM = const_cpu_to_le64(0x0001), /* rx csum verification */
+ UPT1_F_RSS = const_cpu_to_le64(0x0002),
+ UPT1_F_RXVLAN = const_cpu_to_le64(0x0004), /* VLAN tag stripping */
+ UPT1_F_LRO = const_cpu_to_le64(0x0008),
+};
+
+/* all registers are 32 bit wide */
+/* BAR 1 */
+enum {
+ VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
+ VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
+ VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
+ VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
+ VMXNET3_REG_CMD = 0x20, /* Command */
+ VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
+ VMXNET3_REG_MACH = 0x30, /* MAC Address High */
+ VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
+ VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
+};
+
+/* BAR 0 */
+enum {
+ VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
+ VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
+ VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
+ VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
+};
+
+#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
+#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
+
+#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
+#define VMXNET3_REG_ALIGN_MASK 0x7
+
+/* I/O Mapped access to registers */
+#define VMXNET3_IO_TYPE_PT 0
+#define VMXNET3_IO_TYPE_VD 1
+#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
+#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
+#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
+
+enum {
+ VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
+ VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, /* 0xCAFE0000 */
+ VMXNET3_CMD_QUIESCE_DEV, /* 0xCAFE0001 */
+ VMXNET3_CMD_RESET_DEV, /* 0xCAFE0002 */
+ VMXNET3_CMD_UPDATE_RX_MODE, /* 0xCAFE0003 */
+ VMXNET3_CMD_UPDATE_MAC_FILTERS, /* 0xCAFE0004 */
+ VMXNET3_CMD_UPDATE_VLAN_FILTERS, /* 0xCAFE0005 */
+ VMXNET3_CMD_UPDATE_RSSIDT, /* 0xCAFE0006 */
+ VMXNET3_CMD_UPDATE_IML, /* 0xCAFE0007 */
+ VMXNET3_CMD_UPDATE_PMCFG, /* 0xCAFE0008 */
+ VMXNET3_CMD_UPDATE_FEATURE, /* 0xCAFE0009 */
+ VMXNET3_CMD_LOAD_PLUGIN, /* 0xCAFE000A */
+
+ VMXNET3_CMD_FIRST_GET = 0xF00D0000,
+ VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, /* 0xF00D0000 */
+ VMXNET3_CMD_GET_STATS, /* 0xF00D0001 */
+ VMXNET3_CMD_GET_LINK, /* 0xF00D0002 */
+ VMXNET3_CMD_GET_PERM_MAC_LO, /* 0xF00D0003 */
+ VMXNET3_CMD_GET_PERM_MAC_HI, /* 0xF00D0004 */
+ VMXNET3_CMD_GET_DID_LO, /* 0xF00D0005 */
+ VMXNET3_CMD_GET_DID_HI, /* 0xF00D0006 */
+ VMXNET3_CMD_GET_DEV_EXTRA_INFO, /* 0xF00D0007 */
+ VMXNET3_CMD_GET_CONF_INTR /* 0xF00D0008 */
+};
+
+/*
+ * Little Endian layout of bitfields -
+ * Byte 0 : 7.....len.....0
+ * Byte 1 : rsvd gen 13.len.8
+ * Byte 2 : 5.msscof.0 ext1 dtype
+ * Byte 3 : 13...msscof...6
+ *
+ * Big Endian layout of bitfields -
+ * Byte 0: 13...msscof...6
+ * Byte 1 : 5.msscof.0 ext1 dtype
+ * Byte 2 : rsvd gen 13.len.8
+ * Byte 3 : 7.....len.....0
+ *
+ * Thus, le32_to_cpu on the dword will allow the big endian driver to read
+ * the bit fields correctly. And cpu_to_le32 will convert bitfields
+ * bit fields written by big endian driver to format required by device.
+ */
+
+struct Vmxnet3_TxDesc {
+ __le64 addr;
+
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 msscof:14; /* MSS, checksum offset, flags */
+ u32 ext1:1;
+ u32 dtype:1; /* descriptor type */
+ u32 rsvd:1;
+ u32 gen:1; /* generation bit */
+ u32 len:14;
+#else
+ u32 len:14;
+ u32 gen:1; /* generation bit */
+ u32 rsvd:1;
+ u32 dtype:1; /* descriptor type */
+ u32 ext1:1;
+ u32 msscof:14; /* MSS, checksum offset, flags */
+#endif /* __BIG_ENDIAN_BITFIELD */
+
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 tci:16; /* Tag to Insert */
+ u32 ti:1; /* VLAN Tag Insertion */
+ u32 ext2:1;
+ u32 cq:1; /* completion request */
+ u32 eop:1; /* End Of Packet */
+ u32 om:2; /* offload mode */
+ u32 hlen:10; /* header len */
+#else
+ u32 hlen:10; /* header len */
+ u32 om:2; /* offload mode */
+ u32 eop:1; /* End Of Packet */
+ u32 cq:1; /* completion request */
+ u32 ext2:1;
+ u32 ti:1; /* VLAN Tag Insertion */
+ u32 tci:16; /* Tag to Insert */
+#endif /* __BIG_ENDIAN_BITFIELD */
+};
+
+/* TxDesc.OM values */
+#define VMXNET3_OM_NONE 0
+#define VMXNET3_OM_CSUM 2
+#define VMXNET3_OM_TSO 3
+
+/* fields in TxDesc we access w/o using bit fields */
+#define VMXNET3_TXD_EOP_SHIFT 12
+#define VMXNET3_TXD_CQ_SHIFT 13
+#define VMXNET3_TXD_GEN_SHIFT 14
+#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
+#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
+
+#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
+#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
+#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
+
+#define VMXNET3_HDR_COPY_SIZE 128
+
+
+struct Vmxnet3_TxDataDesc {
+ u8 data[VMXNET3_HDR_COPY_SIZE];
+};
+
+#define VMXNET3_TCD_GEN_SHIFT 31
+#define VMXNET3_TCD_GEN_SIZE 1
+#define VMXNET3_TCD_TXIDX_SHIFT 0
+#define VMXNET3_TCD_TXIDX_SIZE 12
+#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
+
+struct Vmxnet3_TxCompDesc {
+ u32 txdIdx:12; /* Index of the EOP TxDesc */
+ u32 ext1:20;
+
+ __le32 ext2;
+ __le32 ext3;
+
+ u32 rsvd:24;
+ u32 type:7; /* completion type */
+ u32 gen:1; /* generation bit */
+};
+
+struct Vmxnet3_RxDesc {
+ __le64 addr;
+
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 gen:1; /* Generation bit */
+ u32 rsvd:15;
+ u32 dtype:1; /* Descriptor type */
+ u32 btype:1; /* Buffer Type */
+ u32 len:14;
+#else
+ u32 len:14;
+ u32 btype:1; /* Buffer Type */
+ u32 dtype:1; /* Descriptor type */
+ u32 rsvd:15;
+ u32 gen:1; /* Generation bit */
+#endif
+ u32 ext1;
+};
+
+/* values of RXD.BTYPE */
+#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
+#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
+
+/* fields in RxDesc we access w/o using bit fields */
+#define VMXNET3_RXD_BTYPE_SHIFT 14
+#define VMXNET3_RXD_GEN_SHIFT 31
+
+struct Vmxnet3_RxCompDesc {
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 ext2:1;
+ u32 cnc:1; /* Checksum Not Calculated */
+ u32 rssType:4; /* RSS hash type used */
+ u32 rqID:10; /* rx queue/ring ID */
+ u32 sop:1; /* Start of Packet */
+ u32 eop:1; /* End of Packet */
+ u32 ext1:2;
+ u32 rxdIdx:12; /* Index of the RxDesc */
+#else
+ u32 rxdIdx:12; /* Index of the RxDesc */
+ u32 ext1:2;
+ u32 eop:1; /* End of Packet */
+ u32 sop:1; /* Start of Packet */
+ u32 rqID:10; /* rx queue/ring ID */
+ u32 rssType:4; /* RSS hash type used */
+ u32 cnc:1; /* Checksum Not Calculated */
+ u32 ext2:1;
+#endif /* __BIG_ENDIAN_BITFIELD */
+
+ __le32 rssHash; /* RSS hash value */
+
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 tci:16; /* Tag stripped */
+ u32 ts:1; /* Tag is stripped */
+ u32 err:1; /* Error */
+ u32 len:14; /* data length */
+#else
+ u32 len:14; /* data length */
+ u32 err:1; /* Error */
+ u32 ts:1; /* Tag is stripped */
+ u32 tci:16; /* Tag stripped */
+#endif /* __BIG_ENDIAN_BITFIELD */
+
+
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 gen:1; /* generation bit */
+ u32 type:7; /* completion type */
+ u32 fcs:1; /* Frame CRC correct */
+ u32 frg:1; /* IP Fragment */
+ u32 v4:1; /* IPv4 */
+ u32 v6:1; /* IPv6 */
+ u32 ipc:1; /* IP Checksum Correct */
+ u32 tcp:1; /* TCP packet */
+ u32 udp:1; /* UDP packet */
+ u32 tuc:1; /* TCP/UDP Checksum Correct */
+ u32 csum:16;
+#else
+ u32 csum:16;
+ u32 tuc:1; /* TCP/UDP Checksum Correct */
+ u32 udp:1; /* UDP packet */
+ u32 tcp:1; /* TCP packet */
+ u32 ipc:1; /* IP Checksum Correct */
+ u32 v6:1; /* IPv6 */
+ u32 v4:1; /* IPv4 */
+ u32 frg:1; /* IP Fragment */
+ u32 fcs:1; /* Frame CRC correct */
+ u32 type:7; /* completion type */
+ u32 gen:1; /* generation bit */
+#endif /* __BIG_ENDIAN_BITFIELD */
+};
+
+/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
+#define VMXNET3_RCD_TUC_SHIFT 16
+#define VMXNET3_RCD_IPC_SHIFT 19
+
+/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
+#define VMXNET3_RCD_TYPE_SHIFT 56
+#define VMXNET3_RCD_GEN_SHIFT 63
+
+/* csum OK for TCP/UDP pkts over IP */
+#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
+ 1 << VMXNET3_RCD_IPC_SHIFT)
+#define VMXNET3_TXD_GEN_SIZE 1
+#define VMXNET3_TXD_EOP_SIZE 1
+
+/* value of RxCompDesc.rssType */
+enum {
+ VMXNET3_RCD_RSS_TYPE_NONE = 0,
+ VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
+ VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
+ VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
+ VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
+};
+
+
+/* a union for accessing all cmd/completion descriptors */
+union Vmxnet3_GenericDesc {
+ __le64 qword[2];
+ __le32 dword[4];
+ __le16 word[8];
+ struct Vmxnet3_TxDesc txd;
+ struct Vmxnet3_RxDesc rxd;
+ struct Vmxnet3_TxCompDesc tcd;
+ struct Vmxnet3_RxCompDesc rcd;
+};
+
+#define VMXNET3_INIT_GEN 1
+
+/* Max size of a single tx buffer */
+#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
+
+/* # of tx desc needed for a tx buffer size */
+#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
+ VMXNET3_MAX_TX_BUF_SIZE)
+
+/* max # of tx descs for a non-tso pkt */
+#define VMXNET3_MAX_TXD_PER_PKT 16
+
+/* Max size of a single rx buffer */
+#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
+/* Minimum size of a type 0 buffer */
+#define VMXNET3_MIN_T0_BUF_SIZE 128
+#define VMXNET3_MAX_CSUM_OFFSET 1024
+
+/* Ring base address alignment */
+#define VMXNET3_RING_BA_ALIGN 512
+#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
+
+/* Ring size must be a multiple of 32 */
+#define VMXNET3_RING_SIZE_ALIGN 32
+#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
+
+/* Max ring size */
+#define VMXNET3_TX_RING_MAX_SIZE 4096
+#define VMXNET3_TC_RING_MAX_SIZE 4096
+#define VMXNET3_RX_RING_MAX_SIZE 4096
+#define VMXNET3_RC_RING_MAX_SIZE 8192
+
+/* a list of reasons for queue stop */
+
+enum {
+ VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
+ VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
+ VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
+ VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
+ VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
+ VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
+ VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
+ VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
+};
+
+/* completion descriptor types */
+#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
+#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
+
+enum {
+ VMXNET3_GOS_BITS_UNK = 0, /* unknown */
+ VMXNET3_GOS_BITS_32 = 1,
+ VMXNET3_GOS_BITS_64 = 2,
+};
+
+#define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
+#define VMXNET3_GOS_TYPE_LINUX 1
+#define VMXNET3_GOS_TYPE_WIN 2
+#define VMXNET3_GOS_TYPE_SOLARIS 3
+#define VMXNET3_GOS_TYPE_FREEBSD 4
+#define VMXNET3_GOS_TYPE_PXE 5
+
+struct Vmxnet3_GOSInfo {
+#ifdef __BIG_ENDIAN_BITFIELD
+ u32 gosMisc:10; /* other info about gos */
+ u32 gosVer:16; /* gos version */
+ u32 gosType:4; /* which guest */
+ u32 gosBits:2; /* 32-bit or 64-bit? */
+#else
+ u32 gosBits:2; /* 32-bit or 64-bit? */
+ u32 gosType:4; /* which guest */
+ u32 gosVer:16; /* gos version */
+ u32 gosMisc:10; /* other info about gos */
+#endif /* __BIG_ENDIAN_BITFIELD */
+};
+
+struct Vmxnet3_DriverInfo {
+ __le32 version;
+ struct Vmxnet3_GOSInfo gos;
+ __le32 vmxnet3RevSpt;
+ __le32 uptVerSpt;
+};
+
+
+#define VMXNET3_REV1_MAGIC 0xbabefee1
+
+/*
+ * QueueDescPA must be 128 bytes aligned. It points to an array of
+ * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
+ * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
+ * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
+ */
+#define VMXNET3_QUEUE_DESC_ALIGN 128
+
+
+struct Vmxnet3_MiscConf {
+ struct Vmxnet3_DriverInfo driverInfo;
+ __le64 uptFeatures;
+ __le64 ddPA; /* driver data PA */
+ __le64 queueDescPA; /* queue descriptor table PA */
+ __le32 ddLen; /* driver data len */
+ __le32 queueDescLen; /* queue desc. table len in bytes */
+ __le32 mtu;
+ __le16 maxNumRxSG;
+ u8 numTxQueues;
+ u8 numRxQueues;
+ __le32 reserved[4];
+};
+
+
+struct Vmxnet3_TxQueueConf {
+ __le64 txRingBasePA;
+ __le64 dataRingBasePA;
+ __le64 compRingBasePA;
+ __le64 ddPA; /* driver data */
+ __le64 reserved;
+ __le32 txRingSize; /* # of tx desc */
+ __le32 dataRingSize; /* # of data desc */
+ __le32 compRingSize; /* # of comp desc */
+ __le32 ddLen; /* size of driver data */
+ u8 intrIdx;
+ u8 _pad[7];
+};
+
+
+struct Vmxnet3_RxQueueConf {
+ __le64 rxRingBasePA[2];
+ __le64 compRingBasePA;
+ __le64 ddPA; /* driver data */
+ __le64 reserved;
+ __le32 rxRingSize[2]; /* # of rx desc */
+ __le32 compRingSize; /* # of rx comp desc */
+ __le32 ddLen; /* size of driver data */
+ u8 intrIdx;
+ u8 _pad[7];
+};
+
+
+enum vmxnet3_intr_mask_mode {
+ VMXNET3_IMM_AUTO = 0,
+ VMXNET3_IMM_ACTIVE = 1,
+ VMXNET3_IMM_LAZY = 2
+};
+
+enum vmxnet3_intr_type {
+ VMXNET3_IT_AUTO = 0,
+ VMXNET3_IT_INTX = 1,
+ VMXNET3_IT_MSI = 2,
+ VMXNET3_IT_MSIX = 3
+};
+
+#define VMXNET3_MAX_TX_QUEUES 8
+#define VMXNET3_MAX_RX_QUEUES 16
+/* addition 1 for events */
+#define VMXNET3_MAX_INTRS 25
+
+/* value of intrCtrl */
+#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
+
+
+struct Vmxnet3_IntrConf {
+ bool autoMask;
+ u8 numIntrs; /* # of interrupts */
+ u8 eventIntrIdx;
+ u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
+ * each intr */
+ __le32 intrCtrl;
+ __le32 reserved[2];
+};
+
+/* one bit per VLAN ID, the size is in the units of u32 */
+#define VMXNET3_VFT_SIZE (4096/(sizeof(uint32_t)*8))
+
+
+struct Vmxnet3_QueueStatus {
+ bool stopped;
+ u8 _pad[3];
+ __le32 error;
+};
+
+
+struct Vmxnet3_TxQueueCtrl {
+ __le32 txNumDeferred;
+ __le32 txThreshold;
+ __le64 reserved;
+};
+
+
+struct Vmxnet3_RxQueueCtrl {
+ bool updateRxProd;
+ u8 _pad[7];
+ __le64 reserved;
+};
+
+enum {
+ VMXNET3_RXM_UCAST = 0x01, /* unicast only */
+ VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
+ VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
+ VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
+ VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
+};
+
+struct Vmxnet3_RxFilterConf {
+ __le32 rxMode; /* VMXNET3_RXM_xxx */
+ __le16 mfTableLen; /* size of the multicast filter table */
+ __le16 _pad1;
+ __le64 mfTablePA; /* PA of the multicast filters table */
+ __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
+};
+
+
+#define VMXNET3_PM_MAX_FILTERS 6
+#define VMXNET3_PM_MAX_PATTERN_SIZE 128
+#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
+
+#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
+#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
+ * filters */
+
+
+struct Vmxnet3_PM_PktFilter {
+ u8 maskSize;
+ u8 patternSize;
+ u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
+ u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
+ u8 pad[6];
+};
+
+
+struct Vmxnet3_PMConf {
+ __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
+ u8 numFilters;
+ u8 pad[5];
+ struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
+};
+
+
+struct Vmxnet3_VariableLenConfDesc {
+ __le32 confVer;
+ __le32 confLen;
+ __le64 confPA;
+};
+
+
+struct Vmxnet3_TxQueueDesc {
+ struct Vmxnet3_TxQueueCtrl ctrl;
+ struct Vmxnet3_TxQueueConf conf;
+
+ /* Driver read after a GET command */
+ struct Vmxnet3_QueueStatus status;
+ struct UPT1_TxStats stats;
+ u8 _pad[88]; /* 128 aligned */
+};
+
+
+struct Vmxnet3_RxQueueDesc {
+ struct Vmxnet3_RxQueueCtrl ctrl;
+ struct Vmxnet3_RxQueueConf conf;
+ /* Driver read after a GET commad */
+ struct Vmxnet3_QueueStatus status;
+ struct UPT1_RxStats stats;
+ u8 __pad[88]; /* 128 aligned */
+};
+
+
+struct Vmxnet3_DSDevRead {
+ /* read-only region for device, read by dev in response to a SET cmd */
+ struct Vmxnet3_MiscConf misc;
+ struct Vmxnet3_IntrConf intrConf;
+ struct Vmxnet3_RxFilterConf rxFilterConf;
+ struct Vmxnet3_VariableLenConfDesc rssConfDesc;
+ struct Vmxnet3_VariableLenConfDesc pmConfDesc;
+ struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
+};
+
+/* All structures in DriverShared are padded to multiples of 8 bytes */
+struct Vmxnet3_DriverShared {
+ __le32 magic;
+ /* make devRead start at 64bit boundaries */
+ __le32 pad;
+ struct Vmxnet3_DSDevRead devRead;
+ __le32 ecr;
+ __le32 reserved[5];
+};
+
+
+#define VMXNET3_ECR_RQERR (1 << 0)
+#define VMXNET3_ECR_TQERR (1 << 1)
+#define VMXNET3_ECR_LINK (1 << 2)
+#define VMXNET3_ECR_DIC (1 << 3)
+#define VMXNET3_ECR_DEBUG (1 << 4)
+
+/* flip the gen bit of a ring */
+#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
+
+/* only use this if moving the idx won't affect the gen bit */
+#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
+ do {\
+ (idx)++;\
+ if (unlikely((idx) == (ring_size))) {\
+ (idx) = 0;\
+ } \
+ } while (0)
+
+#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
+ (vfTable[vid >> 5] |= (1 << (vid & 31)))
+#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
+ (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
+
+#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
+ ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
+
+#define VMXNET3_MAX_MTU 9000
+#define VMXNET3_MIN_MTU 60
+
+#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
+#define VMXNET3_LINK_DOWN 0
+
+#undef u64
+#undef u32
+#undef u16
+#undef u8
+#undef __le16
+#undef __le32
+#undef __le64
+#undef __packed
+#undef const_cpu_to_le64
+#if defined(HOST_WORDS_BIGENDIAN)
+#undef __BIG_ENDIAN_BITFIELD
+#endif
+
+#endif
diff --git a/hw/vmxnet_debug.h b/hw/vmxnet_debug.h
new file mode 100644
index 0000000..96dae0f
--- /dev/null
+++ b/hw/vmxnet_debug.h
@@ -0,0 +1,115 @@
+/*
+ * QEMU VMWARE VMXNET* paravirtual NICs - debugging facilities
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef _QEMU_VMXNET_DEBUG_H
+#define _QEMU_VMXNET_DEBUG_H
+
+#define VMXNET_DEVICE_NAME "vmxnet3"
+
+/* #define VMXNET_DEBUG_CB */
+#define VMXNET_DEBUG_WARNINGS
+#define VMXNET_DEBUG_ERRORS
+/* #define VMXNET_DEBUG_INTERRUPTS */
+/* #define VMXNET_DEBUG_CONFIG */
+/* #define VMXNET_DEBUG_RINGS */
+/* #define VMXNET_DEBUG_PACKETS */
+/* #define VMXNET_DEBUG_SHMEM_ACCESS */
+
+#ifdef VMXNET_DEBUG_SHMEM_ACCESS
+#define VMW_SHPRN(fmt, ...) \
+ do { \
+ printf("[%s][SH][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_SHPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_CB
+#define VMW_CBPRN(fmt, ...) \
+ do { \
+ printf("[%s][CB][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_CBPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_PACKETS
+#define VMW_PKPRN(fmt, ...) \
+ do { \
+ printf("[%s][PK][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_PKPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_WARNINGS
+#define VMW_WRPRN(fmt, ...) \
+ do { \
+ printf("[%s][WR][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_WRPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_ERRORS
+#define VMW_ERPRN(fmt, ...) \
+ do { \
+ printf("[%s][ER][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_ERPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_INTERRUPTS
+#define VMW_IRPRN(fmt, ...) \
+ do { \
+ printf("[%s][IR][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_IRPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_CONFIG
+#define VMW_CFPRN(fmt, ...) \
+ do { \
+ printf("[%s][CF][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_CFPRN(fmt, ...) do {} while (0)
+#endif
+
+#ifdef VMXNET_DEBUG_RINGS
+#define VMW_RIPRN(fmt, ...) \
+ do { \
+ printf("[%s][RI][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define VMW_RIPRN(fmt, ...) do {} while (0)
+#endif
+
+#define VMXNET_MF "%02X:%02X:%02X:%02X:%02X:%02X"
+#define VMXNET_MA(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+
+#endif /* _QEMU_VMXNET3_DEBUG_H */
diff --git a/hw/vmxnet_rx_pkt.c b/hw/vmxnet_rx_pkt.c
new file mode 100644
index 0000000..a40e346
--- /dev/null
+++ b/hw/vmxnet_rx_pkt.c
@@ -0,0 +1,187 @@
+/*
+ * QEMU VMWARE VMXNET* paravirtual NICs - RX packets abstractions
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "vmxnet_rx_pkt.h"
+#include "net/eth.h"
+#include "qemu-common.h"
+#include "qemu/iov.h"
+#include "net/checksum.h"
+#include "net/tap.h"
+
+/*
+ * RX packet may contain up to 2 fragments - rebuilt eth header
+ * in case of VLAN tag stripping
+ * and payload received from QEMU - in any case
+ */
+#define VMXNET_MAX_RX_PACKET_FRAGMENTS (2)
+
+struct VmxnetRxPkt {
+ struct virtio_net_hdr virt_hdr;
+ uint8_t ehdr_buf[ETH_MAX_L2_HDR_LEN];
+ struct iovec vec[VMXNET_MAX_RX_PACKET_FRAGMENTS];
+ uint16_t vec_len;
+ uint32_t tot_len;
+ uint16_t tci;
+ bool vlan_stripped;
+ bool has_virt_hdr;
+ eth_pkt_types_e packet_type;
+
+ /* Analysis results */
+ bool isip4;
+ bool isip6;
+ bool isudp;
+ bool istcp;
+};
+
+void vmxnet_rx_pkt_init(struct VmxnetRxPkt **pkt, bool has_virt_hdr)
+{
+ struct VmxnetRxPkt *p = g_malloc0(sizeof *p);
+ p->has_virt_hdr = has_virt_hdr;
+ *pkt = p;
+}
+
+void vmxnet_rx_pkt_uninit(struct VmxnetRxPkt *pkt)
+{
+ g_free(pkt);
+}
+
+struct virtio_net_hdr *vmxnet_rx_pkt_get_vhdr(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+ return &pkt->virt_hdr;
+}
+
+void vmxnet_rx_pkt_attach_data(struct VmxnetRxPkt *pkt, const void *data,
+ size_t len, bool strip_vlan)
+{
+ uint16_t tci = 0;
+ uint16_t ploff;
+ assert(pkt);
+ pkt->vlan_stripped = false;
+
+ if (strip_vlan) {
+ pkt->vlan_stripped = eth_strip_vlan(data, pkt->ehdr_buf, &ploff, &tci);
+ }
+
+ if (pkt->vlan_stripped) {
+ pkt->vec[0].iov_base = pkt->ehdr_buf;
+ pkt->vec[0].iov_len = ploff - sizeof(struct vlan_header);
+ pkt->vec[1].iov_base = (uint8_t *) data + ploff;
+ pkt->vec[1].iov_len = len - ploff;
+ pkt->vec_len = 2;
+ pkt->tot_len = len - ploff + sizeof(struct eth_header);
+ } else {
+ pkt->vec[0].iov_base = (void *)data;
+ pkt->vec[0].iov_len = len;
+ pkt->vec_len = 1;
+ pkt->tot_len = len;
+ }
+
+ pkt->tci = tci;
+
+ eth_get_protocols(data, len, &pkt->isip4, &pkt->isip6,
+ &pkt->isudp, &pkt->istcp);
+}
+
+void vmxnet_rx_pkt_dump(struct VmxnetRxPkt *pkt)
+{
+#ifdef VMXNET_RX_PKT_DEBUG
+ VmxnetRxPkt *pkt = (VmxnetRxPkt *)pkt;
+ assert(pkt);
+
+ printf("RX PKT: tot_len: %d, vlan_stripped: %d, vlan_tag: %d\n",
+ pkt->tot_len, pkt->vlan_stripped, pkt->tci);
+#endif
+}
+
+void vmxnet_rx_pkt_set_packet_type(struct VmxnetRxPkt *pkt,
+ eth_pkt_types_e packet_type)
+{
+ assert(pkt);
+
+ pkt->packet_type = packet_type;
+
+}
+
+eth_pkt_types_e vmxnet_rx_pkt_get_packet_type(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->packet_type;
+}
+
+size_t vmxnet_rx_pkt_get_total_len(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->tot_len;
+}
+
+void vmxnet_rx_pkt_get_protocols(struct VmxnetRxPkt *pkt,
+ bool *isip4, bool *isip6,
+ bool *isudp, bool *istcp)
+{
+ assert(pkt);
+
+ *isip4 = pkt->isip4;
+ *isip6 = pkt->isip6;
+ *isudp = pkt->isudp;
+ *istcp = pkt->istcp;
+}
+
+struct iovec *vmxnet_rx_pkt_get_iovec(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->vec;
+}
+
+void vmxnet_rx_pkt_set_vhdr(struct VmxnetRxPkt *pkt,
+ struct virtio_net_hdr *vhdr)
+{
+ assert(pkt);
+
+ memcpy(&pkt->virt_hdr, vhdr, sizeof pkt->virt_hdr);
+}
+
+bool vmxnet_rx_pkt_is_vlan_stripped(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->vlan_stripped;
+}
+
+bool vmxnet_rx_pkt_has_virt_hdr(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->has_virt_hdr;
+}
+
+uint16_t vmxnet_rx_pkt_get_num_frags(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->vec_len;
+}
+
+uint16_t vmxnet_rx_pkt_get_vlan_tag(struct VmxnetRxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->tci;
+}
diff --git a/hw/vmxnet_rx_pkt.h b/hw/vmxnet_rx_pkt.h
new file mode 100644
index 0000000..6b2c60e
--- /dev/null
+++ b/hw/vmxnet_rx_pkt.h
@@ -0,0 +1,174 @@
+/*
+ * QEMU VMWARE VMXNET* paravirtual NICs - RX packets abstraction
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef VMXNET_RX_PKT_H
+#define VMXNET_RX_PKT_H
+
+#include "stdint.h"
+#include "stdbool.h"
+#include "net/eth.h"
+
+/* defines to enable packet dump functions */
+/*#define VMXNET_RX_PKT_DEBUG*/
+
+struct VmxnetRxPkt;
+
+/**
+ * Clean all rx packet resources
+ *
+ * @pkt: packet
+ *
+ */
+void vmxnet_rx_pkt_uninit(struct VmxnetRxPkt *pkt);
+
+/**
+ * Init function for rx packet functionality
+ *
+ * @pkt: packet pointer
+ * @has_virt_hdr: device uses virtio header
+ *
+ */
+void vmxnet_rx_pkt_init(struct VmxnetRxPkt **pkt, bool has_virt_hdr);
+
+/**
+ * returns total length of data attached to rx context
+ *
+ * @pkt: packet
+ *
+ * Return: nothing
+ *
+ */
+size_t vmxnet_rx_pkt_get_total_len(struct VmxnetRxPkt *pkt);
+
+/**
+ * fetches packet analysis results
+ *
+ * @pkt: packet
+ * @isip4: whether the packet given is IPv4
+ * @isip6: whether the packet given is IPv6
+ * @isudp: whether the packet given is UDP
+ * @istcp: whether the packet given is TCP
+ *
+ */
+void vmxnet_rx_pkt_get_protocols(struct VmxnetRxPkt *pkt,
+ bool *isip4, bool *isip6,
+ bool *isudp, bool *istcp);
+
+/**
+ * returns virtio header stored in rx context
+ *
+ * @pkt: packet
+ * @ret: virtio header
+ *
+ */
+struct virtio_net_hdr *vmxnet_rx_pkt_get_vhdr(struct VmxnetRxPkt *pkt);
+
+/**
+ * returns packet type
+ *
+ * @pkt: packet
+ * @ret: packet type
+ *
+ */
+eth_pkt_types_e vmxnet_rx_pkt_get_packet_type(struct VmxnetRxPkt *pkt);
+
+/**
+ * returns vlan tag
+ *
+ * @pkt: packet
+ * @ret: VLAN tag
+ *
+ */
+uint16_t vmxnet_rx_pkt_get_vlan_tag(struct VmxnetRxPkt *pkt);
+
+/**
+ * tells whether vlan was stripped from the packet
+ *
+ * @pkt: packet
+ * @ret: VLAN stripped sign
+ *
+ */
+bool vmxnet_rx_pkt_is_vlan_stripped(struct VmxnetRxPkt *pkt);
+
+/**
+ * notifies caller if the packet has virtio header
+ *
+ * @pkt: packet
+ * @ret: true if packet has virtio header, false otherwize
+ *
+ */
+bool vmxnet_rx_pkt_has_virt_hdr(struct VmxnetRxPkt *pkt);
+
+/**
+ * returns number of frags attached to the packet
+ *
+ * @pkt: packet
+ * @ret: number of frags
+ *
+ */
+uint16_t vmxnet_rx_pkt_get_num_frags(struct VmxnetRxPkt *pkt);
+
+/**
+ * attach data to rx packet
+ *
+ * @pkt: packet
+ * @data: pointer to the data buffer
+ * @len: data length
+ * @strip_vlan: should the module strip vlan from data
+ *
+ */
+void vmxnet_rx_pkt_attach_data(struct VmxnetRxPkt *pkt, const void *data,
+ size_t len, bool strip_vlan);
+
+/**
+ * returns io vector that holds the attached data
+ *
+ * @pkt: packet
+ * @ret: pointer to IOVec
+ *
+ */
+struct iovec *vmxnet_rx_pkt_get_iovec(struct VmxnetRxPkt *pkt);
+
+/**
+ * prints rx packet data if debug is enabled
+ *
+ * @pkt: packet
+ *
+ */
+void vmxnet_rx_pkt_dump(struct VmxnetRxPkt *pkt);
+
+/**
+ * copy passed vhdr data to packet context
+ *
+ * @pkt: packet
+ * @vhdr: VHDR buffer
+ *
+ */
+void vmxnet_rx_pkt_set_vhdr(struct VmxnetRxPkt *pkt,
+ struct virtio_net_hdr *vhdr);
+
+/**
+ * save packet type in packet context
+ *
+ * @pkt: packet
+ * @packet_type: the packet type
+ *
+ */
+void vmxnet_rx_pkt_set_packet_type(struct VmxnetRxPkt *pkt,
+ eth_pkt_types_e packet_type);
+
+#endif
diff --git a/hw/vmxnet_tx_pkt.c b/hw/vmxnet_tx_pkt.c
new file mode 100644
index 0000000..b1e795b
--- /dev/null
+++ b/hw/vmxnet_tx_pkt.c
@@ -0,0 +1,567 @@
+/*
+ * QEMU VMWARE VMXNET* paravirtual NICs - TX packets abstractions
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "vmxnet_tx_pkt.h"
+#include "net/eth.h"
+#include "qemu-common.h"
+#include "qemu/iov.h"
+#include "net/checksum.h"
+#include "net/tap.h"
+#include "net/net.h"
+#include "exec/cpu-common.h"
+
+enum {
+ VMXNET_TX_PKT_VHDR_FRAG = 0,
+ VMXNET_TX_PKT_L2HDR_FRAG,
+ VMXNET_TX_PKT_L3HDR_FRAG,
+ VMXNET_TX_PKT_PL_START_FRAG
+};
+
+/* TX packet private context */
+struct VmxnetTxPkt {
+ struct virtio_net_hdr virt_hdr;
+ bool has_virt_hdr;
+
+ struct iovec *raw;
+ uint32_t raw_frags;
+ uint32_t max_raw_frags;
+
+ struct iovec *vec;
+
+ uint8_t l2_hdr[ETH_MAX_L2_HDR_LEN];
+
+ uint32_t payload_len;
+
+ uint32_t payload_frags;
+ uint32_t max_payload_frags;
+
+ uint16_t hdr_len;
+ eth_pkt_types_e packet_type;
+ uint8_t l4proto;
+};
+
+void vmxnet_tx_pkt_init(struct VmxnetTxPkt **pkt, uint32_t max_frags,
+ bool has_virt_hdr)
+{
+ struct VmxnetTxPkt *p = g_malloc0(sizeof *p);
+
+ p->vec = g_malloc((sizeof *p->vec) *
+ (max_frags + VMXNET_TX_PKT_PL_START_FRAG));
+
+ p->raw = g_malloc((sizeof *p->raw) * max_frags);
+
+ p->max_payload_frags = max_frags;
+ p->max_raw_frags = max_frags;
+ p->has_virt_hdr = has_virt_hdr;
+ p->vec[VMXNET_TX_PKT_VHDR_FRAG].iov_base = &p->virt_hdr;
+ p->vec[VMXNET_TX_PKT_VHDR_FRAG].iov_len =
+ p->has_virt_hdr ? sizeof p->virt_hdr : 0;
+ p->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_base = &p->l2_hdr;
+ p->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base = NULL;
+ p->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len = 0;
+
+ *pkt = p;
+}
+
+void vmxnet_tx_pkt_uninit(struct VmxnetTxPkt *pkt)
+{
+ if (pkt) {
+ g_free(pkt->vec);
+ g_free(pkt->raw);
+ g_free(pkt);
+ }
+}
+
+void vmxnet_tx_pkt_update_ip_checksums(struct VmxnetTxPkt *pkt)
+{
+ uint16_t csum;
+ uint32_t ph_raw_csum;
+ assert(pkt);
+ uint8_t gso_type = pkt->virt_hdr.gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
+ struct ip_header *ip_hdr;
+
+ if (VIRTIO_NET_HDR_GSO_TCPV4 != gso_type &&
+ VIRTIO_NET_HDR_GSO_UDP != gso_type) {
+ return;
+ }
+
+ ip_hdr = pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base;
+
+ if (pkt->payload_len + pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len >
+ ETH_MAX_IP_DGRAM_LEN) {
+ return;
+ }
+
+ ip_hdr->ip_len = cpu_to_be16(pkt->payload_len +
+ pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len);
+
+ /* Calculate IP header checksum */
+ ip_hdr->ip_sum = 0;
+ csum = net_raw_checksum((uint8_t *)ip_hdr,
+ pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len);
+ ip_hdr->ip_sum = cpu_to_be16(csum);
+
+ /* Calculate IP pseudo header checksum */
+ ph_raw_csum = eth_calc_pseudo_hdr_csum(ip_hdr, pkt->payload_len);
+ csum = cpu_to_be16(~net_checksum_finish(ph_raw_csum));
+ iov_from_buf(&pkt->vec[VMXNET_TX_PKT_PL_START_FRAG], pkt->payload_frags,
+ pkt->virt_hdr.csum_offset, &csum, sizeof(csum));
+}
+
+static void vmxnet_tx_pkt_calculate_hdr_len(struct VmxnetTxPkt *pkt)
+{
+ pkt->hdr_len = pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_len +
+ pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len;
+}
+
+static bool vmxnet_tx_pkt_parse_headers(struct VmxnetTxPkt *pkt)
+{
+ struct iovec *l2_hdr, *l3_hdr;
+ size_t bytes_read;
+ size_t full_ip6hdr_len;
+ uint16_t l3_proto;
+
+ assert(pkt);
+
+ l2_hdr = &pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG];
+ l3_hdr = &pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG];
+
+ bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, 0, l2_hdr->iov_base,
+ ETH_MAX_L2_HDR_LEN);
+ if (bytes_read < ETH_MAX_L2_HDR_LEN) {
+ l2_hdr->iov_len = 0;
+ return false;
+ } else {
+ l2_hdr->iov_len = eth_get_l2_hdr_length(l2_hdr->iov_base);
+ }
+
+ l3_proto = eth_get_l3_proto(l2_hdr->iov_base, l2_hdr->iov_len);
+
+ switch (l3_proto) {
+ case ETH_P_IP:
+ l3_hdr->iov_base = g_malloc(ETH_MAX_IP4_HDR_LEN);
+
+ bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len,
+ l3_hdr->iov_base, sizeof(struct ip_header));
+
+ if (bytes_read < sizeof(struct ip_header)) {
+ l3_hdr->iov_len = 0;
+ return false;
+ }
+
+ l3_hdr->iov_len = IP_HDR_GET_LEN(l3_hdr->iov_base);
+ pkt->l4proto = ((struct ip_header *) l3_hdr->iov_base)->ip_p;
+
+ /* copy optional IPv4 header data */
+ bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags,
+ l2_hdr->iov_len + sizeof(struct ip_header),
+ l3_hdr->iov_base + sizeof(struct ip_header),
+ l3_hdr->iov_len - sizeof(struct ip_header));
+ if (bytes_read < l3_hdr->iov_len - sizeof(struct ip_header)) {
+ l3_hdr->iov_len = 0;
+ return false;
+ }
+ break;
+
+ case ETH_P_IPV6:
+ if (!eth_parse_ipv6_hdr(pkt->raw, pkt->raw_frags, l2_hdr->iov_len,
+ &pkt->l4proto, &full_ip6hdr_len)) {
+ l3_hdr->iov_len = 0;
+ return false;
+ }
+
+ l3_hdr->iov_base = g_malloc(full_ip6hdr_len);
+
+ bytes_read = iov_to_buf(pkt->raw, pkt->raw_frags, l2_hdr->iov_len,
+ l3_hdr->iov_base, full_ip6hdr_len);
+
+ if (bytes_read < full_ip6hdr_len) {
+ l3_hdr->iov_len = 0;
+ return false;
+ } else {
+ l3_hdr->iov_len = full_ip6hdr_len;
+ }
+ break;
+
+ default:
+ l3_hdr->iov_len = 0;
+ break;
+ }
+
+ vmxnet_tx_pkt_calculate_hdr_len(pkt);
+ pkt->packet_type = get_eth_packet_type(l2_hdr->iov_base);
+ return true;
+}
+
+static bool vmxnet_tx_pkt_rebuild_payload(struct VmxnetTxPkt *pkt)
+{
+ size_t payload_len = iov_size(pkt->raw, pkt->raw_frags) - pkt->hdr_len;
+
+ pkt->payload_frags = iov_copy(&pkt->vec[VMXNET_TX_PKT_PL_START_FRAG],
+ pkt->max_payload_frags,
+ pkt->raw, pkt->raw_frags,
+ pkt->hdr_len, payload_len);
+
+ if (pkt->payload_frags != (uint32_t) -1) {
+ pkt->payload_len = payload_len;
+ return true;
+ } else {
+ return false;
+ }
+}
+
+bool vmxnet_tx_pkt_parse(struct VmxnetTxPkt *pkt)
+{
+ return vmxnet_tx_pkt_parse_headers(pkt) &&
+ vmxnet_tx_pkt_rebuild_payload(pkt);
+}
+
+struct virtio_net_hdr *vmxnet_tx_pkt_get_vhdr(struct VmxnetTxPkt *pkt)
+{
+ assert(pkt);
+ return &pkt->virt_hdr;
+}
+
+static uint8_t vmxnet_tx_pkt_get_gso_type(struct VmxnetTxPkt *pkt,
+ bool tso_enable)
+{
+ uint8_t rc = VIRTIO_NET_HDR_GSO_NONE;
+ uint16_t l3_proto;
+
+ l3_proto = eth_get_l3_proto(pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_base,
+ pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_len);
+
+ if (!tso_enable) {
+ goto func_exit;
+ }
+
+ rc = eth_get_gso_type(l3_proto, pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base,
+ pkt->l4proto);
+
+func_exit:
+ return rc;
+}
+
+void vmxnet_tx_pkt_build_vheader(struct VmxnetTxPkt *pkt, bool tso_enable,
+ bool csum_enable, uint32_t gso_size)
+{
+ struct tcp_hdr l4hdr;
+ assert(pkt);
+
+ /* csum has to be enabled if tso is. */
+ assert(csum_enable || !tso_enable);
+
+ pkt->virt_hdr.gso_type = vmxnet_tx_pkt_get_gso_type(pkt, tso_enable);
+
+ switch (pkt->virt_hdr.gso_type & ~VIRTIO_NET_HDR_GSO_ECN) {
+ case VIRTIO_NET_HDR_GSO_NONE:
+ pkt->virt_hdr.hdr_len = 0;
+ pkt->virt_hdr.gso_size = 0;
+ break;
+
+ case VIRTIO_NET_HDR_GSO_UDP:
+ pkt->virt_hdr.gso_size = IP_FRAG_ALIGN_SIZE(gso_size);
+ pkt->virt_hdr.hdr_len = pkt->hdr_len + sizeof(struct udp_header);
+ break;
+
+ case VIRTIO_NET_HDR_GSO_TCPV4:
+ case VIRTIO_NET_HDR_GSO_TCPV6:
+ iov_to_buf(&pkt->vec[VMXNET_TX_PKT_PL_START_FRAG], pkt->payload_frags,
+ 0, &l4hdr, sizeof(l4hdr));
+ pkt->virt_hdr.hdr_len = pkt->hdr_len + l4hdr.th_off * sizeof(uint32_t);
+ pkt->virt_hdr.gso_size = IP_FRAG_ALIGN_SIZE(gso_size);
+ break;
+
+ default:
+ assert(false);
+ }
+
+ if (csum_enable) {
+ switch (pkt->l4proto) {
+ case IP_PROTO_TCP:
+ pkt->virt_hdr.flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
+ pkt->virt_hdr.csum_start = pkt->hdr_len;
+ pkt->virt_hdr.csum_offset = offsetof(struct tcp_hdr, th_sum);
+ break;
+ case IP_PROTO_UDP:
+ pkt->virt_hdr.flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
+ pkt->virt_hdr.csum_start = pkt->hdr_len;
+ pkt->virt_hdr.csum_offset = offsetof(struct udp_hdr, uh_sum);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void vmxnet_tx_pkt_setup_vlan_header(struct VmxnetTxPkt *pkt, uint16_t vlan)
+{
+ bool is_new;
+ assert(pkt);
+
+ eth_setup_vlan_headers(pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_base,
+ vlan, &is_new);
+
+ /* update l2hdrlen */
+ if (is_new) {
+ pkt->hdr_len += sizeof(struct vlan_header);
+ pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_len +=
+ sizeof(struct vlan_header);
+ }
+}
+
+bool vmxnet_tx_pkt_add_raw_fragment(struct VmxnetTxPkt *pkt, hwaddr pa,
+ size_t len)
+{
+ hwaddr mapped_len = 0;
+ struct iovec *ventry;
+ assert(pkt);
+ assert(pkt->max_raw_frags > pkt->raw_frags);
+
+ if (!len) {
+ return true;
+ }
+
+ ventry = &pkt->raw[pkt->raw_frags];
+ mapped_len = len;
+
+ ventry->iov_base = cpu_physical_memory_map(pa, &mapped_len, false);
+ ventry->iov_len = mapped_len;
+ pkt->raw_frags += !!ventry->iov_base;
+
+ if ((ventry->iov_base == NULL) || (len != mapped_len)) {
+ return false;
+ }
+
+ return true;
+}
+
+eth_pkt_types_e vmxnet_tx_pkt_get_packet_type(struct VmxnetTxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->packet_type;
+}
+
+size_t vmxnet_tx_pkt_get_total_len(struct VmxnetTxPkt *pkt)
+{
+ assert(pkt);
+
+ return pkt->hdr_len + pkt->payload_len;
+}
+
+void vmxnet_tx_pkt_dump(struct VmxnetTxPkt *pkt)
+{
+#ifdef VMXNET_TX_PKT_DEBUG
+ assert(pkt);
+
+ printf("TX PKT: hdr_len: %d, pkt_type: 0x%X, l2hdr_len: %lu, "
+ "l3hdr_len: %lu, payload_len: %u\n", pkt->hdr_len, pkt->packet_type,
+ pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_len,
+ pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len, pkt->payload_len);
+#endif
+}
+
+void vmxnet_tx_pkt_reset(struct VmxnetTxPkt *pkt)
+{
+ int i;
+
+ /* no assert, as reset can be called before tx_pkt_init */
+ if (!pkt) {
+ return;
+ }
+
+ memset(&pkt->virt_hdr, 0, sizeof(pkt->virt_hdr));
+
+ g_free(pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base);
+ pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base = NULL;
+
+ assert(pkt->vec);
+ for (i = VMXNET_TX_PKT_L2HDR_FRAG;
+ i < pkt->payload_frags + VMXNET_TX_PKT_PL_START_FRAG; i++) {
+ pkt->vec[i].iov_len = 0;
+ }
+ pkt->payload_len = 0;
+ pkt->payload_frags = 0;
+
+ assert(pkt->raw);
+ for (i = 0; i < pkt->raw_frags; i++) {
+ assert(pkt->raw[i].iov_base);
+ cpu_physical_memory_unmap(pkt->raw[i].iov_base, pkt->raw[i].iov_len,
+ false, pkt->raw[i].iov_len);
+ pkt->raw[i].iov_len = 0;
+ }
+ pkt->raw_frags = 0;
+
+ pkt->hdr_len = 0;
+ pkt->packet_type = 0;
+ pkt->l4proto = 0;
+}
+
+static void vmxnet_tx_pkt_do_sw_csum(struct VmxnetTxPkt *pkt)
+{
+ struct iovec *iov = &pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG];
+ uint32_t csum_cntr;
+ uint16_t csum = 0;
+ /* num of iovec without vhdr */
+ uint32_t iov_len = pkt->payload_frags + VMXNET_TX_PKT_PL_START_FRAG - 1;
+ uint16_t csl;
+ struct ip_header *iphdr;
+ size_t csum_offset = pkt->virt_hdr.csum_start + pkt->virt_hdr.csum_offset;
+
+ /* Put zero to checksum field */
+ iov_from_buf(iov, iov_len, csum_offset, &csum, sizeof csum);
+
+ /* Calculate L4 TCP/UDP checksum */
+ csl = pkt->payload_len;
+
+ /* data checksum */
+ csum_cntr =
+ net_checksum_add_iov(iov, iov_len, pkt->virt_hdr.csum_start, csl);
+ /* add pseudo header to csum */
+ iphdr = pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base;
+ csum_cntr += eth_calc_pseudo_hdr_csum(iphdr, csl);
+
+ /* Put the checksum obtained into the packet */
+ csum = cpu_to_be16(net_checksum_finish(csum_cntr));
+ iov_from_buf(iov, iov_len, csum_offset, &csum, sizeof csum);
+}
+
+enum {
+ VMXNET_TX_PKT_FRAGMENT_L2_HDR_POS = 0,
+ VMXNET_TX_PKT_FRAGMENT_L3_HDR_POS,
+ VMXNET_TX_PKT_FRAGMENT_HEADER_NUM
+};
+
+#define VMXNET_MAX_FRAG_SG_LIST (64)
+
+static size_t vmxnet_tx_pkt_fetch_fragment(struct VmxnetTxPkt *pkt,
+ int *src_idx, size_t *src_offset, struct iovec *dst, int *dst_idx)
+{
+ size_t fetched = 0;
+ struct iovec *src = pkt->vec;
+
+ *dst_idx = VMXNET_TX_PKT_FRAGMENT_HEADER_NUM;
+
+ while (fetched < pkt->virt_hdr.gso_size) {
+
+ /* no more place in fragment iov */
+ if (*dst_idx == VMXNET_MAX_FRAG_SG_LIST) {
+ break;
+ }
+
+ /* no more data in iovec */
+ if (*src_idx == (pkt->payload_frags + VMXNET_TX_PKT_PL_START_FRAG)) {
+ break;
+ }
+
+
+ dst[*dst_idx].iov_base = src[*src_idx].iov_base + *src_offset;
+ dst[*dst_idx].iov_len = MIN(src[*src_idx].iov_len - *src_offset,
+ pkt->virt_hdr.gso_size - fetched);
+
+ *src_offset += dst[*dst_idx].iov_len;
+ fetched += dst[*dst_idx].iov_len;
+
+ if (*src_offset == src[*src_idx].iov_len) {
+ *src_offset = 0;
+ (*src_idx)++;
+ }
+
+ (*dst_idx)++;
+ }
+
+ return fetched;
+}
+
+static bool vmxnet_tx_pkt_do_sw_fragmentation(struct VmxnetTxPkt *pkt,
+ NetClientState *nc)
+{
+ struct iovec fragment[VMXNET_MAX_FRAG_SG_LIST];
+ size_t fragment_len = 0;
+ bool more_frags = false;
+
+ /* some pointers for shorter code */
+ void *l2_iov_base, *l3_iov_base;
+ size_t l2_iov_len, l3_iov_len;
+ int src_idx = VMXNET_TX_PKT_PL_START_FRAG, dst_idx;
+ size_t src_offset = 0;
+ size_t fragment_offset = 0;
+
+ l2_iov_base = pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_base;
+ l2_iov_len = pkt->vec[VMXNET_TX_PKT_L2HDR_FRAG].iov_len;
+ l3_iov_base = pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_base;
+ l3_iov_len = pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len;
+
+ /* Copy headers */
+ fragment[VMXNET_TX_PKT_FRAGMENT_L2_HDR_POS].iov_base = l2_iov_base;
+ fragment[VMXNET_TX_PKT_FRAGMENT_L2_HDR_POS].iov_len = l2_iov_len;
+ fragment[VMXNET_TX_PKT_FRAGMENT_L3_HDR_POS].iov_base = l3_iov_base;
+ fragment[VMXNET_TX_PKT_FRAGMENT_L3_HDR_POS].iov_len = l3_iov_len;
+
+
+ /* Put as much data as possible and send */
+ do {
+ fragment_len = vmxnet_tx_pkt_fetch_fragment(pkt, &src_idx, &src_offset,
+ fragment, &dst_idx);
+
+ more_frags = (fragment_offset + fragment_len < pkt->payload_len);
+
+ eth_setup_ip4_fragmentation(l2_iov_base, l2_iov_len, l3_iov_base,
+ l3_iov_len, fragment_len, fragment_offset, more_frags);
+
+ eth_fix_ip4_checksum(l3_iov_base, l3_iov_len);
+
+ qemu_sendv_packet(nc, fragment, dst_idx);
+
+ fragment_offset += fragment_len;
+
+ } while (more_frags);
+
+ return true;
+}
+
+bool vmxnet_tx_pkt_send(struct VmxnetTxPkt *pkt, NetClientState *nc)
+{
+ assert(pkt);
+
+ if (!pkt->has_virt_hdr &&
+ pkt->virt_hdr.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
+ vmxnet_tx_pkt_do_sw_csum(pkt);
+ }
+
+ /*
+ * Since underlying infrastructure does not support IP datagrams longer
+ * than 64K we should drop such packets and don't even try to send
+ */
+ if (VIRTIO_NET_HDR_GSO_NONE != pkt->virt_hdr.gso_type) {
+ if (pkt->payload_len >
+ ETH_MAX_IP_DGRAM_LEN -
+ pkt->vec[VMXNET_TX_PKT_L3HDR_FRAG].iov_len) {
+ return false;
+ }
+ }
+
+ if (pkt->has_virt_hdr ||
+ pkt->virt_hdr.gso_type == VIRTIO_NET_HDR_GSO_NONE) {
+ qemu_sendv_packet(nc, pkt->vec,
+ pkt->payload_frags + VMXNET_TX_PKT_PL_START_FRAG);
+ return true;
+ }
+
+ return vmxnet_tx_pkt_do_sw_fragmentation(pkt, nc);
+}
diff --git a/hw/vmxnet_tx_pkt.h b/hw/vmxnet_tx_pkt.h
new file mode 100644
index 0000000..57121a6
--- /dev/null
+++ b/hw/vmxnet_tx_pkt.h
@@ -0,0 +1,148 @@
+/*
+ * QEMU VMWARE VMXNET* paravirtual NICs - TX packets abstraction
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef VMXNET_TX_PKT_H
+#define VMXNET_TX_PKT_H
+
+#include "stdint.h"
+#include "stdbool.h"
+#include "net/eth.h"
+#include "exec/hwaddr.h"
+
+/* define to enable packet dump functions */
+/*#define VMXNET_TX_PKT_DEBUG*/
+
+struct VmxnetTxPkt;
+
+/**
+ * Init function for tx packet functionality
+ *
+ * @pkt: packet pointer
+ * @max_frags: max tx ip fragments
+ * @has_virt_hdr: device uses virtio header.
+ */
+void vmxnet_tx_pkt_init(struct VmxnetTxPkt **pkt, uint32_t max_frags,
+ bool has_virt_hdr);
+
+/**
+ * Clean all tx packet resources.
+ *
+ * @pkt: packet.
+ */
+void vmxnet_tx_pkt_uninit(struct VmxnetTxPkt *pkt);
+
+/**
+ * get virtio header
+ *
+ * @pkt: packet
+ * @ret: virtio header
+ */
+struct virtio_net_hdr *vmxnet_tx_pkt_get_vhdr(struct VmxnetTxPkt *pkt);
+
+/**
+ * build virtio header (will be stored in module context)
+ *
+ * @pkt: packet
+ * @tso_enable: TSO enabled
+ * @csum_enable: CSO enabled
+ * @gso_size: MSS size for TSO
+ *
+ */
+void vmxnet_tx_pkt_build_vheader(struct VmxnetTxPkt *pkt, bool tso_enable,
+ bool csum_enable, uint32_t gso_size);
+
+/**
+ * updates vlan tag, and adds vlan header in case it is missing
+ *
+ * @pkt: packet
+ * @vlan: VLAN tag
+ *
+ */
+void vmxnet_tx_pkt_setup_vlan_header(struct VmxnetTxPkt *pkt, uint16_t vlan);
+
+/**
+ * populate data fragment into pkt context.
+ *
+ * @pkt: packet
+ * @pa: physical address of fragment
+ * @len: length of fragment
+ *
+ */
+bool vmxnet_tx_pkt_add_raw_fragment(struct VmxnetTxPkt *pkt, hwaddr pa,
+ size_t len);
+
+/**
+ * fix ip header fields and calculate checksums needed.
+ *
+ * @pkt: packet
+ *
+ */
+void vmxnet_tx_pkt_update_ip_checksums(struct VmxnetTxPkt *pkt);
+
+/**
+ * get length of all populated data.
+ *
+ * @pkt: packet
+ * @ret: total data length
+ *
+ */
+size_t vmxnet_tx_pkt_get_total_len(struct VmxnetTxPkt *pkt);
+
+/**
+ * get packet type
+ *
+ * @pkt: packet
+ * @ret: packet type
+ *
+ */
+eth_pkt_types_e vmxnet_tx_pkt_get_packet_type(struct VmxnetTxPkt *pkt);
+
+/**
+ * prints packet data if debug is enabled
+ *
+ * @pkt: packet
+ *
+ */
+void vmxnet_tx_pkt_dump(struct VmxnetTxPkt *pkt);
+
+/**
+ * reset tx packet private context (needed to be called between packets)
+ *
+ * @pkt: packet
+ *
+ */
+void vmxnet_tx_pkt_reset(struct VmxnetTxPkt *pkt);
+
+/**
+ * Send packet to qemu. handles sw offloads if vhdr is not supported.
+ *
+ * @pkt: packet
+ * @nc: NetClientState
+ * @ret: operation result
+ *
+ */
+bool vmxnet_tx_pkt_send(struct VmxnetTxPkt *pkt, NetClientState *nc);
+
+/**
+ * parse raw packet data and analyze offload requirements.
+ *
+ * @pkt: packet
+ *
+ */
+bool vmxnet_tx_pkt_parse(struct VmxnetTxPkt *pkt);
+
+#endif
diff --git a/hw/xenfb.c b/hw/xenfb.c
index 3462ded..7c46a2f 100644
--- a/hw/xenfb.c
+++ b/hw/xenfb.c
@@ -54,7 +54,7 @@
struct common {
struct XenDevice xendev; /* must be first */
void *page;
- DisplayState *ds;
+ QemuConsole *con;
};
struct XenInput {
@@ -318,8 +318,9 @@
int dx, int dy, int dz, int button_state)
{
struct XenInput *xenfb = opaque;
- int dw = ds_get_width(xenfb->c.ds);
- int dh = ds_get_height(xenfb->c.ds);
+ DisplaySurface *surface = qemu_console_surface(xenfb->c.con);
+ int dw = surface_width(surface);
+ int dh = surface_height(surface);
int i;
if (xenfb->abs_pointer_wanted)
@@ -353,16 +354,9 @@
struct XenInput *in = container_of(xendev, struct XenInput, c.xendev);
int rc;
- if (!in->c.ds) {
- char *vfb = xenstore_read_str(NULL, "device/vfb");
- if (vfb == NULL) {
- /* there is no vfb, run vkbd on its own */
- in->c.ds = get_displaystate();
- } else {
- g_free(vfb);
- xen_be_printf(xendev, 1, "ds not set (yet)\n");
- return -1;
- }
+ if (!in->c.con) {
+ xen_be_printf(xendev, 1, "ds not set (yet)\n");
+ return -1;
}
rc = common_bind(&in->c);
@@ -615,12 +609,13 @@
*/
static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h)
{
+ DisplaySurface *surface = qemu_console_surface(xenfb->c.con);
int line, oops = 0;
- int bpp = ds_get_bits_per_pixel(xenfb->c.ds);
- int linesize = ds_get_linesize(xenfb->c.ds);
- uint8_t *data = ds_get_data(xenfb->c.ds);
+ int bpp = surface_bits_per_pixel(surface);
+ int linesize = surface_stride(surface);
+ uint8_t *data = surface_data(surface);
- if (!is_buffer_shared(xenfb->c.ds->surface)) {
+ if (!is_buffer_shared(surface)) {
switch (xenfb->depth) {
case 8:
if (bpp == 16) {
@@ -648,10 +643,10 @@
xen_be_printf(&xenfb->c.xendev, 0, "%s: oops: convert %d -> %d bpp?\n",
__FUNCTION__, xenfb->depth, bpp);
- dpy_gfx_update(xenfb->c.ds, x, y, w, h);
+ dpy_gfx_update(xenfb->c.con, x, y, w, h);
}
-#ifdef XENFB_TYPE_REFRESH_PERIOD
+#if 0 /* def XENFB_TYPE_REFRESH_PERIOD */
static int xenfb_queue_full(struct XenFB *xenfb)
{
struct xenfb_page *page = xenfb->c.page;
@@ -703,13 +698,14 @@
static void xenfb_update(void *opaque)
{
struct XenFB *xenfb = opaque;
+ DisplaySurface *surface;
int i;
if (xenfb->c.xendev.be_state != XenbusStateConnected)
return;
if (xenfb->feature_update) {
-#ifdef XENFB_TYPE_REFRESH_PERIOD
+#if 0 /* XENFB_TYPE_REFRESH_PERIOD */
struct DisplayChangeListener *l;
int period = 99999999;
int idle = 1;
@@ -753,21 +749,20 @@
case 16:
case 32:
/* console.c supported depth -> buffer can be used directly */
- qemu_free_displaysurface(xenfb->c.ds);
- xenfb->c.ds->surface = qemu_create_displaysurface_from
+ surface = qemu_create_displaysurface_from
(xenfb->width, xenfb->height, xenfb->depth,
xenfb->row_stride, xenfb->pixels + xenfb->offset,
false);
break;
default:
/* we must convert stuff */
- qemu_resize_displaysurface(xenfb->c.ds, xenfb->width, xenfb->height);
+ surface = qemu_create_displaysurface(xenfb->width, xenfb->height);
break;
}
+ dpy_gfx_replace_surface(xenfb->c.con, surface);
xen_be_printf(&xenfb->c.xendev, 1, "update: resizing: %dx%d @ %d bpp%s\n",
xenfb->width, xenfb->height, xenfb->depth,
- is_buffer_shared(xenfb->c.ds->surface) ? " (shared)" : "");
- dpy_gfx_resize(xenfb->c.ds);
+ is_buffer_shared(surface) ? " (shared)" : "");
xenfb->up_fullscreen = 1;
}
@@ -1009,16 +1004,16 @@
/* vfb */
fb = container_of(xfb, struct XenFB, c.xendev);
- fb->c.ds = graphic_console_init(xenfb_update,
- xenfb_invalidate,
- NULL,
- NULL,
- fb);
+ fb->c.con = graphic_console_init(xenfb_update,
+ xenfb_invalidate,
+ NULL,
+ NULL,
+ fb);
fb->have_console = 1;
/* vkbd */
in = container_of(xin, struct XenInput, c.xendev);
- in->c.ds = fb->c.ds;
+ in->c.con = fb->c.con;
/* retry ->init() */
xen_be_check_state(xin);
diff --git a/hw/xics.h b/hw/xics.h
index c3bf008..6bce042 100644
--- a/hw/xics.h
+++ b/hw/xics.h
@@ -35,6 +35,7 @@
qemu_irq xics_get_qirq(struct icp_state *icp, int irq);
void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi);
-struct icp_state *xics_system_init(int nr_irqs);
+struct icp_state *xics_system_init(int nr_servers, int nr_irqs);
+void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu);
#endif /* __XICS_H__ */
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
index 6c21b96..b2397f4 100644
--- a/hw/xilinx_spips.c
+++ b/hw/xilinx_spips.c
@@ -115,6 +115,19 @@
#define SNOOP_NONE 0xFE
#define SNOOP_STRIPING 0
+typedef enum {
+ READ = 0x3,
+ FAST_READ = 0xb,
+ DOR = 0x3b,
+ QOR = 0x6b,
+ DIOR = 0xbb,
+ QIOR = 0xeb,
+
+ PP = 0x2,
+ DPP = 0xa2,
+ QPP = 0x32,
+} FlashCMD;
+
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
@@ -141,10 +154,15 @@
hwaddr lqspi_cached_addr;
} XilinxSPIPS;
+#define TYPE_XILINX_SPIPS "xilinx,spips"
+
+#define XILINX_SPIPS(obj) \
+ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
+
static inline int num_effective_busses(XilinxSPIPS *s)
{
- return (s->regs[R_LQSPI_STS] & LQSPI_CFG_SEP_BUS &&
- s->regs[R_LQSPI_STS] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
+ return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
+ s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
}
static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
@@ -197,7 +215,7 @@
static void xilinx_spips_reset(DeviceState *d)
{
- XilinxSPIPS *s = DO_UPCAST(XilinxSPIPS, busdev.qdev, d);
+ XilinxSPIPS *s = XILINX_SPIPS(d);
int i;
for (i = 0; i < R_MAX; i++) {
@@ -251,15 +269,19 @@
switch (s->snoop_state) {
case (SNOOP_CHECKING):
switch (tx) { /* new instruction code */
- case 0x0b: /* dual/quad output read DOR/QOR */
- case 0x6b:
+ case READ: /* 3 address bytes, no dummy bytes/cycles */
+ case PP:
+ case DPP:
+ case QPP:
+ s->snoop_state = 3;
+ break;
+ case FAST_READ: /* 3 address bytes, 1 dummy byte */
+ case DOR:
+ case QOR:
+ case DIOR: /* FIXME: these vary between vendor - set to spansion */
s->snoop_state = 4;
break;
- /* FIXME: these vary between vendor - set to spansion */
- case 0xbb: /* high performance dual read DIOR */
- s->snoop_state = 4;
- break;
- case 0xeb: /* high performance quad read QIOR */
+ case QIOR: /* 3 address bytes, 2 dummy bytes */
s->snoop_state = 6;
break;
default:
@@ -483,9 +505,10 @@
}
};
-static int xilinx_spips_init(SysBusDevice *dev)
+static void xilinx_spips_realize(DeviceState *dev, Error **errp)
{
- XilinxSPIPS *s = FROM_SYSBUS(typeof(*s), dev);
+ XilinxSPIPS *s = XILINX_SPIPS(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
DB_PRINT("inited device model\n");
@@ -494,31 +517,29 @@
for (i = 0; i < s->num_busses; ++i) {
char bus_name[16];
snprintf(bus_name, 16, "spi%d", i);
- s->spi[i] = ssi_create_bus(&dev->qdev, bus_name);
+ s->spi[i] = ssi_create_bus(dev, bus_name);
}
- s->cs_lines = g_new(qemu_irq, s->num_cs * s->num_busses);
+ s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
- sysbus_init_irq(dev, &s->irq);
+ sysbus_init_irq(sbd, &s->irq);
for (i = 0; i < s->num_cs * s->num_busses; ++i) {
- sysbus_init_irq(dev, &s->cs_lines[i]);
+ sysbus_init_irq(sbd, &s->cs_lines[i]);
}
memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
- sysbus_init_mmio(dev, &s->iomem);
+ sysbus_init_mmio(sbd, &s->iomem);
memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
(1 << LQSPI_ADDRESS_BITS) * 2);
- sysbus_init_mmio(dev, &s->mmlqspi);
+ sysbus_init_mmio(sbd, &s->mmlqspi);
s->irqline = -1;
s->lqspi_cached_addr = ~0ULL;
fifo8_create(&s->rx_fifo, RXFF_A);
fifo8_create(&s->tx_fifo, TXFF_A);
-
- return 0;
}
static int xilinx_spips_post_load(void *opaque, int version_id)
@@ -552,16 +573,15 @@
static void xilinx_spips_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
- sdc->init = xilinx_spips_init;
+ dc->realize = xilinx_spips_realize;
dc->reset = xilinx_spips_reset;
dc->props = xilinx_spips_properties;
dc->vmsd = &vmstate_xilinx_spips;
}
static const TypeInfo xilinx_spips_info = {
- .name = "xilinx,spips",
+ .name = TYPE_XILINX_SPIPS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XilinxSPIPS),
.class_init = xilinx_spips_class_init,
diff --git a/include/block/block.h b/include/block/block.h
index d4f34d6..9dc6aad 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -135,7 +135,8 @@
void bdrv_delete(BlockDriverState *bs);
int bdrv_parse_cache_flags(const char *mode, int *flags);
int bdrv_parse_discard_flags(const char *mode, int *flags);
-int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
+int bdrv_file_open(BlockDriverState **pbs, const char *filename,
+ QDict *options, int flags);
int bdrv_open_backing_file(BlockDriverState *bs);
int bdrv_open(BlockDriverState *bs, const char *filename, QDict *options,
int flags, BlockDriver *drv);
diff --git a/include/block/block_int.h b/include/block/block_int.h
index ce0aa26..0986a2d 100644
--- a/include/block/block_int.h
+++ b/include/block/block_int.h
@@ -76,6 +76,10 @@
int (*bdrv_probe)(const uint8_t *buf, int buf_size, const char *filename);
int (*bdrv_probe_device)(const char *filename);
+ /* Any driver implementing this callback is expected to be able to handle
+ * NULL file names in its .bdrv_open() implementation */
+ void (*bdrv_parse_filename)(const char *filename, QDict *options, Error **errp);
+
/* For handling image reopen for split or non-split files */
int (*bdrv_reopen_prepare)(BDRVReopenState *reopen_state,
BlockReopenQueue *queue, Error **errp);
@@ -83,7 +87,8 @@
void (*bdrv_reopen_abort)(BDRVReopenState *reopen_state);
int (*bdrv_open)(BlockDriverState *bs, QDict *options, int flags);
- int (*bdrv_file_open)(BlockDriverState *bs, const char *filename, int flags);
+ int (*bdrv_file_open)(BlockDriverState *bs, const char *filename,
+ QDict *options, int flags);
int (*bdrv_read)(BlockDriverState *bs, int64_t sector_num,
uint8_t *buf, int nb_sectors);
int (*bdrv_write)(BlockDriverState *bs, int64_t sector_num,
diff --git a/include/block/nbd.h b/include/block/nbd.h
index 344f05b..0903d7a 100644
--- a/include/block/nbd.h
+++ b/include/block/nbd.h
@@ -22,6 +22,7 @@
#include <sys/types.h>
#include "qemu-common.h"
+#include "qemu/option.h"
struct nbd_request {
uint32_t magic;
@@ -60,10 +61,9 @@
#define NBD_BUFFER_SIZE (1024*1024)
ssize_t nbd_wr_sync(int fd, void *buffer, size_t size, bool do_read);
-int tcp_socket_outgoing(const char *address, uint16_t port);
int tcp_socket_incoming(const char *address, uint16_t port);
-int tcp_socket_outgoing_spec(const char *address_and_port);
int tcp_socket_incoming_spec(const char *address_and_port);
+int tcp_socket_outgoing_opts(QemuOpts *opts);
int unix_socket_outgoing(const char *path);
int unix_socket_incoming(const char *path);
diff --git a/include/char/char.h b/include/char/char.h
index d6a0351..5c3a7a5 100644
--- a/include/char/char.h
+++ b/include/char/char.h
@@ -153,8 +153,8 @@
void qemu_chr_fe_printf(CharDriverState *s, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
-guint qemu_chr_fe_add_watch(CharDriverState *s, GIOCondition cond,
- GIOFunc func, void *user_data);
+int qemu_chr_fe_add_watch(CharDriverState *s, GIOCondition cond,
+ GIOFunc func, void *user_data);
/**
* @qemu_chr_fe_write:
@@ -170,6 +170,21 @@
int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len);
/**
+ * @qemu_chr_fe_write_all:
+ *
+ * Write data to a character backend from the front end. This function will
+ * send data from the front end to the back end. Unlike @qemu_chr_fe_write,
+ * this function will block if the back end cannot consume all of the data
+ * attempted to be written.
+ *
+ * @buf the data
+ * @len the number of bytes to send
+ *
+ * Returns: the number of bytes consumed
+ */
+int qemu_chr_fe_write_all(CharDriverState *s, const uint8_t *buf, int len);
+
+/**
* @qemu_chr_fe_ioctl:
*
* Issue a device specific ioctl to a backend.
diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index 3944b3c..803b6ef 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -218,6 +218,7 @@
#define bfd_mach_cris_v32 32
#define bfd_mach_cris_v10_v32 1032
bfd_arch_microblaze, /* Xilinx MicroBlaze. */
+ bfd_arch_moxie, /* The Moxie core. */
bfd_arch_ia64, /* HP/Intel ia64 */
#define bfd_mach_ia64_elf64 64
#define bfd_mach_ia64_elf32 32
@@ -392,6 +393,7 @@
int print_insn_m88k (bfd_vma, disassemble_info*);
int print_insn_mn10200 (bfd_vma, disassemble_info*);
int print_insn_mn10300 (bfd_vma, disassemble_info*);
+int print_insn_moxie (bfd_vma, disassemble_info*);
int print_insn_ns32k (bfd_vma, disassemble_info*);
int print_insn_big_powerpc (bfd_vma, disassemble_info*);
int print_insn_little_powerpc (bfd_vma, disassemble_info*);
diff --git a/include/glib-compat.h b/include/glib-compat.h
new file mode 100644
index 0000000..8aa77af
--- /dev/null
+++ b/include/glib-compat.h
@@ -0,0 +1,27 @@
+/*
+ * GLIB Compatibility Functions
+ *
+ * Copyright IBM, Corp. 2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef QEMU_GLIB_COMPAT_H
+#define QEMU_GLIB_COMPAT_H
+
+#include <glib.h>
+
+#if !GLIB_CHECK_VERSION(2, 14, 0)
+static inline guint g_timeout_add_seconds(guint interval, GSourceFunc function,
+ gpointer data)
+{
+ return g_timeout_add(interval * 1000, function, data);
+}
+#endif
+
+#endif
diff --git a/include/migration/migration.h b/include/migration/migration.h
index bb617fd..e2acec6 100644
--- a/include/migration/migration.h
+++ b/include/migration/migration.h
@@ -96,6 +96,8 @@
uint64_t dup_mig_bytes_transferred(void);
uint64_t dup_mig_pages_transferred(void);
+uint64_t skipped_mig_bytes_transferred(void);
+uint64_t skipped_mig_pages_transferred(void);
uint64_t norm_mig_bytes_transferred(void);
uint64_t norm_mig_pages_transferred(void);
uint64_t xbzrle_mig_bytes_transferred(void);
diff --git a/include/migration/qemu-file.h b/include/migration/qemu-file.h
index df81261..623c434 100644
--- a/include/migration/qemu-file.h
+++ b/include/migration/qemu-file.h
@@ -51,11 +51,18 @@
*/
typedef int (QEMUFileGetFD)(void *opaque);
+/*
+ * This function writes an iovec to file.
+ */
+typedef ssize_t (QEMUFileWritevBufferFunc)(void *opaque, struct iovec *iov,
+ int iovcnt);
+
typedef struct QEMUFileOps {
QEMUFilePutBufferFunc *put_buffer;
QEMUFileGetBufferFunc *get_buffer;
QEMUFileCloseFunc *close;
QEMUFileGetFD *get_fd;
+ QEMUFileWritevBufferFunc *writev_buffer;
} QEMUFileOps;
QEMUFile *qemu_fopen_ops(void *opaque, const QEMUFileOps *ops);
@@ -68,6 +75,11 @@
int64_t qemu_ftell(QEMUFile *f);
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
void qemu_put_byte(QEMUFile *f, int v);
+/*
+ * put_buffer without copying the buffer.
+ * The buffer should be available till it is sent asynchronously.
+ */
+void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, int size);
static inline void qemu_put_ubyte(QEMUFile *f, unsigned int v)
{
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 6666d27..65918a9 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -149,6 +149,7 @@
extern const VMStateInfo vmstate_info_uint16_equal;
extern const VMStateInfo vmstate_info_int32_equal;
extern const VMStateInfo vmstate_info_uint32_equal;
+extern const VMStateInfo vmstate_info_uint64_equal;
extern const VMStateInfo vmstate_info_int32_le;
extern const VMStateInfo vmstate_info_uint8;
@@ -156,6 +157,8 @@
extern const VMStateInfo vmstate_info_uint32;
extern const VMStateInfo vmstate_info_uint64;
+extern const VMStateInfo vmstate_info_float64;
+
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
extern const VMStateInfo vmstate_info_unused_buffer;
@@ -340,6 +343,16 @@
.offset = vmstate_offset_pointer(_state, _field, _type), \
}
+#define VMSTATE_STRUCT_VARRAY_POINTER_UINT32(_field, _state, _field_num, _vmsd, _type) { \
+ .name = (stringify(_field)), \
+ .version_id = 0, \
+ .num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
+ .size = sizeof(_type), \
+ .vmsd = &(_vmsd), \
+ .flags = VMS_POINTER | VMS_VARRAY_INT32 | VMS_STRUCT, \
+ .offset = vmstate_offset_pointer(_state, _field, _type), \
+}
+
#define VMSTATE_STRUCT_VARRAY_POINTER_UINT16(_field, _state, _field_num, _vmsd, _type) { \
.name = (stringify(_field)), \
.version_id = 0, \
@@ -380,14 +393,14 @@
.offset = vmstate_offset_buffer(_state, _field) + _start, \
}
-#define VMSTATE_BUFFER_MULTIPLY(_field, _state, _version, _test, _start, _field_size, _multiply) { \
+#define VMSTATE_VBUFFER_MULTIPLY(_field, _state, _version, _test, _start, _field_size, _multiply) { \
.name = (stringify(_field)), \
.version_id = (_version), \
.field_exists = (_test), \
.size_offset = vmstate_offset_value(_state, _field_size, uint32_t),\
.size = (_multiply), \
.info = &vmstate_info_buffer, \
- .flags = VMS_VBUFFER|VMS_MULTIPLY, \
+ .flags = VMS_VBUFFER|VMS_POINTER|VMS_MULTIPLY, \
.offset = offsetof(_state, _field), \
.start = (_start), \
}
@@ -518,8 +531,17 @@
#define VMSTATE_INT32_EQUAL(_f, _s) \
VMSTATE_SINGLE(_f, _s, 0, vmstate_info_int32_equal, int32_t)
-#define VMSTATE_UINT32_EQUAL(_f, _s) \
- VMSTATE_SINGLE(_f, _s, 0, vmstate_info_uint32_equal, uint32_t)
+#define VMSTATE_UINT32_EQUAL_V(_f, _s, _v) \
+ VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint32_equal, uint32_t)
+
+#define VMSTATE_UINT32_EQUAL(_f, _s) \
+ VMSTATE_UINT32_EQUAL_V(_f, _s, 0)
+
+#define VMSTATE_UINT64_EQUAL_V(_f, _s, _v) \
+ VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint64_equal, uint64_t)
+
+#define VMSTATE_UINT64_EQUAL(_f, _s) \
+ VMSTATE_UINT64_EQUAL_V(_f, _s, 0)
#define VMSTATE_INT32_LE(_f, _s) \
VMSTATE_SINGLE(_f, _s, 0, vmstate_info_int32_le, int32_t)
@@ -533,6 +555,13 @@
#define VMSTATE_UINT32_TEST(_f, _s, _t) \
VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_info_uint32, uint32_t)
+
+#define VMSTATE_FLOAT64_V(_f, _s, _v) \
+ VMSTATE_SINGLE(_f, _s, _v, vmstate_info_float64, float64)
+
+#define VMSTATE_FLOAT64(_f, _s) \
+ VMSTATE_FLOAT64_V(_f, _s, 0)
+
#define VMSTATE_TIMER_TEST(_f, _s, _test) \
VMSTATE_POINTER_TEST(_f, _s, _test, vmstate_info_timer, QEMUTimer *)
@@ -599,6 +628,12 @@
#define VMSTATE_INT64_ARRAY(_f, _s, _n) \
VMSTATE_INT64_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_FLOAT64_ARRAY_V(_f, _s, _n, _v) \
+ VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_float64, float64)
+
+#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n) \
+ VMSTATE_FLOAT64_ARRAY_V(_f, _s, _n, 0)
+
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
diff --git a/include/net/checksum.h b/include/net/checksum.h
index 1f05298..80203fb 100644
--- a/include/net/checksum.h
+++ b/include/net/checksum.h
@@ -20,10 +20,34 @@
#include <stdint.h>
-uint32_t net_checksum_add(int len, uint8_t *buf);
+uint32_t net_checksum_add_cont(int len, uint8_t *buf, int seq);
uint16_t net_checksum_finish(uint32_t sum);
uint16_t net_checksum_tcpudp(uint16_t length, uint16_t proto,
uint8_t *addrs, uint8_t *buf);
void net_checksum_calculate(uint8_t *data, int length);
+static inline uint32_t
+net_checksum_add(int len, uint8_t *buf)
+{
+ return net_checksum_add_cont(len, buf, 0);
+}
+
+static inline uint16_t
+net_raw_checksum(uint8_t *data, int length)
+{
+ return net_checksum_finish(net_checksum_add(length, data));
+}
+
+/**
+ * net_checksum_add_iov: scatter-gather vector checksumming
+ *
+ * @iov: input scatter-gather array
+ * @iov_cnt: number of array elements
+ * @iov_off: starting iov offset for checksumming
+ * @size: length of data to be checksummed
+ */
+uint32_t net_checksum_add_iov(const struct iovec *iov,
+ const unsigned int iov_cnt,
+ uint32_t iov_off, uint32_t size);
+
#endif /* QEMU_NET_CHECKSUM_H */
diff --git a/include/net/eth.h b/include/net/eth.h
new file mode 100644
index 0000000..1d48e06
--- /dev/null
+++ b/include/net/eth.h
@@ -0,0 +1,347 @@
+/*
+ * QEMU network structures definitions and helper functions
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Portions developed by Free Software Foundation, Inc
+ * Copyright (C) 1991-1997, 2001, 2003, 2006 Free Software Foundation, Inc.
+ * See netinet/ip6.h and netinet/in.h (GNU C Library)
+ *
+ * Portions developed by Igor Kovalenko
+ * Copyright (c) 2006 Igor Kovalenko
+ * See hw/rtl8139.c (QEMU)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef QEMU_ETH_H
+#define QEMU_ETH_H
+
+#include <sys/types.h>
+#include <string.h>
+#include "qemu/bswap.h"
+#include "qemu/iov.h"
+
+#define ETH_ALEN 6
+
+struct eth_header {
+ uint8_t h_dest[ETH_ALEN]; /* destination eth addr */
+ uint8_t h_source[ETH_ALEN]; /* source ether addr */
+ uint16_t h_proto; /* packet type ID field */
+};
+
+struct vlan_header {
+ uint16_t h_tci; /* priority and VLAN ID */
+ uint16_t h_proto; /* encapsulated protocol */
+};
+
+struct ip_header {
+ uint8_t ip_ver_len; /* version and header length */
+ uint8_t ip_tos; /* type of service */
+ uint16_t ip_len; /* total length */
+ uint16_t ip_id; /* identification */
+ uint16_t ip_off; /* fragment offset field */
+ uint8_t ip_ttl; /* time to live */
+ uint8_t ip_p; /* protocol */
+ uint16_t ip_sum; /* checksum */
+ uint32_t ip_src, ip_dst; /* source and destination address */
+};
+
+typedef struct tcp_header {
+ uint16_t th_sport; /* source port */
+ uint16_t th_dport; /* destination port */
+ uint32_t th_seq; /* sequence number */
+ uint32_t th_ack; /* acknowledgment number */
+ uint16_t th_offset_flags; /* data offset, reserved 6 bits, */
+ /* TCP protocol flags */
+ uint16_t th_win; /* window */
+ uint16_t th_sum; /* checksum */
+ uint16_t th_urp; /* urgent pointer */
+} tcp_header;
+
+typedef struct udp_header {
+ uint16_t uh_sport; /* source port */
+ uint16_t uh_dport; /* destination port */
+ uint16_t uh_ulen; /* udp length */
+ uint16_t uh_sum; /* udp checksum */
+} udp_header;
+
+typedef struct ip_pseudo_header {
+ uint32_t ip_src;
+ uint32_t ip_dst;
+ uint8_t zeros;
+ uint8_t ip_proto;
+ uint16_t ip_payload;
+} ip_pseudo_header;
+
+/* IPv6 address */
+struct in6_addr {
+ union {
+ uint8_t __u6_addr8[16];
+ } __in6_u;
+};
+
+struct ip6_header {
+ union {
+ struct ip6_hdrctl {
+ uint32_t ip6_un1_flow; /* 4 bits version, 8 bits TC,
+ 20 bits flow-ID */
+ uint16_t ip6_un1_plen; /* payload length */
+ uint8_t ip6_un1_nxt; /* next header */
+ uint8_t ip6_un1_hlim; /* hop limit */
+ } ip6_un1;
+ uint8_t ip6_un2_vfc; /* 4 bits version, top 4 bits tclass */
+ struct ip6_ecn_access {
+ uint8_t ip6_un3_vfc; /* 4 bits version, top 4 bits tclass */
+ uint8_t ip6_un3_ecn; /* 2 bits ECN, top 6 bits payload length */
+ } ip6_un3;
+ } ip6_ctlun;
+ struct in6_addr ip6_src; /* source address */
+ struct in6_addr ip6_dst; /* destination address */
+};
+
+struct ip6_ext_hdr {
+ uint8_t ip6r_nxt; /* next header */
+ uint8_t ip6r_len; /* length in units of 8 octets */
+};
+
+struct udp_hdr {
+ uint16_t uh_sport; /* source port */
+ uint16_t uh_dport; /* destination port */
+ uint16_t uh_ulen; /* udp length */
+ uint16_t uh_sum; /* udp checksum */
+};
+
+struct tcp_hdr {
+ u_short th_sport; /* source port */
+ u_short th_dport; /* destination port */
+ uint32_t th_seq; /* sequence number */
+ uint32_t th_ack; /* acknowledgment number */
+#ifdef HOST_WORDS_BIGENDIAN
+ u_char th_off : 4, /* data offset */
+ th_x2:4; /* (unused) */
+#else
+ u_char th_x2 : 4, /* (unused) */
+ th_off:4; /* data offset */
+#endif
+
+#define TH_ELN 0x1 /* explicit loss notification */
+#define TH_ECN 0x2 /* explicit congestion notification */
+#define TH_FS 0x4 /* fast start */
+
+ u_char th_flags;
+#define TH_FIN 0x01
+#define TH_SYN 0x02
+#define TH_RST 0x04
+#define TH_PUSH 0x08
+#define TH_ACK 0x10
+#define TH_URG 0x20
+ u_short th_win; /* window */
+ u_short th_sum; /* checksum */
+ u_short th_urp; /* urgent pointer */
+};
+
+#define ip6_nxt ip6_ctlun.ip6_un1.ip6_un1_nxt
+#define ip6_ecn_acc ip6_ctlun.ip6_un3.ip6_un3_ecn
+
+#define PKT_GET_ETH_HDR(p) \
+ ((struct eth_header *)(p))
+#define PKT_GET_VLAN_HDR(p) \
+ ((struct vlan_header *) (((uint8_t *)(p)) + sizeof(struct eth_header)))
+#define PKT_GET_DVLAN_HDR(p) \
+ (PKT_GET_VLAN_HDR(p) + 1)
+#define PKT_GET_IP_HDR(p) \
+ ((struct ip_header *)(((uint8_t *)(p)) + eth_get_l2_hdr_length(p)))
+#define IP_HDR_GET_LEN(p) \
+ ((((struct ip_header *)p)->ip_ver_len & 0x0F) << 2)
+#define PKT_GET_IP_HDR_LEN(p) \
+ (IP_HDR_GET_LEN(PKT_GET_IP_HDR(p)))
+#define PKT_GET_IP6_HDR(p) \
+ ((struct ip6_header *) (((uint8_t *)(p)) + eth_get_l2_hdr_length(p)))
+#define IP_HEADER_VERSION(ip) \
+ ((ip->ip_ver_len >> 4)&0xf)
+
+#define ETH_P_IP (0x0800)
+#define ETH_P_IPV6 (0x86dd)
+#define ETH_P_VLAN (0x8100)
+#define ETH_P_DVLAN (0x88a8)
+#define VLAN_VID_MASK 0x0fff
+#define IP_HEADER_VERSION_4 (4)
+#define IP_HEADER_VERSION_6 (6)
+#define IP_PROTO_TCP (6)
+#define IP_PROTO_UDP (17)
+#define IPTOS_ECN_MASK 0x03
+#define IPTOS_ECN(x) ((x) & IPTOS_ECN_MASK)
+#define IPTOS_ECN_CE 0x03
+#define IP6_ECN_MASK 0xC0
+#define IP6_ECN(x) ((x) & IP6_ECN_MASK)
+#define IP6_ECN_CE 0xC0
+#define IP4_DONT_FRAGMENT_FLAG (1 << 14)
+
+#define IS_SPECIAL_VLAN_ID(x) \
+ (((x) == 0) || ((x) == 0xFFF))
+
+#define ETH_MAX_L2_HDR_LEN \
+ (sizeof(struct eth_header) + 2 * sizeof(struct vlan_header))
+
+#define ETH_MAX_IP4_HDR_LEN (60)
+#define ETH_MAX_IP_DGRAM_LEN (0xFFFF)
+
+#define IP_FRAG_UNIT_SIZE (8)
+#define IP_FRAG_ALIGN_SIZE(x) ((x) & ~0x7)
+#define IP_RF 0x8000 /* reserved fragment flag */
+#define IP_DF 0x4000 /* don't fragment flag */
+#define IP_MF 0x2000 /* more fragments flag */
+#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */
+
+#define IP6_EXT_GRANULARITY (8) /* Size granularity for
+ IPv6 extension headers */
+
+/* IP6 extension header types */
+#define IP6_HOP_BY_HOP (0)
+#define IP6_ROUTING (43)
+#define IP6_FRAGMENT (44)
+#define IP6_ESP (50)
+#define IP6_AUTHENTICATION (51)
+#define IP6_NONE (59)
+#define IP6_DESTINATON (60)
+#define IP6_MOBILITY (135)
+
+static inline int is_multicast_ether_addr(const uint8_t *addr)
+{
+ return 0x01 & addr[0];
+}
+
+static inline int is_broadcast_ether_addr(const uint8_t *addr)
+{
+ return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
+}
+
+static inline int is_unicast_ether_addr(const uint8_t *addr)
+{
+ return !is_multicast_ether_addr(addr);
+}
+
+typedef enum {
+ ETH_PKT_UCAST = 0xAABBCC00,
+ ETH_PKT_BCAST,
+ ETH_PKT_MCAST
+} eth_pkt_types_e;
+
+static inline eth_pkt_types_e
+get_eth_packet_type(const struct eth_header *ehdr)
+{
+ if (is_broadcast_ether_addr(ehdr->h_dest)) {
+ return ETH_PKT_BCAST;
+ } else if (is_multicast_ether_addr(ehdr->h_dest)) {
+ return ETH_PKT_MCAST;
+ } else { /* unicast */
+ return ETH_PKT_UCAST;
+ }
+}
+
+static inline uint32_t
+eth_get_l2_hdr_length(const void *p)
+{
+ uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(p)->h_proto);
+ struct vlan_header *hvlan = PKT_GET_VLAN_HDR(p);
+ switch (proto) {
+ case ETH_P_VLAN:
+ return sizeof(struct eth_header) + sizeof(struct vlan_header);
+ case ETH_P_DVLAN:
+ if (hvlan->h_proto == ETH_P_VLAN) {
+ return sizeof(struct eth_header) + 2 * sizeof(struct vlan_header);
+ } else {
+ return sizeof(struct eth_header) + sizeof(struct vlan_header);
+ }
+ default:
+ return sizeof(struct eth_header);
+ }
+}
+
+static inline uint16_t
+eth_get_pkt_tci(const void *p)
+{
+ uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(p)->h_proto);
+ struct vlan_header *hvlan = PKT_GET_VLAN_HDR(p);
+ switch (proto) {
+ case ETH_P_VLAN:
+ case ETH_P_DVLAN:
+ return be16_to_cpu(hvlan->h_tci);
+ default:
+ return 0;
+ }
+}
+
+static inline bool
+eth_strip_vlan(const void *p, uint8_t *new_ehdr_buf,
+ uint16_t *payload_offset, uint16_t *tci)
+{
+ uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(p)->h_proto);
+ struct vlan_header *hvlan = PKT_GET_VLAN_HDR(p);
+ struct eth_header *new_ehdr = (struct eth_header *) new_ehdr_buf;
+
+ switch (proto) {
+ case ETH_P_VLAN:
+ case ETH_P_DVLAN:
+ memcpy(new_ehdr->h_source, PKT_GET_ETH_HDR(p)->h_source, ETH_ALEN);
+ memcpy(new_ehdr->h_dest, PKT_GET_ETH_HDR(p)->h_dest, ETH_ALEN);
+ new_ehdr->h_proto = hvlan->h_proto;
+ *tci = be16_to_cpu(hvlan->h_tci);
+ *payload_offset =
+ sizeof(struct eth_header) + sizeof(struct vlan_header);
+ if (be16_to_cpu(new_ehdr->h_proto) == ETH_P_VLAN) {
+ memcpy(PKT_GET_VLAN_HDR(new_ehdr),
+ PKT_GET_DVLAN_HDR(p),
+ sizeof(struct vlan_header));
+ *payload_offset += sizeof(struct vlan_header);
+ }
+ return true;
+ default:
+ return false;
+ }
+}
+
+static inline uint16_t
+eth_get_l3_proto(const void *l2hdr, size_t l2hdr_len)
+{
+ uint8_t *proto_ptr = (uint8_t *) l2hdr + l2hdr_len - sizeof(uint16_t);
+ return be16_to_cpup((uint16_t *)proto_ptr);
+}
+
+void eth_setup_vlan_headers(struct eth_header *ehdr, uint16_t vlan_tag,
+ bool *is_new);
+
+uint8_t eth_get_gso_type(uint16_t l3_proto, uint8_t *l3_hdr, uint8_t l4proto);
+
+void eth_get_protocols(const uint8_t *headers,
+ uint32_t hdr_length,
+ bool *isip4, bool *isip6,
+ bool *isudp, bool *istcp);
+
+void eth_setup_ip4_fragmentation(const void *l2hdr, size_t l2hdr_len,
+ void *l3hdr, size_t l3hdr_len,
+ size_t l3payload_len,
+ size_t frag_offset, bool more_frags);
+
+void
+eth_fix_ip4_checksum(void *l3hdr, size_t l3hdr_len);
+
+uint32_t
+eth_calc_pseudo_hdr_csum(struct ip_header *iphdr, uint16_t csl);
+
+bool
+eth_parse_ipv6_hdr(struct iovec *pkt, int pkt_frags,
+ size_t ip6hdr_off, uint8_t *l4proto,
+ size_t *full_hdr_len);
+
+#endif
diff --git a/include/net/net.h b/include/net/net.h
index cb049a1..43d85a1 100644
--- a/include/net/net.h
+++ b/include/net/net.h
@@ -11,6 +11,11 @@
#define MAX_QUEUE_NUM 1024
+/* Maximum GSO packet size (64k) plus plenty of room for
+ * the ethernet and virtio_net headers
+ */
+#define NET_BUFSIZE (4096 + 65536)
+
struct MACAddr {
uint8_t a[6];
};
diff --git a/include/qemu-common.h b/include/qemu-common.h
index 5e13708..31fff22 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -40,7 +40,7 @@
#include <sys/time.h>
#include <assert.h>
#include <signal.h>
-#include <glib.h>
+#include "glib-compat.h"
#ifdef _WIN32
#include "sysemu/os-win32.h"
@@ -442,4 +442,41 @@
int uleb128_encode_small(uint8_t *out, uint32_t n);
int uleb128_decode_small(const uint8_t *in, uint32_t *n);
+/*
+ * Hexdump a buffer to a file. An optional string prefix is added to every line
+ */
+
+void hexdump(const char *buf, FILE *fp, const char *prefix, size_t size);
+
+/* vector definitions */
+#ifdef __ALTIVEC__
+#include <altivec.h>
+#define VECTYPE vector unsigned char
+#define SPLAT(p) vec_splat(vec_ld(0, p), 0)
+#define ALL_EQ(v1, v2) vec_all_eq(v1, v2)
+/* altivec.h may redefine the bool macro as vector type.
+ * Reset it to POSIX semantics. */
+#undef bool
+#define bool _Bool
+#elif defined __SSE2__
+#include <emmintrin.h>
+#define VECTYPE __m128i
+#define SPLAT(p) _mm_set1_epi8(*(p))
+#define ALL_EQ(v1, v2) (_mm_movemask_epi8(_mm_cmpeq_epi8(v1, v2)) == 0xFFFF)
+#else
+#define VECTYPE unsigned long
+#define SPLAT(p) (*(p) * (~0UL / 255))
+#define ALL_EQ(v1, v2) ((v1) == (v2))
+#endif
+
+#define BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR 8
+static inline bool
+can_use_buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+ return (len % (BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR
+ * sizeof(VECTYPE)) == 0
+ && ((uintptr_t) buf) % sizeof(VECTYPE) == 0);
+}
+size_t buffer_find_nonzero_offset(const void *buf, size_t len);
+
#endif
diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h
index ae5c21c..d225f6d 100644
--- a/include/qemu/sockets.h
+++ b/include/qemu/sockets.h
@@ -30,6 +30,8 @@
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
+extern QemuOptsList socket_optslist;
+
/* misc helpers */
int qemu_socket(int domain, int type, int protocol);
int qemu_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
@@ -45,6 +47,7 @@
*/
typedef void NonBlockingConnectHandler(int fd, void *opaque);
+InetSocketAddress *inet_parse(const char *str, Error **errp);
int inet_listen_opts(QemuOpts *opts, int port_offset, Error **errp);
int inet_listen(const char *str, char *ostr, int olen,
int socktype, int port_offset, Error **errp);
diff --git a/include/qom/object.h b/include/qom/object.h
index cf094e7..d0f99c5 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -202,7 +202,7 @@
* Methods are always <emphasis>virtual</emphasis>. Overriding a method in
* #TypeInfo.class_init of a subclass leads to any user of the class obtained
* via OBJECT_GET_CLASS() accessing the overridden function.
- * The original function is not automatically invoked. It is the responsability
+ * The original function is not automatically invoked. It is the responsibility
* of the overriding class to determine whether and when to invoke the method
* being overridden.
*
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 5fc780c..8c8d78e 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -20,6 +20,7 @@
QEMU_ARCH_XTENSA = 4096,
QEMU_ARCH_OPENRISC = 8192,
QEMU_ARCH_UNICORE32 = 0x4000,
+ QEMU_ARCH_MOXIE = 0x8000,
};
extern const uint32_t arch_type;
diff --git a/include/ui/console.h b/include/ui/console.h
index a37cf65..a234c72 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -147,31 +147,43 @@
void cursor_get_mono_image(QEMUCursor *c, int foreground, uint8_t *mask);
void cursor_get_mono_mask(QEMUCursor *c, int transparent, uint8_t *mask);
+typedef struct DisplayChangeListenerOps {
+ const char *dpy_name;
+
+ void (*dpy_refresh)(DisplayChangeListener *dcl);
+
+ void (*dpy_gfx_update)(DisplayChangeListener *dcl,
+ int x, int y, int w, int h);
+ void (*dpy_gfx_switch)(DisplayChangeListener *dcl,
+ struct DisplaySurface *new_surface);
+ void (*dpy_gfx_copy)(DisplayChangeListener *dcl,
+ int src_x, int src_y,
+ int dst_x, int dst_y, int w, int h);
+
+ void (*dpy_text_cursor)(DisplayChangeListener *dcl,
+ int x, int y);
+ void (*dpy_text_resize)(DisplayChangeListener *dcl,
+ int w, int h);
+ void (*dpy_text_update)(DisplayChangeListener *dcl,
+ int x, int y, int w, int h);
+
+ void (*dpy_mouse_set)(DisplayChangeListener *dcl,
+ int x, int y, int on);
+ void (*dpy_cursor_define)(DisplayChangeListener *dcl,
+ QEMUCursor *cursor);
+} DisplayChangeListenerOps;
+
struct DisplayChangeListener {
int idle;
uint64_t gui_timer_interval;
-
- void (*dpy_refresh)(struct DisplayState *s);
-
- void (*dpy_gfx_update)(struct DisplayState *s, int x, int y, int w, int h);
- void (*dpy_gfx_resize)(struct DisplayState *s);
- void (*dpy_gfx_setdata)(struct DisplayState *s);
- void (*dpy_gfx_copy)(struct DisplayState *s, int src_x, int src_y,
- int dst_x, int dst_y, int w, int h);
-
- void (*dpy_text_cursor)(struct DisplayState *s, int x, int y);
- void (*dpy_text_resize)(struct DisplayState *s, int w, int h);
- void (*dpy_text_update)(struct DisplayState *s, int x, int y, int w, int h);
-
- void (*dpy_mouse_set)(struct DisplayState *s, int x, int y, int on);
- void (*dpy_cursor_define)(struct DisplayState *s, QEMUCursor *cursor);
+ const DisplayChangeListenerOps *ops;
+ DisplayState *ds;
QLIST_ENTRY(DisplayChangeListener) next;
};
struct DisplayState {
struct DisplaySurface *surface;
- void *opaque;
struct QEMUTimer *gui_timer;
bool have_gfx;
bool have_text;
@@ -189,11 +201,8 @@
PixelFormat qemu_different_endianness_pixelformat(int bpp);
PixelFormat qemu_default_pixelformat(int bpp);
-DisplaySurface *qemu_create_displaysurface(DisplayState *ds,
- int width, int height);
-DisplaySurface *qemu_resize_displaysurface(DisplayState *ds,
- int width, int height);
-void qemu_free_displaysurface(DisplayState *ds);
+DisplaySurface *qemu_create_displaysurface(int width, int height);
+void qemu_free_displaysurface(DisplaySurface *surface);
static inline int is_surface_bgr(DisplaySurface *surface)
{
@@ -210,208 +219,55 @@
void gui_setup_refresh(DisplayState *ds);
-static inline void register_displaychangelistener(DisplayState *ds, DisplayChangeListener *dcl)
+void register_displaychangelistener(DisplayState *ds,
+ DisplayChangeListener *dcl);
+void unregister_displaychangelistener(DisplayChangeListener *dcl);
+
+void dpy_gfx_update(QemuConsole *con, int x, int y, int w, int h);
+void dpy_gfx_replace_surface(QemuConsole *con,
+ DisplaySurface *surface);
+void dpy_refresh(DisplayState *s);
+void dpy_gfx_copy(QemuConsole *con, int src_x, int src_y,
+ int dst_x, int dst_y, int w, int h);
+void dpy_text_cursor(QemuConsole *con, int x, int y);
+void dpy_text_update(QemuConsole *con, int x, int y, int w, int h);
+void dpy_text_resize(QemuConsole *con, int w, int h);
+void dpy_mouse_set(QemuConsole *con, int x, int y, int on);
+void dpy_cursor_define(QemuConsole *con, QEMUCursor *cursor);
+bool dpy_cursor_define_supported(QemuConsole *con);
+
+static inline int surface_stride(DisplaySurface *s)
{
- QLIST_INSERT_HEAD(&ds->listeners, dcl, next);
- gui_setup_refresh(ds);
- if (dcl->dpy_gfx_resize) {
- dcl->dpy_gfx_resize(ds);
- }
+ return pixman_image_get_stride(s->image);
}
-static inline void unregister_displaychangelistener(DisplayState *ds,
- DisplayChangeListener *dcl)
+static inline void *surface_data(DisplaySurface *s)
{
- QLIST_REMOVE(dcl, next);
- gui_setup_refresh(ds);
+ return pixman_image_get_data(s->image);
}
-static inline void dpy_gfx_update(DisplayState *s, int x, int y, int w, int h)
+static inline int surface_width(DisplaySurface *s)
{
- struct DisplayChangeListener *dcl;
- int width = pixman_image_get_width(s->surface->image);
- int height = pixman_image_get_height(s->surface->image);
-
- x = MAX(x, 0);
- y = MAX(y, 0);
- x = MIN(x, width);
- y = MIN(y, height);
- w = MIN(w, width - x);
- h = MIN(h, height - y);
-
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_gfx_update) {
- dcl->dpy_gfx_update(s, x, y, w, h);
- }
- }
+ return pixman_image_get_width(s->image);
}
-static inline void dpy_gfx_resize(DisplayState *s)
+static inline int surface_height(DisplaySurface *s)
{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_gfx_resize) {
- dcl->dpy_gfx_resize(s);
- }
- }
+ return pixman_image_get_height(s->image);
}
-static inline void dpy_gfx_setdata(DisplayState *s)
+static inline int surface_bits_per_pixel(DisplaySurface *s)
{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_gfx_setdata) {
- dcl->dpy_gfx_setdata(s);
- }
- }
-}
-
-static inline void dpy_refresh(DisplayState *s)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_refresh) {
- dcl->dpy_refresh(s);
- }
- }
-}
-
-static inline void dpy_gfx_copy(struct DisplayState *s, int src_x, int src_y,
- int dst_x, int dst_y, int w, int h)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_gfx_copy) {
- dcl->dpy_gfx_copy(s, src_x, src_y, dst_x, dst_y, w, h);
- } else { /* TODO */
- dcl->dpy_gfx_update(s, dst_x, dst_y, w, h);
- }
- }
-}
-
-static inline void dpy_text_cursor(struct DisplayState *s, int x, int y)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_text_cursor) {
- dcl->dpy_text_cursor(s, x, y);
- }
- }
-}
-
-static inline void dpy_text_update(DisplayState *s, int x, int y, int w, int h)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_text_update) {
- dcl->dpy_text_update(s, x, y, w, h);
- }
- }
-}
-
-static inline void dpy_text_resize(DisplayState *s, int w, int h)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_text_resize) {
- dcl->dpy_text_resize(s, w, h);
- }
- }
-}
-
-static inline void dpy_mouse_set(struct DisplayState *s, int x, int y, int on)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_mouse_set) {
- dcl->dpy_mouse_set(s, x, y, on);
- }
- }
-}
-
-static inline void dpy_cursor_define(struct DisplayState *s, QEMUCursor *cursor)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_cursor_define) {
- dcl->dpy_cursor_define(s, cursor);
- }
- }
-}
-
-static inline bool dpy_cursor_define_supported(struct DisplayState *s)
-{
- struct DisplayChangeListener *dcl;
- QLIST_FOREACH(dcl, &s->listeners, next) {
- if (dcl->dpy_cursor_define) {
- return true;
- }
- }
- return false;
-}
-
-static inline int ds_get_linesize(DisplayState *ds)
-{
- return pixman_image_get_stride(ds->surface->image);
-}
-
-static inline uint8_t* ds_get_data(DisplayState *ds)
-{
- return (void *)pixman_image_get_data(ds->surface->image);
-}
-
-static inline int ds_get_width(DisplayState *ds)
-{
- return pixman_image_get_width(ds->surface->image);
-}
-
-static inline int ds_get_height(DisplayState *ds)
-{
- return pixman_image_get_height(ds->surface->image);
-}
-
-static inline int ds_get_bits_per_pixel(DisplayState *ds)
-{
- int bits = PIXMAN_FORMAT_BPP(ds->surface->format);
+ int bits = PIXMAN_FORMAT_BPP(s->format);
return bits;
}
-static inline int ds_get_bytes_per_pixel(DisplayState *ds)
+static inline int surface_bytes_per_pixel(DisplaySurface *s)
{
- int bits = PIXMAN_FORMAT_BPP(ds->surface->format);
+ int bits = PIXMAN_FORMAT_BPP(s->format);
return (bits + 7) / 8;
}
-static inline pixman_format_code_t ds_get_format(DisplayState *ds)
-{
- return ds->surface->format;
-}
-
-static inline pixman_image_t *ds_get_image(DisplayState *ds)
-{
- return ds->surface->image;
-}
-
-static inline int ds_get_depth(DisplayState *ds)
-{
- return ds->surface->pf.depth;
-}
-
-static inline int ds_get_rmask(DisplayState *ds)
-{
- return ds->surface->pf.rmask;
-}
-
-static inline int ds_get_gmask(DisplayState *ds)
-{
- return ds->surface->pf.gmask;
-}
-
-static inline int ds_get_bmask(DisplayState *ds)
-{
- return ds->surface->pf.bmask;
-}
-
#ifdef CONFIG_CURSES
#include <curses.h>
typedef chtype console_ch_t;
@@ -431,11 +287,11 @@
Error **errp);
typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *);
-DisplayState *graphic_console_init(vga_hw_update_ptr update,
- vga_hw_invalidate_ptr invalidate,
- vga_hw_screen_dump_ptr screen_dump,
- vga_hw_text_update_ptr text_update,
- void *opaque);
+QemuConsole *graphic_console_init(vga_hw_update_ptr update,
+ vga_hw_invalidate_ptr invalidate,
+ vga_hw_screen_dump_ptr screen_dump,
+ vga_hw_text_update_ptr text_update,
+ void *opaque);
void vga_hw_update(void);
void vga_hw_invalidate(void);
@@ -446,9 +302,11 @@
void text_consoles_set_display(DisplayState *ds);
void console_select(unsigned int index);
void console_color_init(DisplayState *ds);
-void qemu_console_resize(DisplayState *ds, int width, int height);
-void qemu_console_copy(DisplayState *ds, int src_x, int src_y,
+void qemu_console_resize(QemuConsole *con, int width, int height);
+void qemu_console_copy(QemuConsole *con, int src_x, int src_y,
int dst_x, int dst_y, int w, int h);
+DisplaySurface *qemu_console_surface(QemuConsole *con);
+DisplayState *qemu_console_displaystate(QemuConsole *console);
typedef CharDriverState *(VcHandler)(ChardevVC *vc);
diff --git a/include/ui/spice-display.h b/include/ui/spice-display.h
index 46f9530..7a20fc4 100644
--- a/include/ui/spice-display.h
+++ b/include/ui/spice-display.h
@@ -71,7 +71,9 @@
typedef struct SimpleSpiceUpdate SimpleSpiceUpdate;
struct SimpleSpiceDisplay {
- DisplayState *ds;
+ QemuConsole *con;
+ DisplaySurface *ds;
+ DisplayChangeListener dcl;
void *buf;
int bufsize;
QXLWorker *worker;
@@ -112,11 +114,12 @@
void qemu_spice_destroy_host_primary(SimpleSpiceDisplay *ssd);
void qemu_spice_vm_change_state_handler(void *opaque, int running,
RunState state);
-void qemu_spice_display_init_common(SimpleSpiceDisplay *ssd, DisplayState *ds);
+void qemu_spice_display_init_common(SimpleSpiceDisplay *ssd);
void qemu_spice_display_update(SimpleSpiceDisplay *ssd,
int x, int y, int w, int h);
-void qemu_spice_display_resize(SimpleSpiceDisplay *ssd);
+void qemu_spice_display_switch(SimpleSpiceDisplay *ssd,
+ DisplaySurface *surface);
void qemu_spice_display_refresh(SimpleSpiceDisplay *ssd);
void qemu_spice_cursor_refresh_unlocked(SimpleSpiceDisplay *ssd);
diff --git a/memory.c b/memory.c
index 92a2196..75ca281 100644
--- a/memory.c
+++ b/memory.c
@@ -1321,7 +1321,7 @@
if (subregion->may_overlap || other->may_overlap) {
continue;
}
- if (int128_gt(int128_make64(offset),
+ if (int128_ge(int128_make64(offset),
int128_add(int128_make64(other->addr), other->size))
|| int128_le(int128_add(int128_make64(offset), subregion->size),
int128_make64(other->addr))) {
diff --git a/migration.c b/migration.c
index 185d112..7fb2147 100644
--- a/migration.c
+++ b/migration.c
@@ -197,11 +197,11 @@
info->ram->remaining = ram_bytes_remaining();
info->ram->total = ram_bytes_total();
info->ram->duplicate = dup_mig_pages_transferred();
+ info->ram->skipped = skipped_mig_pages_transferred();
info->ram->normal = norm_mig_pages_transferred();
info->ram->normal_bytes = norm_mig_bytes_transferred();
info->ram->dirty_pages_rate = s->dirty_pages_rate;
-
if (blk_mig_active()) {
info->has_disk = true;
info->disk = g_malloc0(sizeof(*info->disk));
@@ -227,6 +227,7 @@
info->ram->remaining = 0;
info->ram->total = ram_bytes_total();
info->ram->duplicate = dup_mig_pages_transferred();
+ info->ram->skipped = skipped_mig_pages_transferred();
info->ram->normal = norm_mig_pages_transferred();
info->ram->normal_bytes = norm_mig_bytes_transferred();
break;
diff --git a/monitor.c b/monitor.c
index 2fdfb79..5dfae2a 100644
--- a/monitor.c
+++ b/monitor.c
@@ -261,11 +261,30 @@
}
}
+static gboolean monitor_unblocked(GIOChannel *chan, GIOCondition cond,
+ void *opaque)
+{
+ monitor_flush(opaque);
+ return FALSE;
+}
+
void monitor_flush(Monitor *mon)
{
+ int rc;
+
if (mon && mon->outbuf_index != 0 && !mon->mux_out) {
- qemu_chr_fe_write(mon->chr, mon->outbuf, mon->outbuf_index);
- mon->outbuf_index = 0;
+ rc = qemu_chr_fe_write(mon->chr, mon->outbuf, mon->outbuf_index);
+ if (rc == mon->outbuf_index) {
+ /* all flushed */
+ mon->outbuf_index = 0;
+ return;
+ }
+ if (rc > 0) {
+ /* partinal write */
+ memmove(mon->outbuf, mon->outbuf + rc, mon->outbuf_index - rc);
+ mon->outbuf_index -= rc;
+ }
+ qemu_chr_fe_add_watch(mon->chr, G_IO_OUT, monitor_unblocked, mon);
}
}
@@ -2728,6 +2747,13 @@
.mhandler.cmd = hmp_info_tpm,
},
{
+ .name = "cpu_max",
+ .args_type = "",
+ .params = "",
+ .help = "Get maximum number of VCPUs supported by machine",
+ .mhandler.cmd = hmp_query_cpu_max,
+ },
+ {
.name = NULL,
},
};
@@ -2942,10 +2968,6 @@
{ "xer", 0, &monitor_get_xer, },
{ "tbu", 0, &monitor_get_tbu, },
{ "tbl", 0, &monitor_get_tbl, },
-#if defined(TARGET_PPC64)
- /* Address space register */
- { "asr", offsetof(CPUPPCState, asr) },
-#endif
/* Segment registers */
{ "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
{ "sr0", offsetof(CPUPPCState, sr[0]) },
@@ -3542,10 +3564,10 @@
* If @cmdline is blank, return NULL.
* If it can't be parsed, report to @mon, and return NULL.
* Else, insert command arguments into @qdict, and return the command.
- * If sub-command table exist, and if @cmdline contains addtional string for
- * sub-command, this function will try search sub-command table. if no
- * addtional string for sub-command exist, this function will return the found
- * one in @table.
+ * If a sub-command table exists, and if @cmdline contains an additional string
+ * for a sub-command, this function will try to search the sub-command table.
+ * If no additional string for a sub-command is present, this function will
+ * return the command found in @table.
* Do not assume the returned command points into @table! It doesn't
* when the command is a sub-command.
*/
diff --git a/nbd.c b/nbd.c
index 0698a02..d1a67ee 100644
--- a/nbd.c
+++ b/nbd.c
@@ -199,22 +199,15 @@
}
}
-int tcp_socket_outgoing(const char *address, uint16_t port)
-{
- char address_and_port[128];
- combine_addr(address_and_port, 128, address, port);
- return tcp_socket_outgoing_spec(address_and_port);
-}
-
-int tcp_socket_outgoing_spec(const char *address_and_port)
+int tcp_socket_outgoing_opts(QemuOpts *opts)
{
Error *local_err = NULL;
- int fd = inet_connect(address_and_port, &local_err);
-
+ int fd = inet_connect_opts(opts, &local_err, NULL, NULL);
if (local_err != NULL) {
qerror_report_err(local_err);
error_free(local_err);
}
+
return fd;
}
diff --git a/net/Makefile.objs b/net/Makefile.objs
index a08cd14..4854a14 100644
--- a/net/Makefile.objs
+++ b/net/Makefile.objs
@@ -1,6 +1,7 @@
common-obj-y = net.o queue.o checksum.o util.o hub.o
common-obj-y += socket.o
common-obj-y += dump.o
+common-obj-y += eth.o
common-obj-$(CONFIG_POSIX) += tap.o
common-obj-$(CONFIG_LINUX) += tap-linux.o
common-obj-$(CONFIG_WIN32) += tap-win32.o
diff --git a/net/checksum.c b/net/checksum.c
index 9919b2e..14c0855 100644
--- a/net/checksum.c
+++ b/net/checksum.c
@@ -15,21 +15,23 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu-common.h"
#include "net/checksum.h"
#define PROTO_TCP 6
#define PROTO_UDP 17
-uint32_t net_checksum_add(int len, uint8_t *buf)
+uint32_t net_checksum_add_cont(int len, uint8_t *buf, int seq)
{
uint32_t sum = 0;
int i;
- for (i = 0; i < len; i++) {
- if (i & 1)
- sum += (uint32_t)buf[i];
- else
- sum += (uint32_t)buf[i] << 8;
+ for (i = seq; i < seq + len; i++) {
+ if (i & 1) {
+ sum += (uint32_t)buf[i - seq];
+ } else {
+ sum += (uint32_t)buf[i - seq] << 8;
+ }
}
return sum;
}
@@ -83,3 +85,31 @@
data[14+hlen+csum_offset] = csum >> 8;
data[14+hlen+csum_offset+1] = csum & 0xff;
}
+
+uint32_t
+net_checksum_add_iov(const struct iovec *iov, const unsigned int iov_cnt,
+ uint32_t iov_off, uint32_t size)
+{
+ size_t iovec_off, buf_off;
+ unsigned int i;
+ uint32_t res = 0;
+ uint32_t seq = 0;
+
+ iovec_off = 0;
+ buf_off = 0;
+ for (i = 0; i < iov_cnt && size; i++) {
+ if (iov_off < (iovec_off + iov[i].iov_len)) {
+ size_t len = MIN((iovec_off + iov[i].iov_len) - iov_off , size);
+ void *chunk_buf = iov[i].iov_base + (iov_off - iovec_off);
+
+ res += net_checksum_add_cont(len, chunk_buf, seq);
+ seq += len;
+
+ buf_off += len;
+ iov_off += len;
+ size -= len;
+ }
+ iovec_off += iov[i].iov_len;
+ }
+ return res;
+}
diff --git a/net/eth.c b/net/eth.c
new file mode 100644
index 0000000..1d7494d
--- /dev/null
+++ b/net/eth.c
@@ -0,0 +1,217 @@
+/*
+ * QEMU network structures definitions and helper functions
+ *
+ * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
+ *
+ * Developed by Daynix Computing LTD (http://www.daynix.com)
+ *
+ * Authors:
+ * Dmitry Fleytman <dmitry@daynix.com>
+ * Tamir Shomer <tamirs@daynix.com>
+ * Yan Vugenfirer <yan@daynix.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "net/eth.h"
+#include "net/checksum.h"
+#include "qemu-common.h"
+#include "net/tap.h"
+
+void eth_setup_vlan_headers(struct eth_header *ehdr, uint16_t vlan_tag,
+ bool *is_new)
+{
+ struct vlan_header *vhdr = PKT_GET_VLAN_HDR(ehdr);
+
+ switch (be16_to_cpu(ehdr->h_proto)) {
+ case ETH_P_VLAN:
+ case ETH_P_DVLAN:
+ /* vlan hdr exists */
+ *is_new = false;
+ break;
+
+ default:
+ /* No VLAN header, put a new one */
+ vhdr->h_proto = ehdr->h_proto;
+ ehdr->h_proto = cpu_to_be16(ETH_P_VLAN);
+ *is_new = true;
+ break;
+ }
+ vhdr->h_tci = cpu_to_be16(vlan_tag);
+}
+
+uint8_t
+eth_get_gso_type(uint16_t l3_proto, uint8_t *l3_hdr, uint8_t l4proto)
+{
+ uint8_t ecn_state = 0;
+
+ if (l3_proto == ETH_P_IP) {
+ struct ip_header *iphdr = (struct ip_header *) l3_hdr;
+
+ if (IP_HEADER_VERSION(iphdr) == IP_HEADER_VERSION_4) {
+ if (IPTOS_ECN(iphdr->ip_tos) == IPTOS_ECN_CE) {
+ ecn_state = VIRTIO_NET_HDR_GSO_ECN;
+ }
+ if (l4proto == IP_PROTO_TCP) {
+ return VIRTIO_NET_HDR_GSO_TCPV4 | ecn_state;
+ } else if (l4proto == IP_PROTO_UDP) {
+ return VIRTIO_NET_HDR_GSO_UDP | ecn_state;
+ }
+ }
+ } else if (l3_proto == ETH_P_IPV6) {
+ struct ip6_header *ip6hdr = (struct ip6_header *) l3_hdr;
+
+ if (IP6_ECN(ip6hdr->ip6_ecn_acc) == IP6_ECN_CE) {
+ ecn_state = VIRTIO_NET_HDR_GSO_ECN;
+ }
+
+ if (l4proto == IP_PROTO_TCP) {
+ return VIRTIO_NET_HDR_GSO_TCPV6 | ecn_state;
+ }
+ }
+
+ /* Unsupported offload */
+ assert(false);
+
+ return VIRTIO_NET_HDR_GSO_NONE | ecn_state;
+}
+
+void eth_get_protocols(const uint8_t *headers,
+ uint32_t hdr_length,
+ bool *isip4, bool *isip6,
+ bool *isudp, bool *istcp)
+{
+ int proto;
+ size_t l2hdr_len = eth_get_l2_hdr_length(headers);
+ assert(hdr_length >= eth_get_l2_hdr_length(headers));
+ *isip4 = *isip6 = *isudp = *istcp = false;
+
+ proto = eth_get_l3_proto(headers, l2hdr_len);
+ if (proto == ETH_P_IP) {
+ *isip4 = true;
+
+ struct ip_header *iphdr;
+
+ assert(hdr_length >=
+ eth_get_l2_hdr_length(headers) + sizeof(struct ip_header));
+
+ iphdr = PKT_GET_IP_HDR(headers);
+
+ if (IP_HEADER_VERSION(iphdr) == IP_HEADER_VERSION_4) {
+ if (iphdr->ip_p == IP_PROTO_TCP) {
+ *istcp = true;
+ } else if (iphdr->ip_p == IP_PROTO_UDP) {
+ *isudp = true;
+ }
+ }
+ } else if (proto == ETH_P_IPV6) {
+ uint8_t l4proto;
+ size_t full_ip6hdr_len;
+
+ struct iovec hdr_vec;
+ hdr_vec.iov_base = (void *) headers;
+ hdr_vec.iov_len = hdr_length;
+
+ *isip6 = true;
+ if (eth_parse_ipv6_hdr(&hdr_vec, 1, l2hdr_len,
+ &l4proto, &full_ip6hdr_len)) {
+ if (l4proto == IP_PROTO_TCP) {
+ *istcp = true;
+ } else if (l4proto == IP_PROTO_UDP) {
+ *isudp = true;
+ }
+ }
+ }
+}
+
+void
+eth_setup_ip4_fragmentation(const void *l2hdr, size_t l2hdr_len,
+ void *l3hdr, size_t l3hdr_len,
+ size_t l3payload_len,
+ size_t frag_offset, bool more_frags)
+{
+ if (eth_get_l3_proto(l2hdr, l2hdr_len) == ETH_P_IP) {
+ uint16_t orig_flags;
+ struct ip_header *iphdr = (struct ip_header *) l3hdr;
+ uint16_t frag_off_units = frag_offset / IP_FRAG_UNIT_SIZE;
+ uint16_t new_ip_off;
+
+ assert(frag_offset % IP_FRAG_UNIT_SIZE == 0);
+ assert((frag_off_units & ~IP_OFFMASK) == 0);
+
+ orig_flags = be16_to_cpu(iphdr->ip_off) & ~(IP_OFFMASK|IP_MF);
+ new_ip_off = frag_off_units | orig_flags | (more_frags ? IP_MF : 0);
+ iphdr->ip_off = cpu_to_be16(new_ip_off);
+ iphdr->ip_len = cpu_to_be16(l3payload_len + l3hdr_len);
+ }
+}
+
+void
+eth_fix_ip4_checksum(void *l3hdr, size_t l3hdr_len)
+{
+ struct ip_header *iphdr = (struct ip_header *) l3hdr;
+ iphdr->ip_sum = 0;
+ iphdr->ip_sum = cpu_to_be16(net_raw_checksum(l3hdr, l3hdr_len));
+}
+
+uint32_t
+eth_calc_pseudo_hdr_csum(struct ip_header *iphdr, uint16_t csl)
+{
+ struct ip_pseudo_header ipph;
+ ipph.ip_src = iphdr->ip_src;
+ ipph.ip_dst = iphdr->ip_dst;
+ ipph.ip_payload = cpu_to_be16(csl);
+ ipph.ip_proto = iphdr->ip_p;
+ ipph.zeros = 0;
+ return net_checksum_add(sizeof(ipph), (uint8_t *) &ipph);
+}
+
+static bool
+eth_is_ip6_extension_header_type(uint8_t hdr_type)
+{
+ switch (hdr_type) {
+ case IP6_HOP_BY_HOP:
+ case IP6_ROUTING:
+ case IP6_FRAGMENT:
+ case IP6_ESP:
+ case IP6_AUTHENTICATION:
+ case IP6_DESTINATON:
+ case IP6_MOBILITY:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool eth_parse_ipv6_hdr(struct iovec *pkt, int pkt_frags,
+ size_t ip6hdr_off, uint8_t *l4proto,
+ size_t *full_hdr_len)
+{
+ struct ip6_header ip6_hdr;
+ struct ip6_ext_hdr ext_hdr;
+ size_t bytes_read;
+
+ bytes_read = iov_to_buf(pkt, pkt_frags, ip6hdr_off,
+ &ip6_hdr, sizeof(ip6_hdr));
+ if (bytes_read < sizeof(ip6_hdr)) {
+ return false;
+ }
+
+ *full_hdr_len = sizeof(struct ip6_header);
+
+ if (!eth_is_ip6_extension_header_type(ip6_hdr.ip6_nxt)) {
+ *l4proto = ip6_hdr.ip6_nxt;
+ return true;
+ }
+
+ do {
+ bytes_read = iov_to_buf(pkt, pkt_frags, ip6hdr_off + *full_hdr_len,
+ &ext_hdr, sizeof(ext_hdr));
+ *full_hdr_len += (ext_hdr.ip6r_len + 1) * IP6_EXT_GRANULARITY;
+ } while (eth_is_ip6_extension_header_type(ext_hdr.ip6r_nxt));
+
+ *l4proto = ext_hdr.ip6r_nxt;
+ return true;
+}
diff --git a/net/net.c b/net/net.c
index f3d67f8..7869161 100644
--- a/net/net.c
+++ b/net/net.c
@@ -497,7 +497,7 @@
static ssize_t nc_sendv_compat(NetClientState *nc, const struct iovec *iov,
int iovcnt)
{
- uint8_t buffer[4096];
+ uint8_t buffer[NET_BUFSIZE];
size_t offset;
offset = iov_to_buf(iov, iovcnt, 0, buffer, sizeof(buffer));
diff --git a/net/socket.c b/net/socket.c
index 396dc8c..6c3752b 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -40,7 +40,7 @@
unsigned int index;
unsigned int packet_len;
unsigned int send_index; /* number of bytes sent (only SOCK_STREAM) */
- uint8_t buf[4096];
+ uint8_t buf[NET_BUFSIZE];
struct sockaddr_in dgram_dst; /* contains inet host and port destination iff connectionless (SOCK_DGRAM) */
IOHandler *send_fn; /* differs between SOCK_STREAM/SOCK_DGRAM */
bool read_poll; /* waiting to receive data? */
@@ -146,7 +146,7 @@
NetSocketState *s = opaque;
int size, err;
unsigned l;
- uint8_t buf1[4096];
+ uint8_t buf1[NET_BUFSIZE];
const uint8_t *buf;
size = qemu_recv(s->fd, buf1, sizeof(buf1), 0);
@@ -262,8 +262,7 @@
}
val = 1;
- ret=setsockopt(fd, SOL_SOCKET, SO_REUSEADDR,
- (const char *)&val, sizeof(val));
+ ret = qemu_setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val));
if (ret < 0) {
perror("setsockopt(SOL_SOCKET, SO_REUSEADDR)");
goto fail;
@@ -283,8 +282,8 @@
imr.imr_interface.s_addr = htonl(INADDR_ANY);
}
- ret = setsockopt(fd, IPPROTO_IP, IP_ADD_MEMBERSHIP,
- (const char *)&imr, sizeof(struct ip_mreq));
+ ret = qemu_setsockopt(fd, IPPROTO_IP, IP_ADD_MEMBERSHIP,
+ &imr, sizeof(struct ip_mreq));
if (ret < 0) {
perror("setsockopt(IP_ADD_MEMBERSHIP)");
goto fail;
@@ -292,8 +291,8 @@
/* Force mcast msgs to loopback (eg. several QEMUs in same host */
loop = 1;
- ret=setsockopt(fd, IPPROTO_IP, IP_MULTICAST_LOOP,
- (const char *)&loop, sizeof(loop));
+ ret = qemu_setsockopt(fd, IPPROTO_IP, IP_MULTICAST_LOOP,
+ &loop, sizeof(loop));
if (ret < 0) {
perror("setsockopt(SOL_IP, IP_MULTICAST_LOOP)");
goto fail;
@@ -301,8 +300,8 @@
/* If a bind address is given, only send packets from that address */
if (localaddr != NULL) {
- ret = setsockopt(fd, IPPROTO_IP, IP_MULTICAST_IF,
- (const char *)localaddr, sizeof(*localaddr));
+ ret = qemu_setsockopt(fd, IPPROTO_IP, IP_MULTICAST_IF,
+ localaddr, sizeof(*localaddr));
if (ret < 0) {
perror("setsockopt(IP_MULTICAST_IF)");
goto fail;
@@ -439,6 +438,9 @@
s->fd = fd;
s->listen_fd = -1;
+ /* Disable Nagle algorithm on TCP sockets to reduce latency */
+ socket_set_nodelay(fd);
+
if (is_connected) {
net_socket_connect(s);
} else {
@@ -521,7 +523,7 @@
/* allow fast reuse */
val = 1;
- setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (const char *)&val, sizeof(val));
+ qemu_setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val));
ret = bind(fd, (struct sockaddr *)&saddr, sizeof(saddr));
if (ret < 0) {
@@ -659,8 +661,8 @@
return -1;
}
val = 1;
- ret = setsockopt(fd, SOL_SOCKET, SO_REUSEADDR,
- (const char *)&val, sizeof(val));
+ ret = qemu_setsockopt(fd, SOL_SOCKET, SO_REUSEADDR,
+ &val, sizeof(val));
if (ret < 0) {
perror("setsockopt(SOL_SOCKET, SO_REUSEADDR)");
closesocket(fd);
diff --git a/net/tap.c b/net/tap.c
index daab350..e7c8481 100644
--- a/net/tap.c
+++ b/net/tap.c
@@ -44,17 +44,12 @@
#include "hw/vhost_net.h"
-/* Maximum GSO packet size (64k) plus plenty of room for
- * the ethernet and virtio_net headers
- */
-#define TAP_BUFSIZE (4096 + 65536)
-
typedef struct TAPState {
NetClientState nc;
int fd;
char down_script[1024];
char down_script_arg[128];
- uint8_t buf[TAP_BUFSIZE];
+ uint8_t buf[NET_BUFSIZE];
bool read_poll;
bool write_poll;
bool using_vnet_hdr;
@@ -696,7 +691,7 @@
/* QEMU vlans does not support multiqueue tap, in this case peer is set.
* For -netdev, peer is always NULL. */
if (peer && (tap->has_queues || tap->has_fds || tap->has_vhostfds)) {
- error_report("Multiqueue tap cannnot be used with QEMU vlans");
+ error_report("Multiqueue tap cannot be used with QEMU vlans");
return -1;
}
diff --git a/net/vde.c b/net/vde.c
index 4dea32d..2a619fb 100644
--- a/net/vde.c
+++ b/net/vde.c
@@ -39,7 +39,7 @@
static void vde_to_qemu(void *opaque)
{
VDEState *s = opaque;
- uint8_t buf[4096];
+ uint8_t buf[NET_BUFSIZE];
int size;
size = vde_recv(s->vde, (char *)buf, sizeof(buf), 0);
diff --git a/pc-bios/efi-e1000.rom b/pc-bios/efi-e1000.rom
new file mode 100644
index 0000000..21b880a
--- /dev/null
+++ b/pc-bios/efi-e1000.rom
Binary files differ
diff --git a/pc-bios/efi-eepro100.rom b/pc-bios/efi-eepro100.rom
new file mode 100644
index 0000000..1799c38
--- /dev/null
+++ b/pc-bios/efi-eepro100.rom
Binary files differ
diff --git a/pc-bios/efi-ne2k_pci.rom b/pc-bios/efi-ne2k_pci.rom
new file mode 100644
index 0000000..5d1b38b
--- /dev/null
+++ b/pc-bios/efi-ne2k_pci.rom
Binary files differ
diff --git a/pc-bios/efi-pcnet.rom b/pc-bios/efi-pcnet.rom
new file mode 100644
index 0000000..79fa7a9
--- /dev/null
+++ b/pc-bios/efi-pcnet.rom
Binary files differ
diff --git a/pc-bios/efi-rtl8139.rom b/pc-bios/efi-rtl8139.rom
new file mode 100644
index 0000000..0b78f1a
--- /dev/null
+++ b/pc-bios/efi-rtl8139.rom
Binary files differ
diff --git a/pc-bios/efi-virtio.rom b/pc-bios/efi-virtio.rom
new file mode 100644
index 0000000..e6b2bf7
--- /dev/null
+++ b/pc-bios/efi-virtio.rom
Binary files differ
diff --git a/qapi-schema.json b/qapi-schema.json
index 080dc39..f629a24 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -496,7 +496,9 @@
#
# @total: total amount of bytes involved in the migration process
#
-# @duplicate: number of duplicate pages (since 1.2)
+# @duplicate: number of duplicate (zero) pages (since 1.2)
+#
+# @skipped: number of skipped zero pages (since 1.5)
#
# @normal : number of normal pages (since 1.2)
#
@@ -509,8 +511,8 @@
##
{ 'type': 'MigrationStats',
'data': {'transferred': 'int', 'remaining': 'int', 'total': 'int' ,
- 'duplicate': 'int', 'normal': 'int', 'normal-bytes': 'int',
- 'dirty-pages-rate' : 'int' } }
+ 'duplicate': 'int', 'skipped': 'int', 'normal': 'int',
+ 'normal-bytes': 'int', 'dirty-pages-rate' : 'int' } }
##
# @XBZRLECacheStats
@@ -1832,6 +1834,17 @@
{ 'command': 'query-migrate-cache-size', 'returns': 'int' }
##
+## @query-cpu-max
+##
+## query maximum number of CPUs supported by machine
+##
+## Returns: number of CPUs
+##
+## Since: 1.5
+###
+{ 'command': 'query-cpu-max', 'returns': 'int' }
+
+##
# @ObjectPropertyInfo:
#
# @name: the name of the property
@@ -2996,9 +3009,9 @@
##
{ 'enum': 'TargetType',
'data': [ 'alpha', 'arm', 'cris', 'i386', 'lm32', 'm68k', 'microblazeel',
- 'microblaze', 'mips64el', 'mips64', 'mipsel', 'mips', 'or32',
- 'ppc64', 'ppcemb', 'ppc', 's390x', 'sh4eb', 'sh4', 'sparc64',
- 'sparc', 'unicore32', 'x86_64', 'xtensaeb', 'xtensa' ] }
+ 'microblaze', 'mips64el', 'mips64', 'mipsel', 'mips', 'moxie',
+ 'or32', 'ppc64', 'ppcemb', 'ppc', 's390x', 'sh4eb', 'sh4',
+ 'sparc64', 'sparc', 'unicore32', 'x86_64', 'xtensaeb', 'xtensa' ] }
##
# @TargetInfo:
@@ -3405,13 +3418,12 @@
#
# A union referencing different TPM backend types' configuration options
#
-# @tpm-passthough-options: TPMPassthroughOptions describing the TPM
-# passthrough configuration options
+# @passthrough: The configuration options for the TPM passthrough type
#
# Since: 1.5
##
{ 'union': 'TpmTypeOptions',
- 'data': { 'tpm-passthrough-options' : 'TPMPassthroughOptions' } }
+ 'data': { 'passthrough' : 'TPMPassthroughOptions' } }
##
# @TpmInfo:
@@ -3422,17 +3434,14 @@
#
# @model: The TPM frontend model
#
-# @type: The TPM (backend) type being used
-#
-# @tpm-options: The TPM (backend) type configuration options
+# @options: The TPM (backend) type configuration options
#
# Since: 1.5
##
{ 'type': 'TPMInfo',
'data': {'id': 'str',
'model': 'TpmModel',
- 'type': 'TpmType',
- 'tpm-options': 'TpmTypeOptions' } }
+ 'options': 'TpmTypeOptions' } }
##
# @query-tpm:
diff --git a/qemu-char.c b/qemu-char.c
index e633797..936150f 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -140,6 +140,33 @@
return s->chr_write(s, buf, len);
}
+int qemu_chr_fe_write_all(CharDriverState *s, const uint8_t *buf, int len)
+{
+ int offset = 0;
+ int res;
+
+ while (offset < len) {
+ do {
+ res = s->chr_write(s, buf + offset, len - offset);
+ if (res == -1 && errno == EAGAIN) {
+ g_usleep(100);
+ }
+ } while (res == -1 && errno == EAGAIN);
+
+ if (res == 0) {
+ break;
+ }
+
+ if (res < 0) {
+ return res;
+ }
+
+ offset += res;
+ }
+
+ return offset;
+}
+
int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg)
{
if (!s->chr_ioctl)
@@ -3397,8 +3424,8 @@
}
}
-guint qemu_chr_fe_add_watch(CharDriverState *s, GIOCondition cond,
- GIOFunc func, void *user_data)
+int qemu_chr_fe_add_watch(CharDriverState *s, GIOCondition cond,
+ GIOFunc func, void *user_data)
{
GSource *src;
guint tag;
diff --git a/qemu-io.c b/qemu-io.c
index 79be516..475a8bd 100644
--- a/qemu-io.c
+++ b/qemu-io.c
@@ -1766,7 +1766,7 @@
}
if (growable) {
- if (bdrv_file_open(&bs, name, flags)) {
+ if (bdrv_file_open(&bs, name, NULL, flags)) {
fprintf(stderr, "%s: can't open device %s\n", progname, name);
return 1;
}
diff --git a/qemu-options.hx b/qemu-options.hx
index 30fb85d..c40ba55 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -161,14 +161,14 @@
DEF("boot", HAS_ARG, QEMU_OPTION_boot,
"-boot [order=drives][,once=drives][,menu=on|off]\n"
- " [,splash=sp_name][,splash-time=sp_time][,reboot-timeout=rb_time]\n"
+ " [,splash=sp_name][,splash-time=sp_time][,reboot-timeout=rb_time][,strict=on|off]\n"
" 'drives': floppy (a), hard disk (c), CD-ROM (d), network (n)\n"
" 'sp_name': the file's name that would be passed to bios as logo picture, if menu=on\n"
" 'sp_time': the period that splash picture last if menu=on, unit is ms\n"
" 'rb_timeout': the timeout before guest reboot when boot failed, unit is ms\n",
QEMU_ARCH_ALL)
STEXI
-@item -boot [order=@var{drives}][,once=@var{drives}][,menu=on|off][,splash=@var{sp_name}][,splash-time=@var{sp_time}][,reboot-timeout=@var{rb_timeout}]
+@item -boot [order=@var{drives}][,once=@var{drives}][,menu=on|off][,splash=@var{sp_name}][,splash-time=@var{sp_time}][,reboot-timeout=@var{rb_timeout}][,strict=on|off]
@findex -boot
Specify boot order @var{drives} as a string of drive letters. Valid
drive letters depend on the target achitecture. The x86 PC uses: a, b
@@ -192,6 +192,10 @@
reboot, qemu passes '-1' to bios by default. Currently Seabios for X86
system support it.
+Do strict boot via @option{strict=on} as far as firmware/BIOS
+supports it. This only effects when boot priority is changed by
+bootindex options. The default is non-strict boot.
+
@example
# try to boot from network first, then from hard disk
qemu-system-i386 -boot order=nc
@@ -1119,7 +1123,7 @@
@item websocket
Opens an additional TCP listening port dedicated to VNC Websocket connections.
-By defintion the Websocket port is 5700+@var{display}. If @var{host} is
+By definition the Websocket port is 5700+@var{display}. If @var{host} is
specified connections will only be allowed from this host.
As an alternative the Websocket port could be specified by using
@code{websocket}=@var{port}.
@@ -2237,7 +2241,8 @@
@option{passthrough}.
The specific backend type will determine the applicable options.
-The @code{-tpmdev} option requires a @code{-device} option.
+The @code{-tpmdev} option creates the TPM backend and requires a
+@code{-device} option that specifies the TPM frontend interface model.
Options to each backend are described below.
diff --git a/qga/commands-posix.c b/qga/commands-posix.c
index d7da850..3b5c536 100644
--- a/qga/commands-posix.c
+++ b/qga/commands-posix.c
@@ -120,7 +120,7 @@
return;
}
- /* succeded */
+ /* succeeded */
}
int64_t qmp_guest_get_time(Error **errp)
diff --git a/qmp-commands.hx b/qmp-commands.hx
index b370060..1e0e11e 100644
--- a/qmp-commands.hx
+++ b/qmp-commands.hx
@@ -385,6 +385,28 @@
EQMP
{
+ .name = "query-cpu-max",
+ .args_type = "",
+ .mhandler.cmd_new = qmp_marshal_input_query_cpu_max,
+ },
+
+SQMP
+query-cpu-max
+-------------
+
+Get the maximum CPUs supported by the machine being currently
+emulated.
+
+Returns json-int.
+
+Example:
+
+-> { "execute": "query-cpu-max" }
+<- { "return": 255 }
+
+EQMP
+
+ {
.name = "memsave",
.args_type = "val:l,size:i,filename:s,cpu:i?",
.mhandler.cmd_new = qmp_marshal_input_memsave,
@@ -644,7 +666,7 @@
SQMP
migrate-set-cache-size
----------------------
+----------------------
Set cache size to be used by XBZRLE migration, the cache size will be rounded
down to the nearest power of 2
@@ -667,7 +689,7 @@
SQMP
query-migrate-cache-size
----------------------
+------------------------
Show cache size to be used by XBZRLE migration
@@ -2431,32 +2453,43 @@
- Possible values: "active", "completed", "failed", "cancelled"
- "total-time": total amount of ms since migration started. If
migration has ended, it returns the total migration
- time (json-int)
+ time (json-int)
- "downtime": only present when migration has finished correctly
total amount in ms for downtime that happened (json-int)
- "expected-downtime": only present while migration is active
total amount in ms for downtime that was calculated on
- the last bitmap round (json-int)
+ the last bitmap round (json-int)
- "ram": only present if "status" is "active", it is a json-object with the
- following RAM information (in bytes):
- - "transferred": amount transferred (json-int)
- - "remaining": amount remaining (json-int)
- - "total": total (json-int)
- - "duplicate": number of duplicated pages (json-int)
- - "normal" : number of normal pages transferred (json-int)
- - "normal-bytes" : number of normal bytes transferred (json-int)
+ following RAM information:
+ - "transferred": amount transferred in bytes (json-int)
+ - "remaining": amount remaining to transfer in bytes (json-int)
+ - "total": total amount of memory in bytes (json-int)
+ - "duplicate": number of pages filled entirely with the same
+ byte (json-int)
+ These are sent over the wire much more efficiently.
+ - "skipped": number of skipped zero pages (json-int)
+ - "normal" : number of whole pages transfered. I.e. they
+ were not sent as duplicate or xbzrle pages (json-int)
+ - "normal-bytes" : number of bytes transferred in whole
+ pages. This is just normal pages times size of one page,
+ but this way upper levels don't need to care about page
+ size (json-int)
- "disk": only present if "status" is "active" and it is a block migration,
- it is a json-object with the following disk information (in bytes):
- - "transferred": amount transferred (json-int)
- - "remaining": amount remaining (json-int)
- - "total": total (json-int)
+ it is a json-object with the following disk information:
+ - "transferred": amount transferred in bytes (json-int)
+ - "remaining": amount remaining to transfer in bytes json-int)
+ - "total": total disk size in bytes (json-int)
- "xbzrle-cache": only present if XBZRLE is active.
It is a json-object with the following XBZRLE information:
- - "cache-size": XBZRLE cache size
- - "bytes": total XBZRLE bytes transferred
+ - "cache-size": XBZRLE cache size in bytes
+ - "bytes": number of bytes transferred for XBZRLE compressed pages
- "pages": number of XBZRLE compressed pages
- - "cache-miss": number of cache misses
- - "overflow": number of XBZRLE overflows
+ - "cache-miss": number of XBRZRLE page cache misses
+ - "overflow": number of times XBZRLE overflows. This means
+ that the XBZRLE encoding was bigger than just sent the
+ whole page, and then we sent the whole page instead (as as
+ normal page).
+
Examples:
1. Before the first migration
@@ -2567,11 +2600,11 @@
SQMP
migrate-set-capabilities
--------
+------------------------
Enable/Disable migration capabilities
-- "xbzrle": xbzrle support
+- "xbzrle": XBZRLE support
Arguments:
@@ -2590,7 +2623,7 @@
},
SQMP
query-migrate-capabilities
--------
+--------------------------
Query current migration capabilities
@@ -2721,18 +2754,76 @@
.mhandler.cmd_new = qmp_marshal_input_query_tpm,
},
+SQMP
+query-tpm
+---------
+
+Return information about the TPM device.
+
+Arguments: None
+
+Example:
+
+-> { "execute": "query-tpm" }
+<- { "return":
+ [
+ { "model": "tpm-tis",
+ "options":
+ { "type": "passthrough",
+ "data":
+ { "cancel-path": "/sys/class/misc/tpm0/device/cancel",
+ "path": "/dev/tpm0"
+ }
+ },
+ "id": "tpm0"
+ }
+ ]
+ }
+
+EQMP
+
{
.name = "query-tpm-models",
.args_type = "",
.mhandler.cmd_new = qmp_marshal_input_query_tpm_models,
},
+SQMP
+query-tpm-models
+----------------
+
+Return a list of supported TPM models.
+
+Arguments: None
+
+Example:
+
+-> { "execute": "query-tpm-models" }
+<- { "return": [ "tpm-tis" ] }
+
+EQMP
+
{
.name = "query-tpm-types",
.args_type = "",
.mhandler.cmd_new = qmp_marshal_input_query_tpm_types,
},
+SQMP
+query-tpm-types
+---------------
+
+Return a list of supported TPM types.
+
+Arguments: None
+
+Example:
+
+-> { "execute": "query-tpm-types" }
+<- { "return": [ "passthrough" ] }
+
+EQMP
+
{
.name = "chardev-add",
.args_type = "id:s,backend:q",
diff --git a/qom/object.c b/qom/object.c
index a0e3cbe..8818149 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -629,7 +629,18 @@
ObjectPropertyRelease *release,
void *opaque, Error **errp)
{
- ObjectProperty *prop = g_malloc0(sizeof(*prop));
+ ObjectProperty *prop;
+
+ QTAILQ_FOREACH(prop, &obj->properties, node) {
+ if (strcmp(prop->name, name) == 0) {
+ error_setg(errp, "attempt to add duplicate property '%s'"
+ " to object (type '%s')", name,
+ object_get_typename(obj));
+ return;
+ }
+ }
+
+ prop = g_malloc0(sizeof(*prop));
prop->name = g_strdup(name);
prop->type = g_strdup(type);
diff --git a/qtest.c b/qtest.c
index 5e0e9ec..b03b68a 100644
--- a/qtest.c
+++ b/qtest.c
@@ -191,7 +191,7 @@
len = vsnprintf(buffer, sizeof(buffer), fmt, ap);
va_end(ap);
- qemu_chr_fe_write(chr, (uint8_t *)buffer, len);
+ qemu_chr_fe_write_all(chr, (uint8_t *)buffer, len);
if (qtest_log_fp && qtest_opened) {
fprintf(qtest_log_fp, "%s", buffer);
}
diff --git a/roms/Makefile b/roms/Makefile
index 5e645bc..7a228ae 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -1,5 +1,30 @@
vgabios_variants := stdvga cirrus vmware qxl
+pxerom_variants := e1000 eepro100 ne2k_pci pcnet rtl8139 virtio
+
+pxe-rom-e1000 efi-rom-e1000 : VID := 8086
+pxe-rom-e1000 efi-rom-e1000 : DID := 100e
+pxe-rom-eepro100 efi-rom-eepro100 : VID := 8086
+pxe-rom-eepro100 efi-rom-eepro100 : DID := 1209
+pxe-rom-ne2k_pci efi-rom-ne2k_pci : VID := 1050
+pxe-rom-ne2k_pci efi-rom-ne2k_pci : DID := 0940
+pxe-rom-pcnet efi-rom-pcnet : VID := 1022
+pxe-rom-pcnet efi-rom-pcnet : DID := 2000
+pxe-rom-rtl8139 efi-rom-rtl8139 : VID := 10ec
+pxe-rom-rtl8139 efi-rom-rtl8139 : DID := 8139
+pxe-rom-virtio efi-rom-virtio : VID := 1af4
+pxe-rom-virtio efi-rom-virtio : DID := 1000
+
+#
+# EfiRom utility is shipped with edk2 / tianocore, in BaseTools/
+#
+# We need that to combine multiple images (legacy bios,
+# efi ia32, efi x64) into a single rom binary.
+#
+# We try to find it in the path. You can also pass the location on
+# the command line, i.e. "make EFIROM=/path/to/EfiRom efirom"
+#
+EFIROM ?= $(shell which EfiRom 2>/dev/null)
default:
@echo "nothing is build by default"
@@ -7,6 +32,9 @@
@echo " bios -- update bios.bin (seabios)"
@echo " seavgabios -- update vgabios binaries (seabios)"
@echo " lgplvgabios -- update vgabios binaries (lgpl)"
+ @echo " pxerom -- update nic roms (bios only)"
+ @echo " efirom -- update nic roms (bios+efi, this needs"
+ @echo " the EfiRom utility from edk2 / tianocore)"
bios: config.seabios
sh configure-seabios.sh $<
@@ -26,3 +54,24 @@
lgplvgabios-%:
make -C vgabios vgabios-$*.bin
cp vgabios/VGABIOS-lgpl-latest.$*.bin ../pc-bios/vgabios-$*.bin
+
+pxerom: $(patsubst %,pxe-rom-%,$(pxerom_variants))
+
+pxe-rom-%: ipxe/src/config/local/general.h
+ make -C ipxe/src bin/$(VID)$(DID).rom
+ cp ipxe/src/bin/$(VID)$(DID).rom ../pc-bios/pxe-$*.rom
+
+efirom: $(patsubst %,efi-rom-%,$(pxerom_variants))
+
+efi-rom-%: ipxe/src/config/local/general.h
+ make -C ipxe/src bin/$(VID)$(DID).rom
+ make -C ipxe/src bin-i386-efi/$(VID)$(DID).efidrv
+ make -C ipxe/src bin-x86_64-efi/$(VID)$(DID).efidrv
+ $(EFIROM) -f "0x$(VID)" -i "0x$(DID)" -l 0x02 \
+ -b ipxe/src/bin/$(VID)$(DID).rom \
+ -ec ipxe/src/bin-i386-efi/$(VID)$(DID).efidrv \
+ -ec ipxe/src/bin-x86_64-efi/$(VID)$(DID).efidrv \
+ -o ../pc-bios/efi-$*.rom
+
+ipxe/src/config/local/%: config.ipxe.%
+ cp $< $@
diff --git a/roms/config.ipxe.general.h b/roms/config.ipxe.general.h
new file mode 100644
index 0000000..b3fce53
--- /dev/null
+++ b/roms/config.ipxe.general.h
@@ -0,0 +1,2 @@
+#undef BANNER_TIMEOUT
+#define BANNER_TIMEOUT 0
diff --git a/roms/ipxe b/roms/ipxe
index 7aee315..09c5109 160000
--- a/roms/ipxe
+++ b/roms/ipxe
@@ -1 +1 @@
-Subproject commit 7aee315f61aaf1be6d2fff26339f28a1137231a5
+Subproject commit 09c5109b8585178172c7608de8d52e9d9af0b680
diff --git a/savevm.c b/savevm.c
index 35c8d1e..406caa9 100644
--- a/savevm.c
+++ b/savevm.c
@@ -39,6 +39,7 @@
#include "qmp-commands.h"
#include "trace.h"
#include "qemu/bitops.h"
+#include "qemu/iov.h"
#define SELF_ANNOUNCE_ROUNDS 5
@@ -113,6 +114,7 @@
/* savevm/loadvm support */
#define IO_BUF_SIZE 32768
+#define MAX_IOV_SIZE MIN(IOV_MAX, 64)
struct QEMUFile {
const QEMUFileOps *ops;
@@ -128,6 +130,9 @@
int buf_size; /* 0 when writing */
uint8_t buf[IO_BUF_SIZE];
+ struct iovec iov[MAX_IOV_SIZE];
+ unsigned int iovcnt;
+
int last_error;
};
@@ -171,6 +176,19 @@
qemu_coroutine_yield();
}
+static ssize_t socket_writev_buffer(void *opaque, struct iovec *iov, int iovcnt)
+{
+ QEMUFileSocket *s = opaque;
+ ssize_t len;
+ ssize_t size = iov_size(iov, iovcnt);
+
+ len = iov_send(s->fd, iov, iovcnt, 0, size);
+ if (len < size) {
+ len = -socket_error();
+ }
+ return len;
+}
+
static int socket_get_fd(void *opaque)
{
QEMUFileSocket *s = opaque;
@@ -275,7 +293,7 @@
QEMUFileStdio *s = opaque;
int ret = 0;
- if (s->file->ops->put_buffer) {
+ if (s->file->ops->put_buffer || s->file->ops->writev_buffer) {
int fd = fileno(s->stdio_file);
struct stat st;
@@ -387,6 +405,7 @@
static const QEMUFileOps socket_write_ops = {
.get_fd = socket_get_fd,
.put_buffer = socket_put_buffer,
+ .writev_buffer = socket_writev_buffer,
.close = socket_close
};
@@ -497,22 +516,38 @@
}
}
-/** Flushes QEMUFile buffer
+/**
+ * Flushes QEMUFile buffer
*
+ * If there is writev_buffer QEMUFileOps it uses it otherwise uses
+ * put_buffer ops.
*/
static void qemu_fflush(QEMUFile *f)
{
- int ret = 0;
+ ssize_t ret = 0;
+ int i = 0;
- if (!f->ops->put_buffer) {
+ if (!f->ops->writev_buffer && !f->ops->put_buffer) {
return;
}
- if (f->is_write && f->buf_index > 0) {
- ret = f->ops->put_buffer(f->opaque, f->buf, f->pos, f->buf_index);
- if (ret >= 0) {
- f->pos += f->buf_index;
+
+ if (f->is_write && f->iovcnt > 0) {
+ if (f->ops->writev_buffer) {
+ ret = f->ops->writev_buffer(f->opaque, f->iov, f->iovcnt);
+ if (ret >= 0) {
+ f->pos += ret;
+ }
+ } else {
+ for (i = 0; i < f->iovcnt && ret >= 0; i++) {
+ ret = f->ops->put_buffer(f->opaque, f->iov[i].iov_base, f->pos,
+ f->iov[i].iov_len);
+ if (ret >= 0) {
+ f->pos += ret;
+ }
+ }
}
f->buf_index = 0;
+ f->iovcnt = 0;
}
if (ret < 0) {
qemu_file_set_error(f, ret);
@@ -586,6 +621,40 @@
return ret;
}
+static void add_to_iovec(QEMUFile *f, const uint8_t *buf, int size)
+{
+ /* check for adjacent buffer and coalesce them */
+ if (f->iovcnt > 0 && buf == f->iov[f->iovcnt - 1].iov_base +
+ f->iov[f->iovcnt - 1].iov_len) {
+ f->iov[f->iovcnt - 1].iov_len += size;
+ } else {
+ f->iov[f->iovcnt].iov_base = (uint8_t *)buf;
+ f->iov[f->iovcnt++].iov_len = size;
+ }
+}
+
+void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, int size)
+{
+ if (f->last_error) {
+ return;
+ }
+
+ if (f->is_write == 0 && f->buf_index > 0) {
+ fprintf(stderr,
+ "Attempted to write to buffer while read buffer is not empty\n");
+ abort();
+ }
+
+ add_to_iovec(f, buf, size);
+
+ f->is_write = 1;
+ f->bytes_xfer += size;
+
+ if (f->buf_index >= IO_BUF_SIZE || f->iovcnt >= MAX_IOV_SIZE) {
+ qemu_fflush(f);
+ }
+}
+
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size)
{
int l;
@@ -607,15 +676,12 @@
memcpy(f->buf + f->buf_index, buf, l);
f->is_write = 1;
f->buf_index += l;
- f->bytes_xfer += l;
+ qemu_put_buffer_async(f, f->buf + (f->buf_index - l), l);
+ if (qemu_file_get_error(f)) {
+ break;
+ }
buf += l;
size -= l;
- if (f->buf_index >= IO_BUF_SIZE) {
- qemu_fflush(f);
- if (qemu_file_get_error(f)) {
- break;
- }
- }
}
}
@@ -633,7 +699,11 @@
f->buf[f->buf_index++] = v;
f->is_write = 1;
- if (f->buf_index >= IO_BUF_SIZE) {
+ f->bytes_xfer++;
+
+ add_to_iovec(f, f->buf + (f->buf_index - 1), 1);
+
+ if (f->buf_index >= IO_BUF_SIZE || f->iovcnt >= MAX_IOV_SIZE) {
qemu_fflush(f);
}
}
@@ -1072,6 +1142,27 @@
.put = put_uint64,
};
+/* 64 bit unsigned int. See that the received value is the same than the one
+ in the field */
+
+static int get_uint64_equal(QEMUFile *f, void *pv, size_t size)
+{
+ uint64_t *v = pv;
+ uint64_t v2;
+ qemu_get_be64s(f, &v2);
+
+ if (*v == v2) {
+ return 0;
+ }
+ return -EINVAL;
+}
+
+const VMStateInfo vmstate_info_uint64_equal = {
+ .name = "int64 equal",
+ .get = get_uint64_equal,
+ .put = put_uint64,
+};
+
/* 8 bit int. See that the received value is the same than the one
in the field */
@@ -1112,6 +1203,29 @@
.put = put_uint16,
};
+/* floating point */
+
+static int get_float64(QEMUFile *f, void *pv, size_t size)
+{
+ float64 *v = pv;
+
+ *v = make_float64(qemu_get_be64(f));
+ return 0;
+}
+
+static void put_float64(QEMUFile *f, void *pv, size_t size)
+{
+ uint64_t *v = pv;
+
+ qemu_put_be64(f, float64_val(*v));
+}
+
+const VMStateInfo vmstate_info_float64 = {
+ .name = "float64",
+ .get = get_float64,
+ .put = put_float64,
+};
+
/* timers */
static int get_timer(QEMUFile *f, void *pv, size_t size)
diff --git a/slirp/misc.c b/slirp/misc.c
index d4df972..6b9c2c4 100644
--- a/slirp/misc.c
+++ b/slirp/misc.c
@@ -212,9 +212,9 @@
} while (so->s < 0 && errno == EINTR);
closesocket(s);
opt = 1;
- setsockopt(so->s, SOL_SOCKET, SO_REUSEADDR, (char *)&opt, sizeof(int));
+ qemu_setsockopt(so->s, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(int));
opt = 1;
- setsockopt(so->s, SOL_SOCKET, SO_OOBINLINE, (char *)&opt, sizeof(int));
+ qemu_setsockopt(so->s, SOL_SOCKET, SO_OOBINLINE, &opt, sizeof(int));
socket_set_nonblock(so->s);
/* Append the telnet options now */
diff --git a/slirp/socket.c b/slirp/socket.c
index bb639ae..8e8819c 100644
--- a/slirp/socket.c
+++ b/slirp/socket.c
@@ -627,7 +627,7 @@
addr.sin_port = hport;
if (((s = qemu_socket(AF_INET,SOCK_STREAM,0)) < 0) ||
- (setsockopt(s,SOL_SOCKET,SO_REUSEADDR,(char *)&opt,sizeof(int)) < 0) ||
+ (qemu_setsockopt(s, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(int)) < 0) ||
(bind(s,(struct sockaddr *)&addr, sizeof(addr)) < 0) ||
(listen(s,1) < 0)) {
int tmperrno = errno; /* Don't clobber the real reason we failed */
@@ -642,7 +642,7 @@
#endif
return NULL;
}
- setsockopt(s,SOL_SOCKET,SO_OOBINLINE,(char *)&opt,sizeof(int));
+ qemu_setsockopt(s, SOL_SOCKET, SO_OOBINLINE, &opt, sizeof(int));
getsockname(s,(struct sockaddr *)&addr,&addrlen);
so->so_fport = addr.sin_port;
diff --git a/slirp/tcp_subr.c b/slirp/tcp_subr.c
index 7b7ad60..84a6bb5 100644
--- a/slirp/tcp_subr.c
+++ b/slirp/tcp_subr.c
@@ -338,9 +338,9 @@
socket_set_nonblock(s);
opt = 1;
- setsockopt(s,SOL_SOCKET,SO_REUSEADDR,(char *)&opt,sizeof(opt ));
+ qemu_setsockopt(s, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt));
opt = 1;
- setsockopt(s,SOL_SOCKET,SO_OOBINLINE,(char *)&opt,sizeof(opt ));
+ qemu_setsockopt(s, SOL_SOCKET, SO_OOBINLINE, &opt, sizeof(opt));
addr.sin_family = AF_INET;
if ((so->so_faddr.s_addr & slirp->vnetwork_mask.s_addr) ==
@@ -427,9 +427,9 @@
}
socket_set_nonblock(s);
opt = 1;
- setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (char *)&opt, sizeof(int));
+ qemu_setsockopt(s, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(int));
opt = 1;
- setsockopt(s, SOL_SOCKET, SO_OOBINLINE, (char *)&opt, sizeof(int));
+ qemu_setsockopt(s, SOL_SOCKET, SO_OOBINLINE, &opt, sizeof(int));
socket_set_nodelay(s);
so->so_fport = addr.sin_port;
diff --git a/slirp/udp.c b/slirp/udp.c
index 9286cb7..b105f87 100644
--- a/slirp/udp.c
+++ b/slirp/udp.c
@@ -372,7 +372,7 @@
udp_detach(so);
return NULL;
}
- setsockopt(so->s,SOL_SOCKET,SO_REUSEADDR,(char *)&opt,sizeof(int));
+ qemu_setsockopt(so->s, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(int));
getsockname(so->s,(struct sockaddr *)&addr,&addrlen);
so->so_fport = addr.sin_port;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 9449a0c..282494f 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -189,7 +189,7 @@
cpu_synchronize_state(env);
- eflags = env->eflags;
+ eflags = cpu_compute_eflags(env);
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
cpu_fprintf(f,
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 705147a..7239696 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4200,7 +4200,7 @@
carry_in = carry_out;
break;
default:
- end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADCOX);
+ end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADOX);
break;
}
/* If we can't reuse carry-out, get it out of EFLAGS. */
@@ -4746,7 +4746,7 @@
}
s->pc++;
- /* 4.1.1-4.1.3: No preceeding lock, 66, f2, f3, or rex prefixes. */
+ /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ
| PREFIX_LOCK | PREFIX_DATA)) {
goto illegal_op;
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index bbb7fbf..23c05dd 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -36,10 +36,10 @@
lcc->parent_reset(s);
- tlb_flush(env, 1);
-
/* reset cpu state */
memset(env, 0, offsetof(CPULM32State, breakpoints));
+
+ tlb_flush(env, 1);
}
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index fd50b53..bfb9150 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -229,18 +229,8 @@
{
}
-static inline int cpu_interrupts_enabled(CPULM32State *env)
-{
- return env->ie & IE_IE;
-}
-
#include "exec/cpu-all.h"
-static inline target_ulong cpu_get_pc(CPULM32State *env)
-{
- return env->pc;
-}
-
static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index a0a8399..03fa5fb 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -39,7 +39,12 @@
hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
{
- return addr & TARGET_PAGE_MASK;
+ addr &= TARGET_PAGE_MASK;
+ if (env->flags & LM32_FLAG_IGNORE_MSB) {
+ return addr & 0x7fffffff;
+ } else {
+ return addr;
+ }
}
void lm32_cpu_do_interrupt(CPUState *cs)
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index ebc94a0..7ff991e 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -17,13 +17,13 @@
#define SHIFT 3
#include "exec/softmmu_template.h"
-void helper_raise_exception(CPULM32State *env, uint32_t index)
+void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
{
env->exception_index = index;
cpu_loop_exit(env);
}
-void helper_hlt(CPULM32State *env)
+void HELPER(hlt)(CPULM32State *env)
{
CPUState *cs = CPU(lm32_env_get_cpu(env));
@@ -32,42 +32,42 @@
cpu_loop_exit(env);
}
-void helper_wcsr_im(CPULM32State *env, uint32_t im)
+void HELPER(wcsr_im)(CPULM32State *env, uint32_t im)
{
lm32_pic_set_im(env->pic_state, im);
}
-void helper_wcsr_ip(CPULM32State *env, uint32_t im)
+void HELPER(wcsr_ip)(CPULM32State *env, uint32_t im)
{
lm32_pic_set_ip(env->pic_state, im);
}
-void helper_wcsr_jtx(CPULM32State *env, uint32_t jtx)
+void HELPER(wcsr_jtx)(CPULM32State *env, uint32_t jtx)
{
lm32_juart_set_jtx(env->juart_state, jtx);
}
-void helper_wcsr_jrx(CPULM32State *env, uint32_t jrx)
+void HELPER(wcsr_jrx)(CPULM32State *env, uint32_t jrx)
{
lm32_juart_set_jrx(env->juart_state, jrx);
}
-uint32_t helper_rcsr_im(CPULM32State *env)
+uint32_t HELPER(rcsr_im)(CPULM32State *env)
{
return lm32_pic_get_im(env->pic_state);
}
-uint32_t helper_rcsr_ip(CPULM32State *env)
+uint32_t HELPER(rcsr_ip)(CPULM32State *env)
{
return lm32_pic_get_ip(env->pic_state);
}
-uint32_t helper_rcsr_jtx(CPULM32State *env)
+uint32_t HELPER(rcsr_jtx)(CPULM32State *env)
{
return lm32_juart_get_jtx(env->juart_state);
}
-uint32_t helper_rcsr_jrx(CPULM32State *env)
+uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
{
return lm32_juart_get_jrx(env->juart_state);
}
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 695d9c5..e885bb3 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -324,10 +324,20 @@
int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
+ int i;
if (dc->format == OP_FMT_RI) {
- tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY],
- sign_extend(dc->imm16, 16));
+ switch (cond) {
+ case TCG_COND_GEU:
+ case TCG_COND_GTU:
+ i = zero_extend(dc->imm16, 16);
+ break;
+ default:
+ i = sign_extend(dc->imm16, 16);
+ break;
+ }
+
+ tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i);
} else {
tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
}
@@ -373,7 +383,7 @@
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
- sign_extend(dc->imm16, 16));
+ zero_extend(dc->imm16, 16));
} else {
LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
@@ -385,7 +395,7 @@
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
- sign_extend(dc->imm16, 16));
+ zero_extend(dc->imm16, 16));
} else {
LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
@@ -1027,11 +1037,6 @@
cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
}
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
- qemu_log("-----------------------------------------\n");
- log_cpu_state(env, 0);
- }
-
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
lj = -1;
num_insns = 0;
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 1c62f3c..f2cb88b 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -500,7 +500,7 @@
{
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
addr, is_write, is_exec);
- if (!(env->sregs[SR_MSR] & MSR_EE)) {
+ if (!env || !(env->sregs[SR_MSR] & MSR_EE)) {
return;
}
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 472be35..c7df595 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -517,13 +517,8 @@
acc = ((int64_t)env->active_tc.HI[ac] << 32) |
((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
- if (shift == 0) {
- p[0] = acc << 1;
- p[1] = (acc >> 63) & 0x01;
- } else {
- p[0] = acc >> (shift - 1);
- p[1] = 0;
- }
+ p[0] = (shift == 0) ? (acc << 1) : (acc >> (shift - 1));
+ p[1] = (acc >> 63) & 0x01;
}
/* 128 bits long. p[0] is LO, p[1] is HI */
@@ -3161,8 +3156,8 @@
tempDL[1] += 1;
}
- if ((!(tempDL[1] == 0 && (tempDL[0] & MIPSDSP_LHI) == 0x00)) &&
- (!(tempDL[1] == 1 && (tempDL[0] & MIPSDSP_LHI) == MIPSDSP_LHI))) {
+ if (((tempDL[1] & 0x01) != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
+ ((tempDL[1] & 0x01) != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
set_DSPControl_overflow_flag(1, 23, env);
}
@@ -3187,8 +3182,8 @@
tempDL[1] += 1;
}
- if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
- (tempDL[1] != 1 && (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
+ if (((tempDL[1] & 0x01) != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
+ ((tempDL[1] & 0x01) != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
set_DSPControl_overflow_flag(1, 23, env);
}
@@ -3214,9 +3209,9 @@
}
tempI = tempDL[0] >> 1;
- if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
- (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
- temp64 = tempDL[1];
+ if (((tempDL[1] & 0x01) != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
+ ((tempDL[1] & 0x01) != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
+ temp64 = tempDL[1] & 0x01;
if (temp64 == 0) {
tempI = 0x7FFFFFFF;
} else {
diff --git a/target-moxie/Makefile.objs b/target-moxie/Makefile.objs
new file mode 100644
index 0000000..6381d4d
--- /dev/null
+++ b/target-moxie/Makefile.objs
@@ -0,0 +1,2 @@
+obj-y += translate.o helper.o machine.o cpu.o machine.o
+obj-$(CONFIG_SOFTMMU) += mmu.o
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
new file mode 100644
index 0000000..c17d3f0
--- /dev/null
+++ b/target-moxie/cpu.c
@@ -0,0 +1,172 @@
+/*
+ * QEMU Moxie CPU
+ *
+ * Copyright (c) 2013 Anthony Green
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+#include "migration/vmstate.h"
+#include "machine.h"
+
+static void moxie_cpu_reset(CPUState *s)
+{
+ MoxieCPU *cpu = MOXIE_CPU(s);
+ MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu);
+ CPUMoxieState *env = &cpu->env;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ mcc->parent_reset(s);
+
+ memset(env, 0, offsetof(CPUMoxieState, breakpoints));
+ env->pc = 0x1000;
+
+ tlb_flush(env, 1);
+}
+
+static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ MoxieCPU *cpu = MOXIE_CPU(dev);
+ MoxieCPUClass *occ = MOXIE_CPU_GET_CLASS(dev);
+
+ qemu_init_vcpu(&cpu->env);
+ cpu_reset(CPU(cpu));
+
+ occ->parent_realize(dev, errp);
+}
+
+static void moxie_cpu_initfn(Object *obj)
+{
+ CPUState *cs = CPU(obj);
+ MoxieCPU *cpu = MOXIE_CPU(obj);
+ static int inited;
+
+ cs->env_ptr = &cpu->env;
+ cpu_exec_init(&cpu->env);
+
+ if (tcg_enabled() && !inited) {
+ inited = 1;
+ moxie_translate_init();
+ }
+}
+
+static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc;
+
+ if (cpu_model == NULL) {
+ return NULL;
+ }
+
+ oc = object_class_by_name(cpu_model);
+ if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_MOXIE_CPU) ||
+ object_class_is_abstract(oc))) {
+ return NULL;
+ }
+ return oc;
+}
+
+static void moxie_cpu_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+ MoxieCPUClass *mcc = MOXIE_CPU_CLASS(oc);
+
+ mcc->parent_realize = dc->realize;
+ dc->realize = moxie_cpu_realizefn;
+
+ mcc->parent_reset = cc->reset;
+ cc->reset = moxie_cpu_reset;
+
+ cc->class_by_name = moxie_cpu_class_by_name;
+
+ dc->vmsd = &vmstate_moxie_cpu;
+}
+
+static void moxielite_initfn(Object *obj)
+{
+ /* Set cpu feature flags */
+}
+
+static void moxie_any_initfn(Object *obj)
+{
+ /* Set cpu feature flags */
+}
+
+typedef struct MoxieCPUInfo {
+ const char *name;
+ void (*initfn)(Object *obj);
+} MoxieCPUInfo;
+
+static const MoxieCPUInfo moxie_cpus[] = {
+ { .name = "MoxieLite", .initfn = moxielite_initfn },
+ { .name = "any", .initfn = moxie_any_initfn },
+};
+
+MoxieCPU *cpu_moxie_init(const char *cpu_model)
+{
+ MoxieCPU *cpu;
+ ObjectClass *oc;
+
+ oc = moxie_cpu_class_by_name(cpu_model);
+ if (oc == NULL) {
+ return NULL;
+ }
+ cpu = MOXIE_CPU(object_new(object_class_get_name(oc)));
+ cpu->env.cpu_model_str = cpu_model;
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
+ return cpu;
+}
+
+static void cpu_register(const MoxieCPUInfo *info)
+{
+ TypeInfo type_info = {
+ .parent = TYPE_MOXIE_CPU,
+ .instance_size = sizeof(MoxieCPU),
+ .instance_init = info->initfn,
+ .class_size = sizeof(MoxieCPUClass),
+ };
+
+ type_info.name = g_strdup_printf("%s-" TYPE_MOXIE_CPU, info->name);
+ type_register(&type_info);
+ g_free((void *)type_info.name);
+}
+
+static const TypeInfo moxie_cpu_type_info = {
+ .name = TYPE_MOXIE_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(MoxieCPU),
+ .instance_init = moxie_cpu_initfn,
+ .class_size = sizeof(MoxieCPUClass),
+ .class_init = moxie_cpu_class_init,
+};
+
+static void moxie_cpu_register_types(void)
+{
+ int i;
+ type_register_static(&moxie_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(moxie_cpus); i++) {
+ cpu_register(&moxie_cpus[i]);
+ }
+}
+
+type_init(moxie_cpu_register_types)
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
new file mode 100644
index 0000000..b96236f
--- /dev/null
+++ b/target-moxie/cpu.h
@@ -0,0 +1,167 @@
+/*
+ * Moxie emulation
+ *
+ * Copyright (c) 2008, 2010, 2013 Anthony Green
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _CPU_MOXIE_H
+#define _CPU_MOXIE_H
+
+#include "config.h"
+#include "qemu-common.h"
+
+#define TARGET_LONG_BITS 32
+
+#define CPUArchState struct CPUMoxieState
+
+#define TARGET_HAS_ICE 1
+
+#define CPU_SAVE_VERSION 1
+
+#define ELF_MACHINE 0xFEED /* EM_MOXIE */
+
+#define MOXIE_EX_DIV0 0
+#define MOXIE_EX_BAD 1
+#define MOXIE_EX_IRQ 2
+#define MOXIE_EX_SWI 3
+#define MOXIE_EX_MMU_MISS 4
+#define MOXIE_EX_BREAK 16
+
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat.h"
+
+#define TARGET_PAGE_BITS 12 /* 4k */
+
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+
+#define NB_MMU_MODES 1
+
+typedef struct CPUMoxieState {
+
+ uint32_t flags; /* general execution flags */
+ uint32_t gregs[16]; /* general registers */
+ uint32_t sregs[256]; /* special registers */
+ uint32_t pc; /* program counter */
+ /* Instead of saving the cc value, we save the cmp arguments
+ and compute cc on demand. */
+ uint32_t cc_a; /* reg a for condition code calculation */
+ uint32_t cc_b; /* reg b for condition code calculation */
+
+ void *irq[8];
+
+ CPU_COMMON
+
+} CPUMoxieState;
+
+#include "qom/cpu.h"
+
+#define TYPE_MOXIE_CPU "moxie-cpu"
+
+#define MOXIE_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(MoxieCPUClass, (klass), TYPE_MOXIE_CPU)
+#define MOXIE_CPU(obj) \
+ OBJECT_CHECK(MoxieCPU, (obj), TYPE_MOXIE_CPU)
+#define MOXIE_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(MoxieCPUClass, (obj), TYPE_MOXIE_CPU)
+
+/**
+ * MoxieCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A Moxie CPU model.
+ */
+typedef struct MoxieCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+ void (*parent_reset)(CPUState *cpu);
+} MoxieCPUClass;
+
+/**
+ * MoxieCPU:
+ * @env: #CPUMoxieState
+ *
+ * A Moxie CPU.
+ */
+typedef struct MoxieCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUMoxieState env;
+} MoxieCPU;
+
+static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
+{
+ return MOXIE_CPU(container_of(env, MoxieCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e))
+
+#define ENV_OFFSET offsetof(MoxieCPU, env)
+
+MoxieCPU *cpu_moxie_init(const char *cpu_model);
+int cpu_moxie_exec(CPUMoxieState *s);
+void do_interrupt(CPUMoxieState *env);
+void moxie_translate_init(void);
+int cpu_moxie_signal_handler(int host_signum, void *pinfo,
+ void *puc);
+
+static inline CPUMoxieState *cpu_init(const char *cpu_model)
+{
+ MoxieCPU *cpu = cpu_moxie_init(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ return &cpu->env;
+}
+
+#define cpu_exec cpu_moxie_exec
+#define cpu_gen_code cpu_moxie_gen_code
+#define cpu_signal_handler cpu_moxie_signal_handler
+
+static inline int cpu_mmu_index(CPUMoxieState *env)
+{
+ return 0;
+}
+
+#include "exec/cpu-all.h"
+#include "exec/exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUMoxieState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
+
+static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+}
+
+static inline int cpu_has_work(CPUState *cpu)
+{
+ return cpu->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
+ int rw, int mmu_idx);
+
+#endif /* _CPU_MOXIE_H */
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
new file mode 100644
index 0000000..8604ce8
--- /dev/null
+++ b/target-moxie/helper.c
@@ -0,0 +1,171 @@
+/*
+ * Moxie helper routines.
+ *
+ * Copyright (c) 2008, 2009, 2010, 2013 Anthony Green
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+
+#include "config.h"
+#include "cpu.h"
+#include "mmu.h"
+#include "exec/exec-all.h"
+#include "qemu/host-utils.h"
+#include "helper.h"
+
+#define MMUSUFFIX _mmu
+
+#define SHIFT 0
+#include "exec/softmmu_template.h"
+
+#define SHIFT 1
+#include "exec/softmmu_template.h"
+
+#define SHIFT 2
+#include "exec/softmmu_template.h"
+
+#define SHIFT 3
+#include "exec/softmmu_template.h"
+
+/* Try to fill the TLB and return an exception if error. If retaddr is
+ NULL, it means that the function was called in C code (i.e. not
+ from generated code or from helper.c) */
+void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
+ uintptr_t retaddr)
+{
+ int ret;
+
+ ret = cpu_moxie_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ if (unlikely(ret)) {
+ if (retaddr) {
+ cpu_restore_state(env, retaddr);
+ }
+ }
+ cpu_loop_exit(env);
+}
+
+void helper_raise_exception(CPUMoxieState *env, int ex)
+{
+ env->exception_index = ex;
+ /* Stash the exception type. */
+ env->sregs[2] = ex;
+ /* Stash the address where the exception occurred. */
+ cpu_restore_state(env, GETPC());
+ env->sregs[5] = env->pc;
+ /* Jump the the exception handline routine. */
+ env->pc = env->sregs[1];
+ cpu_loop_exit(env);
+}
+
+uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b)
+{
+ if (unlikely(b == 0)) {
+ helper_raise_exception(env, MOXIE_EX_DIV0);
+ return 0;
+ }
+ if (unlikely(a == INT_MIN && b == -1)) {
+ return INT_MIN;
+ }
+
+ return (int32_t)a / (int32_t)b;
+}
+
+uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
+{
+ if (unlikely(b == 0)) {
+ helper_raise_exception(env, MOXIE_EX_DIV0);
+ return 0;
+ }
+ return a / b;
+}
+
+void helper_debug(CPUMoxieState *env)
+{
+ env->exception_index = EXCP_DEBUG;
+ cpu_loop_exit(env);
+}
+
+#if defined(CONFIG_USER_ONLY)
+
+void do_interrupt(CPUState *env)
+{
+ env->exception_index = -1;
+}
+
+int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
+ int rw, int mmu_idx)
+{
+ env->exception_index = 0xaa;
+ env->debug1 = address;
+ cpu_dump_state(env, stderr, fprintf, 0);
+ return 1;
+}
+
+target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+{
+ return addr;
+}
+
+#else /* !CONFIG_USER_ONLY */
+
+int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
+ int rw, int mmu_idx)
+{
+ MoxieMMUResult res;
+ int prot, miss;
+ target_ulong phy;
+ int r = 1;
+
+ address &= TARGET_PAGE_MASK;
+ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx);
+ if (miss) {
+ /* handle the miss. */
+ phy = 0;
+ env->exception_index = MOXIE_EX_MMU_MISS;
+ } else {
+ phy = res.phy;
+ r = 0;
+ }
+ tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
+ return r;
+}
+
+
+void do_interrupt(CPUMoxieState *env)
+{
+ switch (env->exception_index) {
+ case MOXIE_EX_BREAK:
+ break;
+ default:
+ break;
+ }
+}
+
+hwaddr cpu_get_phys_page_debug(CPUMoxieState *env, target_ulong addr)
+{
+ uint32_t phy = addr;
+ MoxieMMUResult res;
+ int miss;
+ miss = moxie_mmu_translate(&res, env, addr, 0, 0);
+ if (!miss) {
+ phy = res.phy;
+ }
+ return phy;
+}
+#endif
diff --git a/target-moxie/helper.h b/target-moxie/helper.h
new file mode 100644
index 0000000..3aa5549
--- /dev/null
+++ b/target-moxie/helper.h
@@ -0,0 +1,9 @@
+#include "exec/def-helper.h"
+
+DEF_HELPER_2(raise_exception, void, env, int)
+DEF_HELPER_1(debug, void, env)
+
+DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_WG, i32, env, i32, i32)
+
+#include "exec/def-helper.h"
diff --git a/target-moxie/machine.c b/target-moxie/machine.c
new file mode 100644
index 0000000..5bfdb28
--- /dev/null
+++ b/target-moxie/machine.c
@@ -0,0 +1,28 @@
+#include "hw/hw.h"
+#include "hw/boards.h"
+
+const VMStateDescription vmstate_moxie_cpu = {
+ .name = "cpu",
+ .version_id = CPU_SAVE_VERSION,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(flags, CPUMoxieState),
+ VMSTATE_UINT32_ARRAY(gregs, CPUMoxieState, 16),
+ VMSTATE_UINT32_ARRAY(sregs, CPUMoxieState, 256),
+ VMSTATE_UINT32(pc, CPUMoxieState),
+ VMSTATE_UINT32(cc_a, CPUMoxieState),
+ VMSTATE_UINT32(cc_b, CPUMoxieState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+void cpu_save(QEMUFile *f, void *opaque)
+{
+ vmstate_save_state(f, &vmstate_moxie_cpu, opaque);
+}
+
+int cpu_load(QEMUFile *f, void *opaque, int version_id)
+{
+ return vmstate_load_state(f, &vmstate_moxie_cpu, opaque, version_id);
+}
diff --git a/target-moxie/machine.h b/target-moxie/machine.h
new file mode 100644
index 0000000..a1b7290
--- /dev/null
+++ b/target-moxie/machine.h
@@ -0,0 +1 @@
+extern const VMStateDescription vmstate_moxie_cpu;
diff --git a/target-moxie/mmu.c b/target-moxie/mmu.c
new file mode 100644
index 0000000..5217eed
--- /dev/null
+++ b/target-moxie/mmu.c
@@ -0,0 +1,36 @@
+/*
+ * Moxie mmu emulation.
+ *
+ * Copyright (c) 2008, 2013 Anthony Green
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "config.h"
+#include "cpu.h"
+#include "mmu.h"
+#include "exec/exec-all.h"
+
+int moxie_mmu_translate(MoxieMMUResult *res,
+ CPUMoxieState *env, uint32_t vaddr,
+ int rw, int mmu_idx)
+{
+ /* Perform no translation yet. */
+ res->phy = vaddr;
+ return 0;
+}
diff --git a/target-moxie/mmu.h b/target-moxie/mmu.h
new file mode 100644
index 0000000..e01ffc2
--- /dev/null
+++ b/target-moxie/mmu.h
@@ -0,0 +1,19 @@
+#define MOXIE_MMU_ERR_EXEC 0
+#define MOXIE_MMU_ERR_READ 1
+#define MOXIE_MMU_ERR_WRITE 2
+#define MOXIE_MMU_ERR_FLUSH 3
+
+typedef struct {
+ uint32_t phy;
+ uint32_t pfn;
+ int g:1;
+ int v:1;
+ int k:1;
+ int w:1;
+ int e:1;
+ int cause_op;
+} MoxieMMUResult;
+
+int moxie_mmu_translate(MoxieMMUResult *res,
+ CPUMoxieState *env, uint32_t vaddr,
+ int rw, int mmu_idx);
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
new file mode 100644
index 0000000..34f166e
--- /dev/null
+++ b/target-moxie/translate.c
@@ -0,0 +1,926 @@
+/*
+ * Moxie emulation for qemu: main translation routines.
+ *
+ * Copyright (c) 2009, 2013 Anthony Green
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* For information on the Moxie architecture, see
+ * http://moxielogic.org/wiki
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <assert.h>
+
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "disas/disas.h"
+#include "tcg-op.h"
+
+#include "helper.h"
+#define GEN_HELPER 1
+#include "helper.h"
+
+/* This is the state at translation time. */
+typedef struct DisasContext {
+ struct TranslationBlock *tb;
+ target_ulong pc, saved_pc;
+ uint32_t opcode;
+ uint32_t fp_status;
+ /* Routine used to access memory */
+ int memidx;
+ int bstate;
+ target_ulong btarget;
+ int singlestep_enabled;
+} DisasContext;
+
+enum {
+ BS_NONE = 0, /* We go out of the TB without reaching a branch or an
+ * exception condition */
+ BS_STOP = 1, /* We want to stop translation for any reason */
+ BS_BRANCH = 2, /* We reached a branch condition */
+ BS_EXCP = 3, /* We reached an exception condition */
+};
+
+static TCGv cpu_pc;
+static TCGv cpu_gregs[16];
+static TCGv_ptr cpu_env;
+static TCGv cc_a, cc_b;
+
+#include "exec/gen-icount.h"
+
+#define REG(x) (cpu_gregs[x])
+
+/* Extract the signed 10-bit offset from a 16-bit branch
+ instruction. */
+static int extract_branch_offset(int opcode)
+{
+ return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
+}
+
+void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
+{
+ int i;
+ cpu_fprintf(f, "pc=0x%08x\n", env->pc);
+ cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
+ env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
+ for (i = 4; i < 16; i += 4) {
+ cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
+ i-2, env->gregs[i], i-1, env->gregs[i + 1],
+ i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
+ }
+ for (i = 4; i < 16; i += 4) {
+ cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
+ i-2, env->sregs[i], i-1, env->sregs[i + 1],
+ i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
+ }
+}
+
+void moxie_translate_init(void)
+{
+ int i;
+ static int done_init;
+ static const char * const gregnames[16] = {
+ "$fp", "$sp", "$r0", "$r1",
+ "$r2", "$r3", "$r4", "$r5",
+ "$r6", "$r7", "$r8", "$r9",
+ "$r10", "$r11", "$r12", "$r13"
+ };
+
+ if (done_init) {
+ return;
+ }
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUMoxieState, pc), "$pc");
+ for (i = 0; i < 16; i++)
+ cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUMoxieState, gregs[i]),
+ gregnames[i]);
+
+ cc_a = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUMoxieState, cc_a), "cc_a");
+ cc_b = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUMoxieState, cc_b), "cc_b");
+
+ done_init = 1;
+}
+
+static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
+ int n, target_ulong dest)
+{
+ TranslationBlock *tb;
+ tb = ctx->tb;
+
+ if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
+ !ctx->singlestep_enabled) {
+ tcg_gen_goto_tb(n);
+ tcg_gen_movi_i32(cpu_pc, dest);
+ tcg_gen_exit_tb((long) tb + n);
+ } else {
+ tcg_gen_movi_i32(cpu_pc, dest);
+ if (ctx->singlestep_enabled) {
+ gen_helper_debug(cpu_env);
+ }
+ tcg_gen_exit_tb(0);
+ }
+}
+
+static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
+{
+ CPUMoxieState *env = &cpu->env;
+
+ /* Local cache for the instruction opcode. */
+ int opcode;
+ /* Set the default instruction length. */
+ int length = 2;
+
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
+ tcg_gen_debug_insn_start(ctx->pc);
+ }
+
+ /* Examine the 16-bit opcode. */
+ opcode = ctx->opcode;
+
+ /* Decode instruction. */
+ if (opcode & (1 << 15)) {
+ if (opcode & (1 << 14)) {
+ /* This is a Form 3 instruction. */
+ int inst = (opcode >> 10 & 0xf);
+
+#define BRANCH(cond) \
+ do { \
+ int l1 = gen_new_label(); \
+ tcg_gen_brcond_i32(cond, cc_a, cc_b, l1); \
+ gen_goto_tb(env, ctx, 1, ctx->pc+2); \
+ gen_set_label(l1); \
+ gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
+ ctx->bstate = BS_BRANCH; \
+ } while (0)
+
+ switch (inst) {
+ case 0x00: /* beq */
+ BRANCH(TCG_COND_EQ);
+ break;
+ case 0x01: /* bne */
+ BRANCH(TCG_COND_NE);
+ break;
+ case 0x02: /* blt */
+ BRANCH(TCG_COND_LT);
+ break;
+ case 0x03: /* bgt */
+ BRANCH(TCG_COND_GT);
+ break;
+ case 0x04: /* bltu */
+ BRANCH(TCG_COND_LTU);
+ break;
+ case 0x05: /* bgtu */
+ BRANCH(TCG_COND_GTU);
+ break;
+ case 0x06: /* bge */
+ BRANCH(TCG_COND_GE);
+ break;
+ case 0x07: /* ble */
+ BRANCH(TCG_COND_LE);
+ break;
+ case 0x08: /* bgeu */
+ BRANCH(TCG_COND_GEU);
+ break;
+ case 0x09: /* bleu */
+ BRANCH(TCG_COND_LEU);
+ break;
+ default:
+ {
+ TCGv temp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
+ gen_helper_raise_exception(cpu_env, temp);
+ tcg_temp_free_i32(temp);
+ }
+ break;
+ }
+ } else {
+ /* This is a Form 2 instruction. */
+ int inst = (opcode >> 12 & 0x3);
+ switch (inst) {
+ case 0x00: /* inc */
+ {
+ int a = (opcode >> 8) & 0xf;
+ unsigned int v = (opcode & 0xff);
+ tcg_gen_addi_i32(REG(a), REG(a), v);
+ }
+ break;
+ case 0x01: /* dec */
+ {
+ int a = (opcode >> 8) & 0xf;
+ unsigned int v = (opcode & 0xff);
+ tcg_gen_subi_i32(REG(a), REG(a), v);
+ }
+ break;
+ case 0x02: /* gsr */
+ {
+ int a = (opcode >> 8) & 0xf;
+ unsigned v = (opcode & 0xff);
+ tcg_gen_ld_i32(REG(a), cpu_env,
+ offsetof(CPUMoxieState, sregs[v]));
+ }
+ break;
+ case 0x03: /* ssr */
+ {
+ int a = (opcode >> 8) & 0xf;
+ unsigned v = (opcode & 0xff);
+ tcg_gen_st_i32(REG(a), cpu_env,
+ offsetof(CPUMoxieState, sregs[v]));
+ }
+ break;
+ default:
+ {
+ TCGv temp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
+ gen_helper_raise_exception(cpu_env, temp);
+ tcg_temp_free_i32(temp);
+ }
+ break;
+ }
+ }
+ } else {
+ /* This is a Form 1 instruction. */
+ int inst = opcode >> 8;
+ switch (inst) {
+ case 0x00: /* nop */
+ break;
+ case 0x01: /* ldi.l (immediate) */
+ {
+ int reg = (opcode >> 4) & 0xf;
+ int val = cpu_ldl_code(env, ctx->pc+2);
+ tcg_gen_movi_i32(REG(reg), val);
+ length = 6;
+ }
+ break;
+ case 0x02: /* mov (register-to-register) */
+ {
+ int dest = (opcode >> 4) & 0xf;
+ int src = opcode & 0xf;
+ tcg_gen_mov_i32(REG(dest), REG(src));
+ }
+ break;
+ case 0x03: /* jsra */
+ {
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+
+ tcg_gen_movi_i32(t1, ctx->pc + 6);
+
+ /* Make space for the static chain and return address. */
+ tcg_gen_subi_i32(t2, REG(1), 8);
+ tcg_gen_mov_i32(REG(1), t2);
+ tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
+
+ /* Push the current frame pointer. */
+ tcg_gen_subi_i32(t2, REG(1), 4);
+ tcg_gen_mov_i32(REG(1), t2);
+ tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
+
+ /* Set the pc and $fp. */
+ tcg_gen_mov_i32(REG(0), REG(1));
+
+ gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ ctx->bstate = BS_BRANCH;
+ length = 6;
+ }
+ break;
+ case 0x04: /* ret */
+ {
+ TCGv t1 = tcg_temp_new_i32();
+
+ /* The new $sp is the old $fp. */
+ tcg_gen_mov_i32(REG(1), REG(0));
+
+ /* Pop the frame pointer. */
+ tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
+ tcg_gen_addi_i32(t1, REG(1), 4);
+ tcg_gen_mov_i32(REG(1), t1);
+
+
+ /* Pop the return address and skip over the static chain
+ slot. */
+ tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
+ tcg_gen_addi_i32(t1, REG(1), 8);
+ tcg_gen_mov_i32(REG(1), t1);
+
+ tcg_temp_free_i32(t1);
+
+ /* Jump... */
+ tcg_gen_exit_tb(0);
+
+ ctx->bstate = BS_BRANCH;
+ }
+ break;
+ case 0x05: /* add.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_add_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x06: /* push */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ tcg_gen_subi_i32(t1, REG(a), 4);
+ tcg_gen_mov_i32(REG(a), t1);
+ tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
+ tcg_temp_free_i32(t1);
+ }
+ break;
+ case 0x07: /* pop */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+ TCGv t1 = tcg_temp_new_i32();
+
+ tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
+ tcg_gen_addi_i32(t1, REG(a), 4);
+ tcg_gen_mov_i32(REG(a), t1);
+ tcg_temp_free_i32(t1);
+ }
+ break;
+ case 0x08: /* lda.l */
+ {
+ int reg = (opcode >> 4) & 0xf;
+
+ TCGv ptr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
+ tcg_temp_free_i32(ptr);
+
+ length = 6;
+ }
+ break;
+ case 0x09: /* sta.l */
+ {
+ int val = (opcode >> 4) & 0xf;
+
+ TCGv ptr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
+ tcg_temp_free_i32(ptr);
+
+ length = 6;
+ }
+ break;
+ case 0x0a: /* ld.l (register indirect) */
+ {
+ int src = opcode & 0xf;
+ int dest = (opcode >> 4) & 0xf;
+
+ tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
+ }
+ break;
+ case 0x0b: /* st.l */
+ {
+ int dest = (opcode >> 4) & 0xf;
+ int val = opcode & 0xf;
+
+ tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
+ }
+ break;
+ case 0x0c: /* ldo.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+ tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
+ tcg_gen_mov_i32(REG(a), t2);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ length = 6;
+ }
+ break;
+ case 0x0d: /* sto.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+ tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ length = 6;
+ }
+ break;
+ case 0x0e: /* cmp */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_mov_i32(cc_a, REG(a));
+ tcg_gen_mov_i32(cc_b, REG(b));
+ }
+ break;
+ case 0x19: /* jsr */
+ {
+ int fnreg = (opcode >> 4) & 0xf;
+
+ /* Load the stack pointer into T0. */
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+
+ tcg_gen_movi_i32(t1, ctx->pc+2);
+
+ /* Make space for the static chain and return address. */
+ tcg_gen_subi_i32(t2, REG(1), 8);
+ tcg_gen_mov_i32(REG(1), t2);
+ tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
+
+ /* Push the current frame pointer. */
+ tcg_gen_subi_i32(t2, REG(1), 4);
+ tcg_gen_mov_i32(REG(1), t2);
+ tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
+
+ /* Set the pc and $fp. */
+ tcg_gen_mov_i32(REG(0), REG(1));
+ tcg_gen_mov_i32(cpu_pc, REG(fnreg));
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_gen_exit_tb(0);
+ ctx->bstate = BS_BRANCH;
+ }
+ break;
+ case 0x1a: /* jmpa */
+ {
+ tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_exit_tb(0);
+ ctx->bstate = BS_BRANCH;
+ length = 6;
+ }
+ break;
+ case 0x1b: /* ldi.b (immediate) */
+ {
+ int reg = (opcode >> 4) & 0xf;
+ int val = cpu_ldl_code(env, ctx->pc+2);
+ tcg_gen_movi_i32(REG(reg), val);
+ length = 6;
+ }
+ break;
+ case 0x1c: /* ld.b (register indirect) */
+ {
+ int src = opcode & 0xf;
+ int dest = (opcode >> 4) & 0xf;
+
+ tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
+ }
+ break;
+ case 0x1d: /* lda.b */
+ {
+ int reg = (opcode >> 4) & 0xf;
+
+ TCGv ptr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
+ tcg_temp_free_i32(ptr);
+
+ length = 6;
+ }
+ break;
+ case 0x1e: /* st.b */
+ {
+ int dest = (opcode >> 4) & 0xf;
+ int val = opcode & 0xf;
+
+ tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
+ }
+ break;
+ case 0x1f: /* sta.b */
+ {
+ int val = (opcode >> 4) & 0xf;
+
+ TCGv ptr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
+ tcg_temp_free_i32(ptr);
+
+ length = 6;
+ }
+ break;
+ case 0x20: /* ldi.s (immediate) */
+ {
+ int reg = (opcode >> 4) & 0xf;
+ int val = cpu_ldl_code(env, ctx->pc+2);
+ tcg_gen_movi_i32(REG(reg), val);
+ length = 6;
+ }
+ break;
+ case 0x21: /* ld.s (register indirect) */
+ {
+ int src = opcode & 0xf;
+ int dest = (opcode >> 4) & 0xf;
+
+ tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
+ }
+ break;
+ case 0x22: /* lda.s */
+ {
+ int reg = (opcode >> 4) & 0xf;
+
+ TCGv ptr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
+ tcg_temp_free_i32(ptr);
+
+ length = 6;
+ }
+ break;
+ case 0x23: /* st.s */
+ {
+ int dest = (opcode >> 4) & 0xf;
+ int val = opcode & 0xf;
+
+ tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
+ }
+ break;
+ case 0x24: /* sta.s */
+ {
+ int val = (opcode >> 4) & 0xf;
+
+ TCGv ptr = tcg_temp_new_i32();
+ tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
+ tcg_temp_free_i32(ptr);
+
+ length = 6;
+ }
+ break;
+ case 0x25: /* jmp */
+ {
+ int reg = (opcode >> 4) & 0xf;
+ tcg_gen_mov_i32(cpu_pc, REG(reg));
+ tcg_gen_exit_tb(0);
+ ctx->bstate = BS_BRANCH;
+ }
+ break;
+ case 0x26: /* and */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_and_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x27: /* lshr */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv sv = tcg_temp_new_i32();
+ tcg_gen_andi_i32(sv, REG(b), 0x1f);
+ tcg_gen_shr_i32(REG(a), REG(a), sv);
+ tcg_temp_free_i32(sv);
+ }
+ break;
+ case 0x28: /* ashl */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv sv = tcg_temp_new_i32();
+ tcg_gen_andi_i32(sv, REG(b), 0x1f);
+ tcg_gen_shl_i32(REG(a), REG(a), sv);
+ tcg_temp_free_i32(sv);
+ }
+ break;
+ case 0x29: /* sub.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_sub_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x2a: /* neg */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_neg_i32(REG(a), REG(b));
+ }
+ break;
+ case 0x2b: /* or */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_or_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x2c: /* not */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_not_i32(REG(a), REG(b));
+ }
+ break;
+ case 0x2d: /* ashr */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv sv = tcg_temp_new_i32();
+ tcg_gen_andi_i32(sv, REG(b), 0x1f);
+ tcg_gen_sar_i32(REG(a), REG(a), sv);
+ tcg_temp_free_i32(sv);
+ }
+ break;
+ case 0x2e: /* xor */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_xor_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x2f: /* mul.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ tcg_gen_mul_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x30: /* swi */
+ {
+ int val = cpu_ldl_code(env, ctx->pc+2);
+
+ TCGv temp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(temp, val);
+ tcg_gen_st_i32(temp, cpu_env,
+ offsetof(CPUMoxieState, sregs[3]));
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
+ gen_helper_raise_exception(cpu_env, temp);
+ tcg_temp_free_i32(temp);
+
+ length = 6;
+ }
+ break;
+ case 0x31: /* div.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
+ }
+ break;
+ case 0x32: /* udiv.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
+ }
+ break;
+ case 0x33: /* mod.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+ tcg_gen_rem_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x34: /* umod.l */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+ tcg_gen_remu_i32(REG(a), REG(a), REG(b));
+ }
+ break;
+ case 0x35: /* brk */
+ {
+ TCGv temp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
+ gen_helper_raise_exception(cpu_env, temp);
+ tcg_temp_free_i32(temp);
+ }
+ break;
+ case 0x36: /* ldo.b */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+ tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
+ tcg_gen_mov_i32(REG(a), t2);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ length = 6;
+ }
+ break;
+ case 0x37: /* sto.b */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+ tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ length = 6;
+ }
+ break;
+ case 0x38: /* ldo.s */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+ tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
+ tcg_gen_mov_i32(REG(a), t2);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ length = 6;
+ }
+ break;
+ case 0x39: /* sto.s */
+ {
+ int a = (opcode >> 4) & 0xf;
+ int b = opcode & 0xf;
+
+ TCGv t1 = tcg_temp_new_i32();
+ TCGv t2 = tcg_temp_new_i32();
+ tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
+ tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+
+ length = 6;
+ }
+ break;
+ default:
+ {
+ TCGv temp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(cpu_pc, ctx->pc);
+ tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
+ gen_helper_raise_exception(cpu_env, temp);
+ tcg_temp_free_i32(temp);
+ }
+ break;
+ }
+ }
+
+ return length;
+}
+
+/* generate intermediate code for basic block 'tb'. */
+static void
+gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
+ bool search_pc)
+{
+ DisasContext ctx;
+ target_ulong pc_start;
+ uint16_t *gen_opc_end;
+ CPUBreakpoint *bp;
+ int j, lj = -1;
+ CPUMoxieState *env = &cpu->env;
+ int num_insns;
+
+ pc_start = tb->pc;
+ gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
+ ctx.pc = pc_start;
+ ctx.saved_pc = -1;
+ ctx.tb = tb;
+ ctx.memidx = 0;
+ ctx.singlestep_enabled = 0;
+ ctx.bstate = BS_NONE;
+ num_insns = 0;
+
+ gen_tb_start();
+ do {
+ if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
+ QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (ctx.pc == bp->pc) {
+ tcg_gen_movi_i32(cpu_pc, ctx.pc);
+ gen_helper_debug(cpu_env);
+ ctx.bstate = BS_EXCP;
+ goto done_generating;
+ }
+ }
+ }
+
+ if (search_pc) {
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
+ if (lj < j) {
+ lj++;
+ while (lj < j) {
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
+ }
+ }
+ tcg_ctx.gen_opc_pc[lj] = ctx.pc;
+ tcg_ctx.gen_opc_instr_start[lj] = 1;
+ tcg_ctx.gen_opc_icount[lj] = num_insns;
+ }
+ ctx.opcode = cpu_lduw_code(env, ctx.pc);
+ ctx.pc += decode_opc(cpu, &ctx);
+ num_insns++;
+
+ if (env->singlestep_enabled) {
+ break;
+ }
+
+ if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
+ break;
+ }
+ } while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
+
+ if (env->singlestep_enabled) {
+ tcg_gen_movi_tl(cpu_pc, ctx.pc);
+ gen_helper_debug(cpu_env);
+ } else {
+ switch (ctx.bstate) {
+ case BS_STOP:
+ case BS_NONE:
+ gen_goto_tb(env, &ctx, 0, ctx.pc);
+ break;
+ case BS_EXCP:
+ tcg_gen_exit_tb(0);
+ break;
+ case BS_BRANCH:
+ default:
+ break;
+ }
+ }
+ done_generating:
+ gen_tb_end(tb, num_insns);
+ *tcg_ctx.gen_opc_ptr = INDEX_op_end;
+ if (search_pc) {
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
+ lj++;
+ while (lj <= j) {
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
+ }
+ } else {
+ tb->size = ctx.pc - pc_start;
+ tb->icount = num_insns;
+ }
+}
+
+void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, false);
+}
+
+void gen_intermediate_code_pc(CPUMoxieState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, true);
+}
+
+void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb, int pc_pos)
+{
+ env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+}
diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs
index 00ac4ad..2c43c34 100644
--- a/target-ppc/Makefile.objs
+++ b/target-ppc/Makefile.objs
@@ -1,11 +1,14 @@
obj-y += cpu-models.o
obj-y += translate.o
-obj-$(CONFIG_SOFTMMU) += machine.o
+ifeq ($(CONFIG_SOFTMMU),y)
+obj-y += machine.o mmu_helper.o mmu-hash32.o
+obj-$(TARGET_PPC64) += mmu-hash64.o
+endif
obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
obj-y += excp_helper.o
obj-y += fpu_helper.o
obj-y += int_helper.o
-obj-y += mmu_helper.o
obj-y += timebase_helper.o
obj-y += misc_helper.o
obj-y += mem_helper.o
+obj-$(CONFIG_USER_ONLY) += user_only_helper.o
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 20ca84e..17f56b7 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1101,9 +1101,9 @@
"PowerPC 7457A v1.2 (G4)")
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
+#if defined(TODO)
POWERPC_DEF("620", CPU_POWERPC_620, 620,
"PowerPC 620")
-#if defined(TODO)
POWERPC_DEF("630", CPU_POWERPC_630, 630,
"PowerPC 630 (POWER3)")
#endif
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 09bfae3..c27cef7 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -68,6 +68,10 @@
#endif
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
+#if defined(CONFIG_SOFTMMU)
+ int (*handle_mmu_fault)(CPUPPCState *env, target_ulong eaddr, int rwx,
+ int mmu_idx);
+#endif
} PowerPCCPUClass;
/**
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 6886666..42c36e2 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -113,13 +113,13 @@
#if defined(TARGET_PPC64)
#define POWERPC_MMU_64 0x00010000
#define POWERPC_MMU_1TSEG 0x00020000
+#define POWERPC_MMU_AMR 0x00040000
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
- /* 620 variant (no segment exceptions) */
- POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
- POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
- /* Architecture 2.06 "degraded" (no 1T segments) */
+ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
+ | POWERPC_MMU_AMR | 0x00000003,
+ /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
#endif /* defined(TARGET_PPC64) */
};
@@ -396,36 +396,12 @@
#define SDR_64_HTABSIZE 0x000000000000001FULL
#endif /* defined(TARGET_PPC64 */
-#define HASH_PTE_SIZE_32 8
-#define HASH_PTE_SIZE_64 16
-
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
uint64_t vsid;
};
-/* Bits in the SLB ESID word */
-#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
-#define SLB_ESID_V 0x0000000008000000ULL /* valid */
-
-/* Bits in the SLB VSID word */
-#define SLB_VSID_SHIFT 12
-#define SLB_VSID_SHIFT_1T 24
-#define SLB_VSID_SSIZE_SHIFT 62
-#define SLB_VSID_B 0xc000000000000000ULL
-#define SLB_VSID_B_256M 0x0000000000000000ULL
-#define SLB_VSID_B_1T 0x4000000000000000ULL
-#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
-#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
-#define SLB_VSID_KS 0x0000000000000800ULL
-#define SLB_VSID_KP 0x0000000000000400ULL
-#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
-#define SLB_VSID_L 0x0000000000000100ULL
-#define SLB_VSID_C 0x0000000000000080ULL /* class */
-#define SLB_VSID_LP 0x0000000000000030ULL
-#define SLB_VSID_ATTR 0x0000000000000FFFULL
-
#define SEGMENT_SHIFT_256M 28
#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
@@ -965,8 +941,6 @@
/* MMU context - only relevant for full system emulation */
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
- /* Address space register */
- target_ulong asr;
/* PowerPC 64 SLB area */
ppc_slb_t slb[64];
int slb_nr;
@@ -1105,20 +1079,6 @@
env->wdt_period[3] = (d_); \
} while (0)
-#if !defined(CONFIG_USER_ONLY)
-/* Context used internally during MMU translations */
-typedef struct mmu_ctx_t mmu_ctx_t;
-struct mmu_ctx_t {
- hwaddr raddr; /* Real address */
- hwaddr eaddr; /* Effective address */
- int prot; /* Protection bits */
- hwaddr hash[2]; /* Pagetable hash values */
- target_ulong ptem; /* Virtual segment ID | API */
- int key; /* Access key */
- int nx; /* Non-execute area */
-};
-#endif
-
#include "cpu-qom.h"
/*****************************************************************************/
@@ -1130,17 +1090,14 @@
is returned if the signal was handled by the virtual CPU. */
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
void *puc);
-int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
- int mmu_idx);
-#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
void ppc_hw_interrupt (CPUPPCState *env);
+#if defined(CONFIG_USER_ONLY)
+int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+ int mmu_idx);
+#endif
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
-#if defined(TARGET_PPC64)
-void ppc_store_asr (CPUPPCState *env, target_ulong value);
-int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
-#endif /* defined(TARGET_PPC64) */
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr (CPUPPCState *env, target_ulong value);
@@ -1172,14 +1129,13 @@
void store_40x_sler (CPUPPCState *env, uint32_t val);
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
-int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
- hwaddr *raddrp, target_ulong address,
- uint32_t pid);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
#endif
#endif
+void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
+
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
{
uint64_t gprv;
@@ -1270,6 +1226,7 @@
#define SPR_601_UDECR (0x006)
#define SPR_LR (0x008)
#define SPR_CTR (0x009)
+#define SPR_UAMR (0x00C)
#define SPR_DSCR (0x011)
#define SPR_DSISR (0x012)
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
@@ -1307,6 +1264,7 @@
#define SPR_MPC_CMPH (0x09B)
#define SPR_MPC_LCTRL1 (0x09C)
#define SPR_MPC_LCTRL2 (0x09D)
+#define SPR_UAMOR (0x09D)
#define SPR_MPC_ICTRL (0x09E)
#define SPR_MPC_BAR (0x09F)
#define SPR_VRSAVE (0x100)
@@ -1489,11 +1447,9 @@
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
#define SPR_PERF3 (0x303)
-#define SPR_620_PMC1R (0x303)
#define SPR_RCPU_MI_RBA3 (0x303)
#define SPR_MPC_MI_EPN (0x303)
#define SPR_PERF4 (0x304)
-#define SPR_620_PMC2R (0x304)
#define SPR_PERF5 (0x305)
#define SPR_MPC_MI_TWC (0x305)
#define SPR_PERF6 (0x306)
@@ -1509,7 +1465,6 @@
#define SPR_RCPU_L2U_RBA2 (0x30A)
#define SPR_MPC_MD_AP (0x30A)
#define SPR_PERFB (0x30B)
-#define SPR_620_MMCR0R (0x30B)
#define SPR_RCPU_L2U_RBA3 (0x30B)
#define SPR_MPC_MD_EPN (0x30B)
#define SPR_PERFC (0x30C)
@@ -1524,9 +1479,7 @@
#define SPR_UPERF1 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_UPERF3 (0x313)
-#define SPR_620_PMC1W (0x313)
#define SPR_UPERF4 (0x314)
-#define SPR_620_PMC2W (0x314)
#define SPR_UPERF5 (0x315)
#define SPR_UPERF6 (0x316)
#define SPR_UPERF7 (0x317)
@@ -1534,7 +1487,6 @@
#define SPR_UPERF9 (0x319)
#define SPR_UPERFA (0x31A)
#define SPR_UPERFB (0x31B)
-#define SPR_620_MMCR0W (0x31B)
#define SPR_UPERFC (0x31C)
#define SPR_UPERFD (0x31D)
#define SPR_UPERFE (0x31E)
@@ -1606,49 +1558,33 @@
#define SPR_USDA (0x3AF)
#define SPR_40x_ZPR (0x3B0)
#define SPR_BOOKE_MAS7 (0x3B0)
-#define SPR_620_PMR0 (0x3B0)
#define SPR_MMCR2 (0x3B0)
#define SPR_PMC5 (0x3B1)
#define SPR_40x_PID (0x3B1)
-#define SPR_620_PMR1 (0x3B1)
#define SPR_PMC6 (0x3B2)
#define SPR_440_MMUCR (0x3B2)
-#define SPR_620_PMR2 (0x3B2)
#define SPR_4xx_CCR0 (0x3B3)
#define SPR_BOOKE_EPLC (0x3B3)
-#define SPR_620_PMR3 (0x3B3)
#define SPR_405_IAC3 (0x3B4)
#define SPR_BOOKE_EPSC (0x3B4)
-#define SPR_620_PMR4 (0x3B4)
#define SPR_405_IAC4 (0x3B5)
-#define SPR_620_PMR5 (0x3B5)
#define SPR_405_DVC1 (0x3B6)
-#define SPR_620_PMR6 (0x3B6)
#define SPR_405_DVC2 (0x3B7)
-#define SPR_620_PMR7 (0x3B7)
#define SPR_BAMR (0x3B7)
#define SPR_MMCR0 (0x3B8)
-#define SPR_620_PMR8 (0x3B8)
#define SPR_PMC1 (0x3B9)
#define SPR_40x_SGR (0x3B9)
-#define SPR_620_PMR9 (0x3B9)
#define SPR_PMC2 (0x3BA)
#define SPR_40x_DCWR (0x3BA)
-#define SPR_620_PMRA (0x3BA)
#define SPR_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
-#define SPR_620_PMRB (0x3BB)
#define SPR_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
-#define SPR_620_PMRC (0x3BC)
#define SPR_401_SKR (0x3BC)
#define SPR_PMC3 (0x3BD)
#define SPR_405_DBCR1 (0x3BD)
-#define SPR_620_PMRD (0x3BD)
#define SPR_PMC4 (0x3BE)
-#define SPR_620_PMRE (0x3BE)
#define SPR_SDA (0x3BF)
-#define SPR_620_PMRF (0x3BF)
#define SPR_403_VTBL (0x3CC)
#define SPR_403_VTBU (0x3CD)
#define SPR_DMISS (0x3D0)
@@ -1716,15 +1652,12 @@
#define SPR_LDSTCR (0x3F8)
#define SPR_L2PMCR (0x3F8)
#define SPR_750FX_HID2 (0x3F8)
-#define SPR_620_BUSCSR (0x3F8)
#define SPR_Exxx_L1FINV0 (0x3F8)
#define SPR_L2CR (0x3F9)
-#define SPR_620_L2CR (0x3F9)
#define SPR_L3CR (0x3FA)
#define SPR_750_TDCH (0x3FA)
#define SPR_IABR2 (0x3FA)
#define SPR_40x_DCCR (0x3FA)
-#define SPR_620_L2SR (0x3FA)
#define SPR_ICTC (0x3FB)
#define SPR_40x_ICCR (0x3FB)
#define SPR_THRM1 (0x3FC)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 9d67926..9e779ea 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -463,6 +463,11 @@
fpscr_set_rounding_mode(env);
}
+void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
+{
+ helper_store_fpscr(env, arg, mask);
+}
+
void helper_float_check_status(CPUPPCState *env)
{
if (env->exception_index == POWERPC_EXCP_PROGRAM &&
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index fcf372a..d33ee66 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -382,7 +382,6 @@
DEF_HELPER_1(load_601_rtcu, tl, env)
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
-DEF_HELPER_2(store_asr, void, env, tl)
DEF_HELPER_1(load_purr, tl, env)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index e663ff0..597066f 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -32,6 +32,7 @@
#include "sysemu/device_tree.h"
#include "hw/sysbus.h"
#include "hw/spapr.h"
+#include "mmu-hash64.h"
#include "hw/sysbus.h"
#include "hw/spapr.h"
@@ -1077,7 +1078,7 @@
dprintf("handle halt\n");
ret = kvmppc_handle_halt(cpu);
break;
-#ifdef CONFIG_PSERIES
+#if defined(TARGET_PPC64)
case KVM_EXIT_PAPR_HCALL:
dprintf("handle PAPR hypercall\n");
run->papr_hcall.ret = spapr_hypercall(cpu,
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 708a840..235b0d5 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -37,7 +37,7 @@
qemu_put_be32s(f, &fpscr);
qemu_put_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
- qemu_put_betls(f, &env->asr);
+ qemu_put_betls(f, &env->spr[SPR_ASR]);
qemu_put_sbe32s(f, &env->slb_nr);
#endif
qemu_put_betls(f, &env->spr[SPR_SDR1]);
@@ -125,7 +125,7 @@
env->fpscr = fpscr;
qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
- qemu_get_betls(f, &env->asr);
+ qemu_get_betls(f, &env->spr[SPR_ASR]);
qemu_get_sbe32s(f, &env->slb_nr);
#endif
qemu_get_betls(f, &sdr1);
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index ba383c8..9783e52 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -252,41 +252,3 @@
#undef HI_IDX
#undef LO_IDX
-
-/*****************************************************************************/
-/* Softmmu support */
-#if !defined(CONFIG_USER_ONLY)
-
-#define MMUSUFFIX _mmu
-
-#define SHIFT 0
-#include "exec/softmmu_template.h"
-
-#define SHIFT 1
-#include "exec/softmmu_template.h"
-
-#define SHIFT 2
-#include "exec/softmmu_template.h"
-
-#define SHIFT 3
-#include "exec/softmmu_template.h"
-
-/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
- uintptr_t retaddr)
-{
- int ret;
-
- ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
- if (unlikely(ret != 0)) {
- if (likely(retaddr)) {
- /* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
- }
- helper_raise_exception_err(env, env->exception_index, env->error_code);
- }
-}
-#endif /* !CONFIG_USER_ONLY */
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index 26edcca..616aab6 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -35,12 +35,6 @@
env->spr[sprn]);
}
#if !defined(CONFIG_USER_ONLY)
-#if defined(TARGET_PPC64)
-void helper_store_asr(CPUPPCState *env, target_ulong val)
-{
- ppc_store_asr(env, val);
-}
-#endif
void helper_store_sdr1(CPUPPCState *env, target_ulong val)
{
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
new file mode 100644
index 0000000..f6adf22
--- /dev/null
+++ b/target-ppc/mmu-hash32.c
@@ -0,0 +1,560 @@
+/*
+ * PowerPC MMU, TLB and BAT emulation helpers for QEMU.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright (c) 2013 David Gibson, IBM Corporation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "helper.h"
+#include "sysemu/kvm.h"
+#include "kvm_ppc.h"
+#include "mmu-hash32.h"
+
+//#define DEBUG_MMU
+//#define DEBUG_BAT
+
+#ifdef DEBUG_MMU
+# define LOG_MMU(...) qemu_log(__VA_ARGS__)
+# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
+#else
+# define LOG_MMU(...) do { } while (0)
+# define LOG_MMU_STATE(...) do { } while (0)
+#endif
+
+#ifdef DEBUG_BATS
+# define LOG_BATS(...) qemu_log(__VA_ARGS__)
+#else
+# define LOG_BATS(...) do { } while (0)
+#endif
+
+struct mmu_ctx_hash32 {
+ hwaddr raddr; /* Real address */
+ int prot; /* Protection bits */
+ int key; /* Access key */
+};
+
+static int ppc_hash32_pp_prot(int key, int pp, int nx)
+{
+ int prot;
+
+ if (key == 0) {
+ switch (pp) {
+ case 0x0:
+ case 0x1:
+ case 0x2:
+ prot = PAGE_READ | PAGE_WRITE;
+ break;
+
+ case 0x3:
+ prot = PAGE_READ;
+ break;
+
+ default:
+ abort();
+ }
+ } else {
+ switch (pp) {
+ case 0x0:
+ prot = 0;
+ break;
+
+ case 0x1:
+ case 0x3:
+ prot = PAGE_READ;
+ break;
+
+ case 0x2:
+ prot = PAGE_READ | PAGE_WRITE;
+ break;
+
+ default:
+ abort();
+ }
+ }
+ if (nx == 0) {
+ prot |= PAGE_EXEC;
+ }
+
+ return prot;
+}
+
+static int ppc_hash32_pte_prot(CPUPPCState *env,
+ target_ulong sr, ppc_hash_pte32_t pte)
+{
+ unsigned pp, key;
+
+ key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
+ pp = pte.pte1 & HPTE32_R_PP;
+
+ return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
+}
+
+static target_ulong hash32_bat_size(CPUPPCState *env,
+ target_ulong batu, target_ulong batl)
+{
+ if ((msr_pr && !(batu & BATU32_VP))
+ || (!msr_pr && !(batu & BATU32_VS))) {
+ return 0;
+ }
+
+ return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
+}
+
+static int hash32_bat_prot(CPUPPCState *env,
+ target_ulong batu, target_ulong batl)
+{
+ int pp, prot;
+
+ prot = 0;
+ pp = batl & BATL32_PP;
+ if (pp != 0) {
+ prot = PAGE_READ | PAGE_EXEC;
+ if (pp == 0x2) {
+ prot |= PAGE_WRITE;
+ }
+ }
+ return prot;
+}
+
+static target_ulong hash32_bat_601_size(CPUPPCState *env,
+ target_ulong batu, target_ulong batl)
+{
+ if (!(batl & BATL32_601_V)) {
+ return 0;
+ }
+
+ return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
+}
+
+static int hash32_bat_601_prot(CPUPPCState *env,
+ target_ulong batu, target_ulong batl)
+{
+ int key, pp;
+
+ pp = batu & BATU32_601_PP;
+ if (msr_pr == 0) {
+ key = !!(batu & BATU32_601_KS);
+ } else {
+ key = !!(batu & BATU32_601_KP);
+ }
+ return ppc_hash32_pp_prot(key, pp, 0);
+}
+
+static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
+ int *prot)
+{
+ target_ulong *BATlt, *BATut;
+ int i;
+
+ LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
+ rwx == 2 ? 'I' : 'D', ea);
+ if (rwx == 2) {
+ BATlt = env->IBAT[1];
+ BATut = env->IBAT[0];
+ } else {
+ BATlt = env->DBAT[1];
+ BATut = env->DBAT[0];
+ }
+ for (i = 0; i < env->nb_BATs; i++) {
+ target_ulong batu = BATut[i];
+ target_ulong batl = BATlt[i];
+ target_ulong mask;
+
+ if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
+ mask = hash32_bat_601_size(env, batu, batl);
+ } else {
+ mask = hash32_bat_size(env, batu, batl);
+ }
+ LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);
+
+ if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
+ hwaddr raddr = (batl & mask) | (ea & ~mask);
+
+ if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
+ *prot = hash32_bat_601_prot(env, batu, batl);
+ } else {
+ *prot = hash32_bat_prot(env, batu, batl);
+ }
+
+ return raddr & TARGET_PAGE_MASK;
+ }
+ }
+
+ /* No hit */
+#if defined(DEBUG_BATS)
+ if (qemu_log_enabled()) {
+ LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
+ for (i = 0; i < 4; i++) {
+ BATu = &BATut[i];
+ BATl = &BATlt[i];
+ BEPIu = *BATu & BATU32_BEPIU;
+ BEPIl = *BATu & BATU32_BEPIL;
+ bl = (*BATu & 0x00001FFC) << 15;
+ LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
+ TARGET_FMT_lx " " TARGET_FMT_lx "\n",
+ __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
+ *BATu, *BATl, BEPIu, BEPIl, bl);
+ }
+ }
+#endif
+
+ return -1;
+}
+
+static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
+ target_ulong eaddr, int rwx,
+ hwaddr *raddr, int *prot)
+{
+ int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
+
+ LOG_MMU("direct store...\n");
+
+ if ((sr & 0x1FF00000) >> 20 == 0x07f) {
+ /* Memory-forced I/O controller interface access */
+ /* If T=1 and BUID=x'07F', the 601 performs a memory access
+ * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
+ */
+ *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return 0;
+ }
+
+ if (rwx == 2) {
+ /* No code fetch is allowed in direct-store areas */
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x10000000;
+ return 1;
+ }
+
+ switch (env->access_type) {
+ case ACCESS_INT:
+ /* Integer load/store : only access allowed */
+ break;
+ case ACCESS_FLOAT:
+ /* Floating point load/store */
+ env->exception_index = POWERPC_EXCP_ALIGN;
+ env->error_code = POWERPC_EXCP_ALIGN_FP;
+ env->spr[SPR_DAR] = eaddr;
+ return 1;
+ case ACCESS_RES:
+ /* lwarx, ldarx or srwcx. */
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x06000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04000000;
+ }
+ return 1;
+ case ACCESS_CACHE:
+ /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
+ /* Should make the instruction do no-op.
+ * As it already do no-op, it's quite easy :-)
+ */
+ *raddr = eaddr;
+ return 0;
+ case ACCESS_EXT:
+ /* eciwx or ecowx */
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x06100000;
+ } else {
+ env->spr[SPR_DSISR] = 0x04100000;
+ }
+ return 1;
+ default:
+ qemu_log("ERROR: instruction should not need "
+ "address translation\n");
+ abort();
+ }
+ if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
+ *raddr = eaddr;
+ return 0;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x0a000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x08000000;
+ }
+ return 1;
+ }
+}
+
+hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
+{
+ return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
+}
+
+static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
+ bool secondary, target_ulong ptem,
+ ppc_hash_pte32_t *pte)
+{
+ hwaddr pte_offset = pteg_off;
+ target_ulong pte0, pte1;
+ int i;
+
+ for (i = 0; i < HPTES_PER_GROUP; i++) {
+ pte0 = ppc_hash32_load_hpte0(env, pte_offset);
+ pte1 = ppc_hash32_load_hpte1(env, pte_offset);
+
+ if ((pte0 & HPTE32_V_VALID)
+ && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
+ && HPTE32_V_COMPARE(pte0, ptem)) {
+ pte->pte0 = pte0;
+ pte->pte1 = pte1;
+ return pte_offset;
+ }
+
+ pte_offset += HASH_PTE_SIZE_32;
+ }
+
+ return -1;
+}
+
+static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
+ target_ulong sr, target_ulong eaddr,
+ ppc_hash_pte32_t *pte)
+{
+ hwaddr pteg_off, pte_offset;
+ hwaddr hash;
+ uint32_t vsid, pgidx, ptem;
+
+ vsid = sr & SR32_VSID;
+ pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
+ hash = vsid ^ pgidx;
+ ptem = (vsid << 7) | (pgidx >> 10);
+
+ /* Page address translation */
+ LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
+ " hash " TARGET_FMT_plx "\n",
+ env->htab_base, env->htab_mask, hash);
+
+ /* Primary PTEG lookup */
+ LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ " vsid=%" PRIx32 " ptem=%" PRIx32
+ " hash=" TARGET_FMT_plx "\n",
+ env->htab_base, env->htab_mask, vsid, ptem, hash);
+ pteg_off = get_pteg_offset32(env, hash);
+ pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
+ if (pte_offset == -1) {
+ /* Secondary PTEG lookup */
+ LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ " vsid=%" PRIx32 " api=%" PRIx32
+ " hash=" TARGET_FMT_plx "\n", env->htab_base,
+ env->htab_mask, vsid, ptem, ~hash);
+ pteg_off = get_pteg_offset32(env, ~hash);
+ pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
+ }
+
+ return pte_offset;
+}
+
+static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
+ target_ulong eaddr)
+{
+ hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
+ hwaddr mask = ~TARGET_PAGE_MASK;
+
+ return (rpn & ~mask) | (eaddr & mask);
+}
+
+int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
+ int mmu_idx)
+{
+ target_ulong sr;
+ hwaddr pte_offset;
+ ppc_hash_pte32_t pte;
+ int prot;
+ uint32_t new_pte1;
+ const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
+ hwaddr raddr;
+
+ assert((rwx == 0) || (rwx == 1) || (rwx == 2));
+
+ /* 1. Handle real mode accesses */
+ if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
+ /* Translation is off */
+ raddr = eaddr;
+ tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
+ TARGET_PAGE_SIZE);
+ return 0;
+ }
+
+ /* 2. Check Block Address Translation entries (BATs) */
+ if (env->nb_BATs != 0) {
+ raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
+ if (raddr != -1) {
+ if (need_prot[rwx] & ~prot) {
+ if (rwx == 2) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x08000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x0a000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x08000000;
+ }
+ }
+ return 1;
+ }
+
+ tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ raddr & TARGET_PAGE_MASK, prot, mmu_idx,
+ TARGET_PAGE_SIZE);
+ return 0;
+ }
+ }
+
+ /* 3. Look up the Segment Register */
+ sr = env->sr[eaddr >> 28];
+
+ /* 4. Handle direct store segments */
+ if (sr & SR32_T) {
+ if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
+ &raddr, &prot) == 0) {
+ tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ raddr & TARGET_PAGE_MASK, prot, mmu_idx,
+ TARGET_PAGE_SIZE);
+ return 0;
+ } else {
+ return 1;
+ }
+ }
+
+ /* 5. Check for segment level no-execute violation */
+ if ((rwx == 2) && (sr & SR32_NX)) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x10000000;
+ return 1;
+ }
+
+ /* 6. Locate the PTE in the hash table */
+ pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
+ if (pte_offset == -1) {
+ if (rwx == 2) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x40000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x42000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x40000000;
+ }
+ }
+
+ return 1;
+ }
+ LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
+
+ /* 7. Check access permissions */
+
+ prot = ppc_hash32_pte_prot(env, sr, pte);
+
+ if (need_prot[rwx] & ~prot) {
+ /* Access right violation */
+ LOG_MMU("PTE access rejected\n");
+ if (rwx == 2) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x08000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x0a000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x08000000;
+ }
+ }
+ return 1;
+ }
+
+ LOG_MMU("PTE access granted !\n");
+
+ /* 8. Update PTE referenced and changed bits if necessary */
+
+ new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
+ if (rwx == 1) {
+ new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
+ } else {
+ /* Treat the page as read-only for now, so that a later write
+ * will pass through this function again to set the C bit */
+ prot &= ~PAGE_WRITE;
+ }
+
+ if (new_pte1 != pte.pte1) {
+ ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
+ }
+
+ /* 9. Determine the real address from the PTE */
+
+ raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
+
+ tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ prot, mmu_idx, TARGET_PAGE_SIZE);
+
+ return 0;
+}
+
+hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
+{
+ target_ulong sr;
+ hwaddr pte_offset;
+ ppc_hash_pte32_t pte;
+ int prot;
+
+ if (msr_dr == 0) {
+ /* Translation is off */
+ return eaddr;
+ }
+
+ if (env->nb_BATs != 0) {
+ hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
+ if (raddr != -1) {
+ return raddr;
+ }
+ }
+
+ sr = env->sr[eaddr >> 28];
+
+ if (sr & SR32_T) {
+ /* FIXME: Add suitable debug support for Direct Store segments */
+ return -1;
+ }
+
+ pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
+ if (pte_offset == -1) {
+ return -1;
+ }
+
+ return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
+}
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
new file mode 100644
index 0000000..884786b
--- /dev/null
+++ b/target-ppc/mmu-hash32.h
@@ -0,0 +1,102 @@
+#if !defined (__MMU_HASH32_H__)
+#define __MMU_HASH32_H__
+
+#ifndef CONFIG_USER_ONLY
+
+hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
+hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
+int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+ int mmu_idx);
+
+/*
+ * Segment register definitions
+ */
+
+#define SR32_T 0x80000000
+#define SR32_KS 0x40000000
+#define SR32_KP 0x20000000
+#define SR32_NX 0x10000000
+#define SR32_VSID 0x00ffffff
+
+/*
+ * Block Address Translation (BAT) definitions
+ */
+
+#define BATU32_BEPI 0xfffe0000
+#define BATU32_BL 0x00001ffc
+#define BATU32_VS 0x00000002
+#define BATU32_VP 0x00000001
+
+
+#define BATL32_BRPN 0xfffe0000
+#define BATL32_WIMG 0x00000078
+#define BATL32_PP 0x00000003
+
+/* PowerPC 601 has slightly different BAT registers */
+
+#define BATU32_601_KS 0x00000008
+#define BATU32_601_KP 0x00000004
+#define BATU32_601_PP 0x00000003
+
+#define BATL32_601_V 0x00000040
+#define BATL32_601_BL 0x0000003f
+
+/*
+ * Hash page table definitions
+ */
+
+#define HPTES_PER_GROUP 8
+#define HASH_PTE_SIZE_32 8
+#define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP)
+
+#define HPTE32_V_VALID 0x80000000
+#define HPTE32_V_VSID 0x7fffff80
+#define HPTE32_V_SECONDARY 0x00000040
+#define HPTE32_V_API 0x0000003f
+#define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf))
+
+#define HPTE32_R_RPN 0xfffff000
+#define HPTE32_R_R 0x00000100
+#define HPTE32_R_C 0x00000080
+#define HPTE32_R_W 0x00000040
+#define HPTE32_R_I 0x00000020
+#define HPTE32_R_M 0x00000010
+#define HPTE32_R_G 0x00000008
+#define HPTE32_R_WIMG 0x00000078
+#define HPTE32_R_PP 0x00000003
+
+static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
+ hwaddr pte_offset)
+{
+ assert(!env->external_htab); /* Not supported on 32-bit for now */
+ return ldl_phys(env->htab_base + pte_offset);
+}
+
+static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
+ hwaddr pte_offset)
+{
+ assert(!env->external_htab); /* Not supported on 32-bit for now */
+ return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
+}
+
+static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
+ hwaddr pte_offset, target_ulong pte0)
+{
+ assert(!env->external_htab); /* Not supported on 32-bit for now */
+ stl_phys(env->htab_base + pte_offset, pte0);
+}
+
+static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
+ hwaddr pte_offset, target_ulong pte1)
+{
+ assert(!env->external_htab); /* Not supported on 32-bit for now */
+ stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
+}
+
+typedef struct {
+ uint32_t pte0, pte1;
+} ppc_hash_pte32_t;
+
+#endif /* CONFIG_USER_ONLY */
+
+#endif /* __MMU_HASH32_H__ */
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
new file mode 100644
index 0000000..43ccf45
--- /dev/null
+++ b/target-ppc/mmu-hash64.c
@@ -0,0 +1,546 @@
+/*
+ * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright (c) 2013 David Gibson, IBM Corporation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "cpu.h"
+#include "helper.h"
+#include "sysemu/kvm.h"
+#include "kvm_ppc.h"
+#include "mmu-hash64.h"
+
+//#define DEBUG_MMU
+//#define DEBUG_SLB
+
+#ifdef DEBUG_MMU
+# define LOG_MMU(...) qemu_log(__VA_ARGS__)
+# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
+#else
+# define LOG_MMU(...) do { } while (0)
+# define LOG_MMU_STATE(...) do { } while (0)
+#endif
+
+#ifdef DEBUG_SLB
+# define LOG_SLB(...) qemu_log(__VA_ARGS__)
+#else
+# define LOG_SLB(...) do { } while (0)
+#endif
+
+/*
+ * SLB handling
+ */
+
+static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
+{
+ uint64_t esid_256M, esid_1T;
+ int n;
+
+ LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
+
+ esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
+ esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
+
+ for (n = 0; n < env->slb_nr; n++) {
+ ppc_slb_t *slb = &env->slb[n];
+
+ LOG_SLB("%s: slot %d %016" PRIx64 " %016"
+ PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
+ /* We check for 1T matches on all MMUs here - if the MMU
+ * doesn't have 1T segment support, we will have prevented 1T
+ * entries from being inserted in the slbmte code. */
+ if (((slb->esid == esid_256M) &&
+ ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
+ || ((slb->esid == esid_1T) &&
+ ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
+ return slb;
+ }
+ }
+
+ return NULL;
+}
+
+void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
+{
+ int i;
+ uint64_t slbe, slbv;
+
+ cpu_synchronize_state(env);
+
+ cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+ for (i = 0; i < env->slb_nr; i++) {
+ slbe = env->slb[i].esid;
+ slbv = env->slb[i].vsid;
+ if (slbe == 0 && slbv == 0) {
+ continue;
+ }
+ cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+ i, slbe, slbv);
+ }
+}
+
+void helper_slbia(CPUPPCState *env)
+{
+ int n, do_invalidate;
+
+ do_invalidate = 0;
+ /* XXX: Warning: slbia never invalidates the first segment */
+ for (n = 1; n < env->slb_nr; n++) {
+ ppc_slb_t *slb = &env->slb[n];
+
+ if (slb->esid & SLB_ESID_V) {
+ slb->esid &= ~SLB_ESID_V;
+ /* XXX: given the fact that segment size is 256 MB or 1TB,
+ * and we still don't have a tlb_flush_mask(env, n, mask)
+ * in QEMU, we just invalidate all TLBs
+ */
+ do_invalidate = 1;
+ }
+ }
+ if (do_invalidate) {
+ tlb_flush(env, 1);
+ }
+}
+
+void helper_slbie(CPUPPCState *env, target_ulong addr)
+{
+ ppc_slb_t *slb;
+
+ slb = slb_lookup(env, addr);
+ if (!slb) {
+ return;
+ }
+
+ if (slb->esid & SLB_ESID_V) {
+ slb->esid &= ~SLB_ESID_V;
+
+ /* XXX: given the fact that segment size is 256 MB or 1TB,
+ * and we still don't have a tlb_flush_mask(env, n, mask)
+ * in QEMU, we just invalidate all TLBs
+ */
+ tlb_flush(env, 1);
+ }
+}
+
+int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+{
+ int slot = rb & 0xfff;
+ ppc_slb_t *slb = &env->slb[slot];
+
+ if (rb & (0x1000 - env->slb_nr)) {
+ return -1; /* Reserved bits set or slot too high */
+ }
+ if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
+ return -1; /* Bad segment size */
+ }
+ if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
+ return -1; /* 1T segment on MMU that doesn't support it */
+ }
+
+ /* Mask out the slot number as we store the entry */
+ slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
+ slb->vsid = rs;
+
+ LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
+ " %016" PRIx64 "\n", __func__, slot, rb, rs,
+ slb->esid, slb->vsid);
+
+ return 0;
+}
+
+static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
+ target_ulong *rt)
+{
+ int slot = rb & 0xfff;
+ ppc_slb_t *slb = &env->slb[slot];
+
+ if (slot >= env->slb_nr) {
+ return -1;
+ }
+
+ *rt = slb->esid;
+ return 0;
+}
+
+static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
+ target_ulong *rt)
+{
+ int slot = rb & 0xfff;
+ ppc_slb_t *slb = &env->slb[slot];
+
+ if (slot >= env->slb_nr) {
+ return -1;
+ }
+
+ *rt = slb->vsid;
+ return 0;
+}
+
+void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+{
+ if (ppc_store_slb(env, rb, rs) < 0) {
+ helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL);
+ }
+}
+
+target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
+{
+ target_ulong rt = 0;
+
+ if (ppc_load_slb_esid(env, rb, &rt) < 0) {
+ helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL);
+ }
+ return rt;
+}
+
+target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+{
+ target_ulong rt = 0;
+
+ if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
+ helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL);
+ }
+ return rt;
+}
+
+/*
+ * 64-bit hash table MMU handling
+ */
+
+static int ppc_hash64_pte_prot(CPUPPCState *env,
+ ppc_slb_t *slb, ppc_hash_pte64_t pte)
+{
+ unsigned pp, key;
+ /* Some pp bit combinations have undefined behaviour, so default
+ * to no access in those cases */
+ int prot = 0;
+
+ key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
+ : (slb->vsid & SLB_VSID_KS));
+ pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
+
+ if (key == 0) {
+ switch (pp) {
+ case 0x0:
+ case 0x1:
+ case 0x2:
+ prot = PAGE_READ | PAGE_WRITE;
+ break;
+
+ case 0x3:
+ case 0x6:
+ prot = PAGE_READ;
+ break;
+ }
+ } else {
+ switch (pp) {
+ case 0x0:
+ case 0x6:
+ prot = 0;
+ break;
+
+ case 0x1:
+ case 0x3:
+ prot = PAGE_READ;
+ break;
+
+ case 0x2:
+ prot = PAGE_READ | PAGE_WRITE;
+ break;
+ }
+ }
+
+ /* No execute if either noexec or guarded bits set */
+ if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
+ || (slb->vsid & SLB_VSID_N)) {
+ prot |= PAGE_EXEC;
+ }
+
+ return prot;
+}
+
+static int ppc_hash64_amr_prot(CPUPPCState *env, ppc_hash_pte64_t pte)
+{
+ int key, amrbits;
+ int prot = PAGE_EXEC;
+
+
+ /* Only recent MMUs implement Virtual Page Class Key Protection */
+ if (!(env->mmu_model & POWERPC_MMU_AMR)) {
+ return PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ }
+
+ key = HPTE64_R_KEY(pte.pte1);
+ amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
+
+ /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
+ /* env->spr[SPR_AMR]); */
+
+ if (amrbits & 0x2) {
+ prot |= PAGE_WRITE;
+ }
+ if (amrbits & 0x1) {
+ prot |= PAGE_READ;
+ }
+
+ return prot;
+}
+
+static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off,
+ bool secondary, target_ulong ptem,
+ ppc_hash_pte64_t *pte)
+{
+ hwaddr pte_offset = pteg_off;
+ target_ulong pte0, pte1;
+ int i;
+
+ for (i = 0; i < HPTES_PER_GROUP; i++) {
+ pte0 = ppc_hash64_load_hpte0(env, pte_offset);
+ pte1 = ppc_hash64_load_hpte1(env, pte_offset);
+
+ if ((pte0 & HPTE64_V_VALID)
+ && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
+ && HPTE64_V_COMPARE(pte0, ptem)) {
+ pte->pte0 = pte0;
+ pte->pte1 = pte1;
+ return pte_offset;
+ }
+
+ pte_offset += HASH_PTE_SIZE_64;
+ }
+
+ return -1;
+}
+
+static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
+ ppc_slb_t *slb, target_ulong eaddr,
+ ppc_hash_pte64_t *pte)
+{
+ hwaddr pteg_off, pte_offset;
+ hwaddr hash;
+ uint64_t vsid, epnshift, epnmask, epn, ptem;
+
+ /* Page size according to the SLB, which we use to generate the
+ * EPN for hash table lookup.. When we implement more recent MMU
+ * extensions this might be different from the actual page size
+ * encoded in the PTE */
+ epnshift = (slb->vsid & SLB_VSID_L)
+ ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
+ epnmask = ~((1ULL << epnshift) - 1);
+
+ if (slb->vsid & SLB_VSID_B) {
+ /* 1TB segment */
+ vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
+ epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
+ hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
+ } else {
+ /* 256M segment */
+ vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
+ epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
+ hash = vsid ^ (epn >> epnshift);
+ }
+ ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
+
+ /* Page address translation */
+ LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
+ " hash " TARGET_FMT_plx "\n",
+ env->htab_base, env->htab_mask, hash);
+
+ /* Primary PTEG lookup */
+ LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
+ " hash=" TARGET_FMT_plx "\n",
+ env->htab_base, env->htab_mask, vsid, ptem, hash);
+ pteg_off = (hash * HASH_PTEG_SIZE_64) & env->htab_mask;
+ pte_offset = ppc_hash64_pteg_search(env, pteg_off, 0, ptem, pte);
+
+ if (pte_offset == -1) {
+ /* Secondary PTEG lookup */
+ LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
+ " hash=" TARGET_FMT_plx "\n", env->htab_base,
+ env->htab_mask, vsid, ptem, ~hash);
+
+ pteg_off = (~hash * HASH_PTEG_SIZE_64) & env->htab_mask;
+ pte_offset = ppc_hash64_pteg_search(env, pteg_off, 1, ptem, pte);
+ }
+
+ return pte_offset;
+}
+
+static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
+ target_ulong eaddr)
+{
+ hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
+ /* FIXME: Add support for SLLP extended page sizes */
+ int target_page_bits = (slb->vsid & SLB_VSID_L)
+ ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
+ hwaddr mask = (1ULL << target_page_bits) - 1;
+
+ return (rpn & ~mask) | (eaddr & mask);
+}
+
+int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
+ int rwx, int mmu_idx)
+{
+ ppc_slb_t *slb;
+ hwaddr pte_offset;
+ ppc_hash_pte64_t pte;
+ int pp_prot, amr_prot, prot;
+ uint64_t new_pte1;
+ const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
+ hwaddr raddr;
+
+ assert((rwx == 0) || (rwx == 1) || (rwx == 2));
+
+ /* 1. Handle real mode accesses */
+ if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
+ /* Translation is off */
+ /* In real mode the top 4 effective address bits are ignored */
+ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
+ tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
+ TARGET_PAGE_SIZE);
+ return 0;
+ }
+
+ /* 2. Translation is on, so look up the SLB */
+ slb = slb_lookup(env, eaddr);
+
+ if (!slb) {
+ if (rwx == 2) {
+ env->exception_index = POWERPC_EXCP_ISEG;
+ env->error_code = 0;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSEG;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ }
+ return 1;
+ }
+
+ /* 3. Check for segment level no-execute violation */
+ if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x10000000;
+ return 1;
+ }
+
+ /* 4. Locate the PTE in the hash table */
+ pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
+ if (pte_offset == -1) {
+ if (rwx == 2) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x40000000;
+ } else {
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (rwx == 1) {
+ env->spr[SPR_DSISR] = 0x42000000;
+ } else {
+ env->spr[SPR_DSISR] = 0x40000000;
+ }
+ }
+ return 1;
+ }
+ LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
+
+ /* 5. Check access permissions */
+
+ pp_prot = ppc_hash64_pte_prot(env, slb, pte);
+ amr_prot = ppc_hash64_amr_prot(env, pte);
+ prot = pp_prot & amr_prot;
+
+ if ((need_prot[rwx] & ~prot) != 0) {
+ /* Access right violation */
+ LOG_MMU("PTE access rejected\n");
+ if (rwx == 2) {
+ env->exception_index = POWERPC_EXCP_ISI;
+ env->error_code = 0x08000000;
+ } else {
+ target_ulong dsisr = 0;
+
+ env->exception_index = POWERPC_EXCP_DSI;
+ env->error_code = 0;
+ env->spr[SPR_DAR] = eaddr;
+ if (need_prot[rwx] & ~pp_prot) {
+ dsisr |= 0x08000000;
+ }
+ if (rwx == 1) {
+ dsisr |= 0x02000000;
+ }
+ if (need_prot[rwx] & ~amr_prot) {
+ dsisr |= 0x00200000;
+ }
+ env->spr[SPR_DSISR] = dsisr;
+ }
+ return 1;
+ }
+
+ LOG_MMU("PTE access granted !\n");
+
+ /* 6. Update PTE referenced and changed bits if necessary */
+
+ new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
+ if (rwx == 1) {
+ new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
+ } else {
+ /* Treat the page as read-only for now, so that a later write
+ * will pass through this function again to set the C bit */
+ prot &= ~PAGE_WRITE;
+ }
+
+ if (new_pte1 != pte.pte1) {
+ ppc_hash64_store_hpte1(env, pte_offset, new_pte1);
+ }
+
+ /* 7. Determine the real address from the PTE */
+
+ raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
+
+ tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ prot, mmu_idx, TARGET_PAGE_SIZE);
+
+ return 0;
+}
+
+hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
+{
+ ppc_slb_t *slb;
+ hwaddr pte_offset;
+ ppc_hash_pte64_t pte;
+
+ if (msr_dr == 0) {
+ /* In real mode the top 4 effective address bits are ignored */
+ return addr & 0x0FFFFFFFFFFFFFFFULL;
+ }
+
+ slb = slb_lookup(env, addr);
+ if (!slb) {
+ return -1;
+ }
+
+ pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte);
+ if (pte_offset == -1) {
+ return -1;
+ }
+
+ return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK;
+}
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
new file mode 100644
index 0000000..55f5a23
--- /dev/null
+++ b/target-ppc/mmu-hash64.h
@@ -0,0 +1,124 @@
+#if !defined (__MMU_HASH64_H__)
+#define __MMU_HASH64_H__
+
+#ifndef CONFIG_USER_ONLY
+
+#ifdef TARGET_PPC64
+void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
+int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
+hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
+int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+ int mmu_idx);
+#endif
+
+/*
+ * SLB definitions
+ */
+
+/* Bits in the SLB ESID word */
+#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
+#define SLB_ESID_V 0x0000000008000000ULL /* valid */
+
+/* Bits in the SLB VSID word */
+#define SLB_VSID_SHIFT 12
+#define SLB_VSID_SHIFT_1T 24
+#define SLB_VSID_SSIZE_SHIFT 62
+#define SLB_VSID_B 0xc000000000000000ULL
+#define SLB_VSID_B_256M 0x0000000000000000ULL
+#define SLB_VSID_B_1T 0x4000000000000000ULL
+#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
+#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
+#define SLB_VSID_KS 0x0000000000000800ULL
+#define SLB_VSID_KP 0x0000000000000400ULL
+#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
+#define SLB_VSID_L 0x0000000000000100ULL
+#define SLB_VSID_C 0x0000000000000080ULL /* class */
+#define SLB_VSID_LP 0x0000000000000030ULL
+#define SLB_VSID_ATTR 0x0000000000000FFFULL
+
+/*
+ * Hash page table definitions
+ */
+
+#define HPTES_PER_GROUP 8
+#define HASH_PTE_SIZE_64 16
+#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
+
+#define HPTE64_V_SSIZE_SHIFT 62
+#define HPTE64_V_AVPN_SHIFT 7
+#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
+#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
+#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80ULL))
+#define HPTE64_V_LARGE 0x0000000000000004ULL
+#define HPTE64_V_SECONDARY 0x0000000000000002ULL
+#define HPTE64_V_VALID 0x0000000000000001ULL
+
+#define HPTE64_R_PP0 0x8000000000000000ULL
+#define HPTE64_R_TS 0x4000000000000000ULL
+#define HPTE64_R_KEY_HI 0x3000000000000000ULL
+#define HPTE64_R_RPN_SHIFT 12
+#define HPTE64_R_RPN 0x0ffffffffffff000ULL
+#define HPTE64_R_FLAGS 0x00000000000003ffULL
+#define HPTE64_R_PP 0x0000000000000003ULL
+#define HPTE64_R_N 0x0000000000000004ULL
+#define HPTE64_R_G 0x0000000000000008ULL
+#define HPTE64_R_M 0x0000000000000010ULL
+#define HPTE64_R_I 0x0000000000000020ULL
+#define HPTE64_R_W 0x0000000000000040ULL
+#define HPTE64_R_WIMG 0x0000000000000078ULL
+#define HPTE64_R_C 0x0000000000000080ULL
+#define HPTE64_R_R 0x0000000000000100ULL
+#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
+#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 60) | \
+ (((x) & HPTE64_R_KEY_LO) >> 9))
+
+#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
+#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
+
+static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
+ hwaddr pte_offset)
+{
+ if (env->external_htab) {
+ return ldq_p(env->external_htab + pte_offset);
+ } else {
+ return ldq_phys(env->htab_base + pte_offset);
+ }
+}
+
+static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
+ hwaddr pte_offset)
+{
+ if (env->external_htab) {
+ return ldq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2);
+ } else {
+ return ldq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
+ }
+}
+
+static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
+ hwaddr pte_offset, target_ulong pte0)
+{
+ if (env->external_htab) {
+ stq_p(env->external_htab + pte_offset, pte0);
+ } else {
+ stq_phys(env->htab_base + pte_offset, pte0);
+ }
+}
+
+static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
+ hwaddr pte_offset, target_ulong pte1)
+{
+ if (env->external_htab) {
+ stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
+ } else {
+ stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
+ }
+}
+
+typedef struct {
+ uint64_t pte0, pte1;
+} ppc_hash_pte64_t;
+
+#endif /* CONFIG_USER_ONLY */
+
+#endif /* !defined (__MMU_HASH64_H__) */
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 1cc1c16..acf0133 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -20,10 +20,11 @@
#include "helper.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
+#include "mmu-hash64.h"
+#include "mmu-hash32.h"
//#define DEBUG_MMU
//#define DEBUG_BATS
-//#define DEBUG_SLB
//#define DEBUG_SOFTWARE_TLB
//#define DUMP_PAGE_TABLES
//#define DEBUG_SOFTWARE_TLB
@@ -49,39 +50,21 @@
# define LOG_BATS(...) do { } while (0)
#endif
-#ifdef DEBUG_SLB
-# define LOG_SLB(...) qemu_log(__VA_ARGS__)
-#else
-# define LOG_SLB(...) do { } while (0)
-#endif
-
/*****************************************************************************/
/* PowerPC MMU emulation */
-#if defined(CONFIG_USER_ONLY)
-int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
- int mmu_idx)
-{
- int exception, error_code;
- if (rw == 2) {
- exception = POWERPC_EXCP_ISI;
- error_code = 0x40000000;
- } else {
- exception = POWERPC_EXCP_DSI;
- error_code = 0x40000000;
- if (rw) {
- error_code |= 0x02000000;
- }
- env->spr[SPR_DAR] = address;
- env->spr[SPR_DSISR] = error_code;
- }
- env->exception_index = exception;
- env->error_code = error_code;
+/* Context used internally during MMU translations */
+typedef struct mmu_ctx_t mmu_ctx_t;
+struct mmu_ctx_t {
+ hwaddr raddr; /* Real address */
+ hwaddr eaddr; /* Effective address */
+ int prot; /* Protection bits */
+ hwaddr hash[2]; /* Pagetable hash values */
+ target_ulong ptem; /* Virtual segment ID | API */
+ int key; /* Access key */
+ int nx; /* Non-execute area */
+};
- return 1;
-}
-
-#else
/* Common routines used by software and hardware TLBs emulation */
static inline int pte_is_valid(target_ulong pte0)
{
@@ -93,31 +76,14 @@
*pte0 &= ~0x80000000;
}
-#if defined(TARGET_PPC64)
-static inline int pte64_is_valid(target_ulong pte0)
-{
- return pte0 & 0x0000000000000001ULL ? 1 : 0;
-}
-
-static inline void pte64_invalidate(target_ulong *pte0)
-{
- *pte0 &= ~0x0000000000000001ULL;
-}
-#endif
-
#define PTE_PTEM_MASK 0x7FFFFFBF
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
-#if defined(TARGET_PPC64)
-#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
-#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
-#endif
-static inline int pp_check(int key, int pp, int nx)
+static int pp_check(int key, int pp, int nx)
{
int access;
/* Compute access rights */
- /* When pp is 3/7, the result is undefined. Set it to noaccess */
access = 0;
if (key == 0) {
switch (pp) {
@@ -127,14 +93,12 @@
access |= PAGE_WRITE;
/* No break here */
case 0x3:
- case 0x6:
access |= PAGE_READ;
break;
}
} else {
switch (pp) {
case 0x0:
- case 0x6:
access = 0;
break;
case 0x1:
@@ -153,7 +117,7 @@
return access;
}
-static inline int check_prot(int prot, int rw, int access_type)
+static int check_prot(int prot, int rw, int access_type)
{
int ret;
@@ -180,40 +144,21 @@
return ret;
}
-static inline int pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
- target_ulong pte1, int h, int rw, int type)
+static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
target_ulong ptem, mmask;
int access, ret, pteh, ptev, pp;
ret = -1;
/* Check validity and table match */
-#if defined(TARGET_PPC64)
- if (is_64b) {
- ptev = pte64_is_valid(pte0);
- pteh = (pte0 >> 1) & 1;
- } else
-#endif
- {
- ptev = pte_is_valid(pte0);
- pteh = (pte0 >> 6) & 1;
- }
+ ptev = pte_is_valid(pte0);
+ pteh = (pte0 >> 6) & 1;
if (ptev && h == pteh) {
/* Check vsid & api */
-#if defined(TARGET_PPC64)
- if (is_64b) {
- ptem = pte0 & PTE64_PTEM_MASK;
- mmask = PTE64_CHECK_MASK;
- pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
- ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
- ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
- } else
-#endif
- {
- ptem = pte0 & PTE_PTEM_MASK;
- mmask = PTE_CHECK_MASK;
- pp = pte1 & 0x00000003;
- }
+ ptem = pte0 & PTE_PTEM_MASK;
+ mmask = PTE_CHECK_MASK;
+ pp = pte1 & 0x00000003;
if (ptem == ctx->ptem) {
if (ctx->raddr != (hwaddr)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
@@ -241,22 +186,8 @@
return ret;
}
-static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
- target_ulong pte1, int h, int rw, int type)
-{
- return pte_check(ctx, 0, pte0, pte1, h, rw, type);
-}
-
-#if defined(TARGET_PPC64)
-static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
- target_ulong pte1, int h, int rw, int type)
-{
- return pte_check(ctx, 1, pte0, pte1, h, rw, type);
-}
-#endif
-
-static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
- int ret, int rw)
+static int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
+ int ret, int rw)
{
int store = 0;
@@ -392,7 +323,7 @@
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, eaddr, tlb->pte1,
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
- switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
+ switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
case -3:
/* TLB inconsistency */
return -1;
@@ -454,34 +385,8 @@
*protp = prot;
}
-static inline void bat_601_size_prot(CPUPPCState *env, target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu, target_ulong *BATl)
-{
- target_ulong bl;
- int key, pp, valid, prot;
-
- bl = (*BATl & 0x0000003F) << 17;
- LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
- (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
- prot = 0;
- valid = (*BATl >> 6) & 1;
- if (valid) {
- pp = *BATu & 0x00000003;
- if (msr_pr == 0) {
- key = (*BATu >> 3) & 1;
- } else {
- key = (*BATu >> 2) & 1;
- }
- prot = pp_check(key, pp, 0);
- }
- *blp = bl;
- *validp = valid;
- *protp = prot;
-}
-
-static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong virtual, int rw, int type)
+static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong virtual, int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong BEPIl, BEPIu, bl;
@@ -505,11 +410,7 @@
BATl = &BATlt[i];
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
- if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
- bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
- } else {
- bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
- }
+ bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
" BATl " TARGET_FMT_lx "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
@@ -556,332 +457,35 @@
return ret;
}
-static inline hwaddr get_pteg_offset(CPUPPCState *env,
- hwaddr hash,
- int pte_size)
-{
- return (hash * pte_size * 8) & env->htab_mask;
-}
-
-/* PTE table lookup */
-static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
- int rw, int type, int target_page_bits)
-{
- hwaddr pteg_off;
- target_ulong pte0, pte1;
- int i, good = -1;
- int ret, r;
-
- ret = -1; /* No entry found */
- pteg_off = get_pteg_offset(env, ctx->hash[h],
- is_64b ? HASH_PTE_SIZE_64 : HASH_PTE_SIZE_32);
- for (i = 0; i < 8; i++) {
-#if defined(TARGET_PPC64)
- if (is_64b) {
- if (env->external_htab) {
- pte0 = ldq_p(env->external_htab + pteg_off + (i * 16));
- pte1 = ldq_p(env->external_htab + pteg_off + (i * 16) + 8);
- } else {
- pte0 = ldq_phys(env->htab_base + pteg_off + (i * 16));
- pte1 = ldq_phys(env->htab_base + pteg_off + (i * 16) + 8);
- }
-
- r = pte64_check(ctx, pte0, pte1, h, rw, type);
- LOG_MMU("Load pte from %016" HWADDR_PRIx " => " TARGET_FMT_lx " "
- TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
- pteg_off + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
- (int)((pte0 >> 1) & 1), ctx->ptem);
- } else
-#endif
- {
- if (env->external_htab) {
- pte0 = ldl_p(env->external_htab + pteg_off + (i * 8));
- pte1 = ldl_p(env->external_htab + pteg_off + (i * 8) + 4);
- } else {
- pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));
- pte1 = ldl_phys(env->htab_base + pteg_off + (i * 8) + 4);
- }
- r = pte32_check(ctx, pte0, pte1, h, rw, type);
- LOG_MMU("Load pte from %08" HWADDR_PRIx " => " TARGET_FMT_lx " "
- TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
- pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
- (int)((pte0 >> 6) & 1), ctx->ptem);
- }
- switch (r) {
- case -3:
- /* PTE inconsistency */
- return -1;
- case -2:
- /* Access violation */
- ret = -2;
- good = i;
- break;
- case -1:
- default:
- /* No PTE match */
- break;
- case 0:
- /* access granted */
- /* XXX: we should go on looping to check all PTEs consistency
- * but if we can speed-up the whole thing as the
- * result would be undefined if PTEs are not consistent.
- */
- ret = 0;
- good = i;
- goto done;
- }
- }
- if (good != -1) {
- done:
- LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
- ctx->raddr, ctx->prot, ret);
- /* Update page flags */
- pte1 = ctx->raddr;
- if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
-#if defined(TARGET_PPC64)
- if (is_64b) {
- if (env->external_htab) {
- stq_p(env->external_htab + pteg_off + (good * 16) + 8,
- pte1);
- } else {
- stq_phys_notdirty(env->htab_base + pteg_off +
- (good * 16) + 8, pte1);
- }
- } else
-#endif
- {
- if (env->external_htab) {
- stl_p(env->external_htab + pteg_off + (good * 8) + 4,
- pte1);
- } else {
- stl_phys_notdirty(env->htab_base + pteg_off +
- (good * 8) + 4, pte1);
- }
- }
- }
- }
-
- /* We have a TLB that saves 4K pages, so let's
- * split a huge page to 4k chunks */
- if (target_page_bits != TARGET_PAGE_BITS) {
- ctx->raddr |= (ctx->eaddr & ((1 << target_page_bits) - 1))
- & TARGET_PAGE_MASK;
- }
- return ret;
-}
-
-static inline int find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int h, int rw,
- int type, int target_page_bits)
-{
-#if defined(TARGET_PPC64)
- if (env->mmu_model & POWERPC_MMU_64) {
- return find_pte2(env, ctx, 1, h, rw, type, target_page_bits);
- }
-#endif
-
- return find_pte2(env, ctx, 0, h, rw, type, target_page_bits);
-}
-
-#if defined(TARGET_PPC64)
-static inline ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
-{
- uint64_t esid_256M, esid_1T;
- int n;
-
- LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
-
- esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
- esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
-
- for (n = 0; n < env->slb_nr; n++) {
- ppc_slb_t *slb = &env->slb[n];
-
- LOG_SLB("%s: slot %d %016" PRIx64 " %016"
- PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
- /* We check for 1T matches on all MMUs here - if the MMU
- * doesn't have 1T segment support, we will have prevented 1T
- * entries from being inserted in the slbmte code. */
- if (((slb->esid == esid_256M) &&
- ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
- || ((slb->esid == esid_1T) &&
- ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
- return slb;
- }
- }
-
- return NULL;
-}
-
-/*****************************************************************************/
-/* SPR accesses */
-
-void helper_slbia(CPUPPCState *env)
-{
- int n, do_invalidate;
-
- do_invalidate = 0;
- /* XXX: Warning: slbia never invalidates the first segment */
- for (n = 1; n < env->slb_nr; n++) {
- ppc_slb_t *slb = &env->slb[n];
-
- if (slb->esid & SLB_ESID_V) {
- slb->esid &= ~SLB_ESID_V;
- /* XXX: given the fact that segment size is 256 MB or 1TB,
- * and we still don't have a tlb_flush_mask(env, n, mask)
- * in QEMU, we just invalidate all TLBs
- */
- do_invalidate = 1;
- }
- }
- if (do_invalidate) {
- tlb_flush(env, 1);
- }
-}
-
-void helper_slbie(CPUPPCState *env, target_ulong addr)
-{
- ppc_slb_t *slb;
-
- slb = slb_lookup(env, addr);
- if (!slb) {
- return;
- }
-
- if (slb->esid & SLB_ESID_V) {
- slb->esid &= ~SLB_ESID_V;
-
- /* XXX: given the fact that segment size is 256 MB or 1TB,
- * and we still don't have a tlb_flush_mask(env, n, mask)
- * in QEMU, we just invalidate all TLBs
- */
- tlb_flush(env, 1);
- }
-}
-
-int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
-{
- int slot = rb & 0xfff;
- ppc_slb_t *slb = &env->slb[slot];
-
- if (rb & (0x1000 - env->slb_nr)) {
- return -1; /* Reserved bits set or slot too high */
- }
- if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
- return -1; /* Bad segment size */
- }
- if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
- return -1; /* 1T segment on MMU that doesn't support it */
- }
-
- /* Mask out the slot number as we store the entry */
- slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
- slb->vsid = rs;
-
- LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
- " %016" PRIx64 "\n", __func__, slot, rb, rs,
- slb->esid, slb->vsid);
-
- return 0;
-}
-
-static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
- target_ulong *rt)
-{
- int slot = rb & 0xfff;
- ppc_slb_t *slb = &env->slb[slot];
-
- if (slot >= env->slb_nr) {
- return -1;
- }
-
- *rt = slb->esid;
- return 0;
-}
-
-static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
- target_ulong *rt)
-{
- int slot = rb & 0xfff;
- ppc_slb_t *slb = &env->slb[slot];
-
- if (slot >= env->slb_nr) {
- return -1;
- }
-
- *rt = slb->vsid;
- return 0;
-}
-#endif /* defined(TARGET_PPC64) */
-
/* Perform segment based translation */
-static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
hwaddr hash;
target_ulong vsid;
int ds, pr, target_page_bits;
- int ret, ret2;
+ int ret;
+ target_ulong sr, pgidx;
pr = msr_pr;
ctx->eaddr = eaddr;
-#if defined(TARGET_PPC64)
- if (env->mmu_model & POWERPC_MMU_64) {
- ppc_slb_t *slb;
- target_ulong pageaddr;
- int segment_bits;
- LOG_MMU("Check SLBs\n");
- slb = slb_lookup(env, eaddr);
- if (!slb) {
- return -5;
- }
+ sr = env->sr[eaddr >> 28];
+ ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
+ ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
+ ds = sr & 0x80000000 ? 1 : 0;
+ ctx->nx = sr & 0x10000000 ? 1 : 0;
+ vsid = sr & 0x00FFFFFF;
+ target_page_bits = TARGET_PAGE_BITS;
+ LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
+ TARGET_FMT_lx " lr=" TARGET_FMT_lx
+ " ir=%d dr=%d pr=%d %d t=%d\n",
+ eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
+ (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
+ pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
+ hash = vsid ^ pgidx;
+ ctx->ptem = (vsid << 7) | (pgidx >> 10);
- if (slb->vsid & SLB_VSID_B) {
- vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
- segment_bits = 40;
- } else {
- vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
- segment_bits = 28;
- }
-
- target_page_bits = (slb->vsid & SLB_VSID_L)
- ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
- ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
- : (slb->vsid & SLB_VSID_KS));
- ds = 0;
- ctx->nx = !!(slb->vsid & SLB_VSID_N);
-
- pageaddr = eaddr & ((1ULL << segment_bits)
- - (1ULL << target_page_bits));
- if (slb->vsid & SLB_VSID_B) {
- hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
- } else {
- hash = vsid ^ (pageaddr >> target_page_bits);
- }
- /* Only 5 bits of the page index are used in the AVPN */
- ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
- ((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- target_ulong sr, pgidx;
-
- sr = env->sr[eaddr >> 28];
- ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
- ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
- ds = sr & 0x80000000 ? 1 : 0;
- ctx->nx = sr & 0x10000000 ? 1 : 0;
- vsid = sr & 0x00FFFFFF;
- target_page_bits = TARGET_PAGE_BITS;
- LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
- TARGET_FMT_lx " lr=" TARGET_FMT_lx
- " ir=%d dr=%d pr=%d %d t=%d\n",
- eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
- (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
- pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
- hash = vsid ^ pgidx;
- ctx->ptem = (vsid << 7) | (pgidx >> 10);
- }
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
ctx->key, ds, ctx->nx, vsid);
ret = -1;
@@ -897,33 +501,8 @@
/* Initialize real address with an invalid value */
ctx->raddr = (hwaddr)-1ULL;
- if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
- env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
- /* Software TLB search */
- ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
- } else {
- LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
- " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n",
- env->htab_base, env->htab_mask, vsid, ctx->ptem,
- ctx->hash[0]);
- /* Primary table lookup */
- ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
- if (ret < 0) {
- /* Secondary table lookup */
- if (eaddr != 0xEFFFFFFF) {
- LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
- " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n", env->htab_base,
- env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
- }
- ret2 = find_pte(env, ctx, 1, rw, type,
- target_page_bits);
- if (ret2 != -1) {
- ret = ret2;
- }
- }
- }
+ /* Software TLB search */
+ ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
#if defined(DUMP_PAGE_TABLES)
if (qemu_log_enabled()) {
hwaddr curaddr;
@@ -1309,8 +888,8 @@
}
/* TLB check function for MAS based SoftTLBs */
-int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
- hwaddr *raddrp,
+static int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
+ hwaddr *raddrp,
target_ulong address, uint32_t pid)
{
target_ulong mask;
@@ -1597,28 +1176,6 @@
}
}
-#if defined(TARGET_PPC64)
-static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
- CPUPPCState *env)
-{
- int i;
- uint64_t slbe, slbv;
-
- cpu_synchronize_state(env);
-
- cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
- for (i = 0; i < env->slb_nr; i++) {
- slbe = env->slb[i].esid;
- slbv = env->slb[i].vsid;
- if (slbe == 0 && slbv == 0) {
- continue;
- }
- cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
- i, slbe, slbv);
- }
-}
-#endif
-
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
{
switch (env->mmu_model) {
@@ -1632,7 +1189,7 @@
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_06d:
- mmubooks_dump_mmu(f, cpu_fprintf, env);
+ dump_slb(f, cpu_fprintf, env);
break;
#endif
default:
@@ -1649,8 +1206,6 @@
ctx->prot = PAGE_READ | PAGE_EXEC;
ret = 0;
switch (env->mmu_model) {
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
case POWERPC_MMU_SOFT_4xx:
@@ -1658,16 +1213,7 @@
case POWERPC_MMU_BOOKE:
ctx->prot |= PAGE_WRITE;
break;
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06d:
- /* Real address are 60 bits long */
- ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
- ctx->prot |= PAGE_WRITE;
- break;
-#endif
+
case POWERPC_MMU_SOFT_4xx_Z:
if (unlikely(msr_pe != 0)) {
/* 403 family add some particular protections,
@@ -1692,15 +1238,10 @@
}
}
break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
- break;
- case POWERPC_MMU_BOOKE206:
- cpu_abort(env, "BookE 2.06 MMU doesn't have physical real mode\n");
- break;
+
default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
+ /* Caller's checks mean we should never get here for other models */
+ abort();
return -1;
}
@@ -1710,71 +1251,62 @@
static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int access_type)
{
- int ret;
+ int ret = -1;
+ bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
+ || (access_type != ACCESS_CODE && msr_dr == 0);
#if 0
qemu_log("%s\n", __func__);
#endif
- if ((access_type == ACCESS_CODE && msr_ir == 0) ||
- (access_type != ACCESS_CODE && msr_dr == 0)) {
- if (env->mmu_model == POWERPC_MMU_BOOKE) {
- /* The BookE MMU always performs address translation. The
- IS and DS bits only affect the address space. */
- ret = mmubooke_get_physical_address(env, ctx, eaddr,
- rw, access_type);
- } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
- ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
- access_type);
- } else {
- /* No address translation. */
+
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_6xx:
+ case POWERPC_MMU_SOFT_74xx:
+ if (real_mode) {
ret = check_physical(env, ctx, eaddr, rw);
- }
- } else {
- ret = -1;
- switch (env->mmu_model) {
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
- case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
+ } else {
/* Try to find a BAT */
if (env->nb_BATs != 0) {
- ret = get_bat(env, ctx, eaddr, rw, access_type);
+ ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, access_type);
}
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06d:
-#endif
if (ret < 0) {
/* We didn't match any BAT entry or don't have BATs */
- ret = get_segment(env, ctx, eaddr, rw, access_type);
+ ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type);
}
- break;
- case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
+ }
+ break;
+
+ case POWERPC_MMU_SOFT_4xx:
+ case POWERPC_MMU_SOFT_4xx_Z:
+ if (real_mode) {
+ ret = check_physical(env, ctx, eaddr, rw);
+ } else {
ret = mmu40x_get_physical_address(env, ctx, eaddr,
rw, access_type);
- break;
- case POWERPC_MMU_BOOKE:
- ret = mmubooke_get_physical_address(env, ctx, eaddr,
- rw, access_type);
- break;
- case POWERPC_MMU_BOOKE206:
- ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
- access_type);
- break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
- break;
- case POWERPC_MMU_REAL:
- cpu_abort(env, "PowerPC in real mode do not do any translation\n");
- return -1;
- default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
- return -1;
}
+ break;
+ case POWERPC_MMU_BOOKE:
+ ret = mmubooke_get_physical_address(env, ctx, eaddr,
+ rw, access_type);
+ break;
+ case POWERPC_MMU_BOOKE206:
+ ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
+ access_type);
+ break;
+ case POWERPC_MMU_MPC8xx:
+ /* XXX: TODO */
+ cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ break;
+ case POWERPC_MMU_REAL:
+ if (real_mode) {
+ ret = check_physical(env, ctx, eaddr, rw);
+ } else {
+ cpu_abort(env, "PowerPC in real mode do not do any translation\n");
+ }
+ return -1;
+ default:
+ cpu_abort(env, "Unknown or invalid MMU model\n");
+ return -1;
}
#if 0
qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
@@ -1788,6 +1320,22 @@
{
mmu_ctx_t ctx;
+ switch (env->mmu_model) {
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06d:
+ return ppc_hash64_get_phys_page_debug(env, addr);
+#endif
+
+ case POWERPC_MMU_32B:
+ case POWERPC_MMU_601:
+ return ppc_hash32_get_phys_page_debug(env, addr);
+
+ default:
+ ;
+ }
+
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) {
return -1;
}
@@ -1836,8 +1384,8 @@
}
/* Perform address translation */
-int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
- int mmu_idx)
+static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
+ int rw, int mmu_idx)
{
mmu_ctx_t ctx;
int access_type;
@@ -1880,17 +1428,6 @@
env->spr[SPR_40x_DEAR] = address;
env->spr[SPR_40x_ESR] = 0x00000000;
break;
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06d:
-#endif
- env->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0x40000000;
- break;
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, address, rw);
/* fall through */
@@ -1932,19 +1469,6 @@
env->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
break;
-#if defined(TARGET_PPC64)
- case -5:
- /* No match in segment table */
- if (env->mmu_model == POWERPC_MMU_620) {
- env->exception_index = POWERPC_EXCP_ISI;
- /* XXX: this might be incorrect */
- env->error_code = 0x40000000;
- } else {
- env->exception_index = POWERPC_EXCP_ISEG;
- env->error_code = 0;
- }
- break;
-#endif
}
} else {
switch (ret) {
@@ -1964,9 +1488,9 @@
tlb_miss:
env->error_code |= ctx.key << 19;
env->spr[SPR_HASH1] = env->htab_base +
- get_pteg_offset(env, ctx.hash[0], HASH_PTE_SIZE_32);
+ get_pteg_offset32(env, ctx.hash[0]);
env->spr[SPR_HASH2] = env->htab_base +
- get_pteg_offset(env, ctx.hash[1], HASH_PTE_SIZE_32);
+ get_pteg_offset32(env, ctx.hash[1]);
break;
case POWERPC_MMU_SOFT_74xx:
if (rw == 1) {
@@ -1992,23 +1516,6 @@
env->spr[SPR_40x_ESR] = 0x00000000;
}
break;
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06d:
-#endif
- env->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = address;
- if (rw == 1) {
- env->spr[SPR_DSISR] = 0x42000000;
- } else {
- env->spr[SPR_DSISR] = 0x40000000;
- }
- break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
@@ -2094,26 +1601,6 @@
break;
}
break;
-#if defined(TARGET_PPC64)
- case -5:
- /* No match in segment table */
- if (env->mmu_model == POWERPC_MMU_620) {
- env->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = address;
- /* XXX: this might be incorrect */
- if (rw == 1) {
- env->spr[SPR_DSISR] = 0x42000000;
- } else {
- env->spr[SPR_DSISR] = 0x40000000;
- }
- } else {
- env->exception_index = POWERPC_EXCP_DSEG;
- env->error_code = 0;
- env->spr[SPR_DAR] = address;
- }
- break;
-#endif
}
}
#if 0
@@ -2326,7 +1813,6 @@
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_06d:
@@ -2396,7 +1882,6 @@
tlb_flush_page(env, addr | (0xF << 28));
break;
#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_06d:
@@ -2420,16 +1905,6 @@
/*****************************************************************************/
/* Special registers manipulation */
-#if defined(TARGET_PPC64)
-void ppc_store_asr(CPUPPCState *env, target_ulong value)
-{
- if (env->asr != value) {
- env->asr = value;
- tlb_flush(env, 1);
- }
-}
-#endif
-
void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
@@ -2511,41 +1986,6 @@
#endif
}
}
-#endif /* !defined(CONFIG_USER_ONLY) */
-
-#if !defined(CONFIG_USER_ONLY)
-/* SLB management */
-#if defined(TARGET_PPC64)
-void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
-{
- if (ppc_store_slb(env, rb, rs) < 0) {
- helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL);
- }
-}
-
-target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
-{
- target_ulong rt = 0;
-
- if (ppc_load_slb_esid(env, rb, &rt) < 0) {
- helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL);
- }
- return rt;
-}
-
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
-{
- target_ulong rt = 0;
-
- if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
- helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL);
- }
- return rt;
-}
-#endif /* defined(TARGET_PPC64) */
/* TLB management */
void helper_tlbia(CPUPPCState *env)
@@ -3321,4 +2761,45 @@
booke206_flush_tlb(env, flags, 1);
}
-#endif
+
+
+/*****************************************************************************/
+
+#define MMUSUFFIX _mmu
+
+#define SHIFT 0
+#include "exec/softmmu_template.h"
+
+#define SHIFT 1
+#include "exec/softmmu_template.h"
+
+#define SHIFT 2
+#include "exec/softmmu_template.h"
+
+#define SHIFT 3
+#include "exec/softmmu_template.h"
+
+/* try to fill the TLB and return an exception if error. If retaddr is
+ NULL, it means that the function was called in C code (i.e. not
+ from generated code or from helper.c) */
+/* XXX: fix it to restore all registers */
+void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
+ uintptr_t retaddr)
+{
+ CPUState *cpu = ENV_GET_CPU(env);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ int ret;
+
+ if (pcc->handle_mmu_fault) {
+ ret = pcc->handle_mmu_fault(env, addr, is_write, mmu_idx);
+ } else {
+ ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ }
+ if (unlikely(ret != 0)) {
+ if (likely(retaddr)) {
+ /* now we have a real cpu fault */
+ cpu_restore_state(env, retaddr);
+ }
+ helper_raise_exception_err(env, env->exception_index, env->error_code);
+ }
+}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 380a884..5e741d1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -204,6 +204,13 @@
int singlestep_enabled;
} DisasContext;
+/* True when active word size < size of target_long. */
+#ifdef TARGET_PPC64
+# define NARROW_MODE(C) (!(C)->sf_mode)
+#else
+# define NARROW_MODE(C) 0
+#endif
+
struct opc_handler_t {
/* invalid bits for instruction 1 (Rc(opcode) == 0) */
uint32_t inval1;
@@ -260,12 +267,10 @@
static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
{
-#if defined(TARGET_PPC64)
- if (ctx->sf_mode)
- tcg_gen_movi_tl(cpu_nip, nip);
- else
-#endif
- tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
+ if (NARROW_MODE(ctx)) {
+ nip = (uint32_t)nip;
+ }
+ tcg_gen_movi_tl(cpu_nip, nip);
}
static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
@@ -627,7 +632,6 @@
tcg_temp_free(t0);
}
-#if defined(TARGET_PPC64)
static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0, t1;
@@ -651,68 +655,62 @@
gen_op_cmp32(arg0, t0, s, crf);
tcg_temp_free(t0);
}
-#endif
static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
{
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode))
+ if (NARROW_MODE(ctx)) {
gen_op_cmpi32(reg, 0, 1, 0);
- else
-#endif
+ } else {
gen_op_cmpi(reg, 0, 1, 0);
+ }
}
/* cmp */
static void gen_cmp(DisasContext *ctx)
{
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
+ if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1, crfD(ctx->opcode));
- else
-#endif
+ } else {
gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1, crfD(ctx->opcode));
+ }
}
/* cmpi */
static void gen_cmpi(DisasContext *ctx)
{
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
+ if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1, crfD(ctx->opcode));
- else
-#endif
+ } else {
gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1, crfD(ctx->opcode));
+ }
}
/* cmpl */
static void gen_cmpl(DisasContext *ctx)
{
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
+ if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
0, crfD(ctx->opcode));
- else
-#endif
+ } else {
gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
0, crfD(ctx->opcode));
+ }
}
/* cmpli */
static void gen_cmpli(DisasContext *ctx)
{
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
+ if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
0, crfD(ctx->opcode));
- else
-#endif
+ } else {
gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
0, crfD(ctx->opcode));
+ }
}
/* isel (PowerPC 2.03 specification) */
@@ -756,11 +754,9 @@
tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
}
tcg_temp_free(t0);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
}
-#endif
tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
@@ -778,14 +774,26 @@
}
if (compute_ca) {
- TCGv zero = tcg_const_tl(0);
- if (add_ca) {
- tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
- tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
+ if (NARROW_MODE(ctx)) {
+ TCGv t1 = tcg_temp_new();
+ tcg_gen_ext32u_tl(t1, arg2);
+ tcg_gen_ext32u_tl(t0, arg1);
+ tcg_gen_add_tl(t0, t0, t1);
+ tcg_temp_free(t1);
+ if (add_ca) {
+ tcg_gen_add_tl(t0, t0, cpu_ca);
+ }
+ tcg_gen_shri_tl(cpu_ca, t0, 32);
} else {
- tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
+ TCGv zero = tcg_const_tl(0);
+ if (add_ca) {
+ tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
+ tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
+ } else {
+ tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
+ }
+ tcg_temp_free(zero);
}
- tcg_temp_free(zero);
} else {
tcg_gen_add_tl(t0, arg1, arg2);
if (add_ca) {
@@ -1114,14 +1122,25 @@
{
TCGv t0 = ret;
- if (((add_ca && compute_ca) || compute_ov)
- && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
+ if (compute_ov && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
t0 = tcg_temp_new();
}
- if (add_ca) {
- /* dest = ~arg1 + arg2 + ca. */
- if (compute_ca) {
+ if (compute_ca) {
+ /* dest = ~arg1 + arg2 [+ ca]. */
+ if (NARROW_MODE(ctx)) {
+ TCGv inv1 = tcg_temp_new();
+ tcg_gen_not_tl(inv1, arg1);
+ tcg_gen_ext32u_tl(t0, arg2);
+ tcg_gen_ext32u_tl(inv1, inv1);
+ if (add_ca) {
+ tcg_gen_add_tl(t0, t0, cpu_ca);
+ } else {
+ tcg_gen_addi_tl(t0, t0, 1);
+ }
+ tcg_gen_add_tl(t0, t0, inv1);
+ tcg_gen_shri_tl(cpu_ca, t0, 32);
+ } else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
zero = tcg_const_tl(0);
@@ -1130,14 +1149,16 @@
tcg_temp_free(zero);
tcg_temp_free(inv1);
} else {
- tcg_gen_sub_tl(t0, arg2, arg1);
- tcg_gen_add_tl(t0, t0, cpu_ca);
- tcg_gen_subi_tl(t0, t0, 1);
- }
- } else {
- if (compute_ca) {
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
+ tcg_gen_sub_tl(t0, arg2, arg1);
}
+ } else if (add_ca) {
+ /* Since we're ignoring carry-out, we can simplify the
+ standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
+ tcg_gen_sub_tl(t0, arg2, arg1);
+ tcg_gen_add_tl(t0, t0, cpu_ca);
+ tcg_gen_subi_tl(t0, t0, 1);
+ } else {
tcg_gen_sub_tl(t0, arg2, arg1);
}
@@ -2311,45 +2332,37 @@
simm &= ~maskl;
if (rA(ctx->opcode) == 0) {
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
- tcg_gen_movi_tl(EA, (uint32_t)simm);
- } else
-#endif
+ if (NARROW_MODE(ctx)) {
+ simm = (uint32_t)simm;
+ }
tcg_gen_movi_tl(EA, simm);
} else if (likely(simm != 0)) {
tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(EA, EA);
}
-#endif
} else {
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
- } else
-#endif
- tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
+ } else {
+ tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
+ }
}
}
static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
{
if (rA(ctx->opcode) == 0) {
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
- } else
-#endif
- tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
+ } else {
+ tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
+ }
} else {
tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(EA, EA);
}
-#endif
}
}
@@ -2357,13 +2370,10 @@
{
if (rA(ctx->opcode) == 0) {
tcg_gen_movi_tl(EA, 0);
+ } else if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
} else {
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
- tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
- } else
-#endif
- tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
}
}
@@ -2371,11 +2381,9 @@
target_long val)
{
tcg_gen_addi_tl(ret, arg1, val);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(ret, ret);
}
-#endif
}
static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
@@ -3320,10 +3328,9 @@
{
TranslationBlock *tb;
tb = ctx->tb;
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode)
+ if (NARROW_MODE(ctx)) {
dest = (uint32_t) dest;
-#endif
+ }
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
likely(!ctx->singlestep_enabled)) {
tcg_gen_goto_tb(n);
@@ -3351,12 +3358,10 @@
static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
{
-#if defined(TARGET_PPC64)
- if (ctx->sf_mode == 0)
- tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
- else
-#endif
- tcg_gen_movi_tl(cpu_lr, nip);
+ if (NARROW_MODE(ctx)) {
+ nip = (uint32_t)nip;
+ }
+ tcg_gen_movi_tl(cpu_lr, nip);
}
/* b ba bl bla */
@@ -3366,18 +3371,16 @@
ctx->exception = POWERPC_EXCP_BRANCH;
/* sign extend LI */
-#if defined(TARGET_PPC64)
- if (ctx->sf_mode)
- li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
- else
-#endif
- li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
- if (likely(AA(ctx->opcode) == 0))
+ li = LI(ctx->opcode);
+ li = (li ^ 0x02000000) - 0x02000000;
+ if (likely(AA(ctx->opcode) == 0)) {
target = ctx->nip + li - 4;
- else
+ } else {
target = li;
- if (LK(ctx->opcode))
+ }
+ if (LK(ctx->opcode)) {
gen_setlr(ctx, ctx->nip);
+ }
gen_update_cfar(ctx, ctx->nip);
gen_goto_tb(ctx, 0, target);
}
@@ -3413,12 +3416,11 @@
return;
}
tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode)
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(temp, cpu_ctr);
- else
-#endif
+ } else {
tcg_gen_mov_tl(temp, cpu_ctr);
+ }
if (bo & 0x2) {
tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
} else {
@@ -3452,20 +3454,14 @@
gen_set_label(l1);
gen_goto_tb(ctx, 1, ctx->nip);
} else {
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode))
+ if (NARROW_MODE(ctx)) {
tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
- else
-#endif
+ } else {
tcg_gen_andi_tl(cpu_nip, target, ~3);
+ }
tcg_gen_exit_tb(0);
gen_set_label(l1);
-#if defined(TARGET_PPC64)
- if (!(ctx->sf_mode))
- tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
- else
-#endif
- tcg_gen_movi_tl(cpu_nip, ctx->nip);
+ gen_update_nip(ctx, ctx->nip);
tcg_gen_exit_tb(0);
}
}
@@ -4324,15 +4320,14 @@
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
return;
}
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
TCGv t0 = tcg_temp_new();
tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
gen_helper_tlbie(cpu_env, t0);
tcg_temp_free(t0);
- } else
-#endif
+ } else {
gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ }
#endif
}
@@ -7577,11 +7572,9 @@
tcg_gen_movi_tl(EA, uimm << sh);
} else {
tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
-#if defined(TARGET_PPC64)
- if (!ctx->sf_mode) {
+ if (NARROW_MODE(ctx)) {
tcg_gen_ext32u_tl(EA, EA);
}
-#endif
}
}
@@ -9428,7 +9421,6 @@
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
#if defined(TARGET_PPC64)
- case POWERPC_MMU_620:
case POWERPC_MMU_64B:
#endif
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 15eebe9..781170f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -25,6 +25,8 @@
#include "sysemu/arch_init.h"
#include "sysemu/cpus.h"
#include "cpu-models.h"
+#include "mmu-hash32.h"
+#include "mmu-hash64.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
@@ -365,7 +367,6 @@
}
/* 64 bits PowerPC specific SPRs */
-/* ASR */
#if defined(TARGET_PPC64)
static void spr_read_hior (void *opaque, int gprn, int sprn)
{
@@ -379,16 +380,6 @@
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
tcg_temp_free(t0);
}
-
-static void spr_read_asr (void *opaque, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
-}
-
-static void spr_write_asr (void *opaque, int sprn, int gprn)
-{
- gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
-}
#endif
#endif
@@ -1028,6 +1019,54 @@
0x00000000);
}
+#ifdef TARGET_PPC64
+#ifndef CONFIG_USER_ONLY
+static void spr_read_uamr (void *opaque, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], SPR_AMR);
+ spr_load_dump_spr(SPR_AMR);
+}
+
+static void spr_write_uamr (void *opaque, int sprn, int gprn)
+{
+ gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
+ spr_store_dump_spr(SPR_AMR);
+}
+
+static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ gen_load_spr(t0, SPR_UAMOR);
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ gen_store_spr(SPR_AMR, t0);
+ spr_store_dump_spr(SPR_AMR);
+}
+#endif /* CONFIG_USER_ONLY */
+
+static void gen_spr_amr (CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ /* Virtual Page Class Key protection */
+ /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
+ * userspace accessible, 29 is privileged. So we only need to set
+ * the kvm ONE_REG id on one of them, we use 29 */
+ spr_register(env, SPR_UAMR, "UAMR",
+ &spr_read_uamr, &spr_write_uamr_pr,
+ &spr_read_uamr, &spr_write_uamr,
+ 0);
+ spr_register_kvm(env, SPR_AMR, "AMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
+ spr_register_kvm(env, SPR_UAMOR, "UAMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_UAMOR, 0);
+#endif /* !CONFIG_USER_ONLY */
+}
+#endif /* TARGET_PPC64 */
+
static void gen_spr_thrm (CPUPPCState *env)
{
/* Thermal management */
@@ -2151,173 +2190,6 @@
0x00000000);
}
-#if defined (TARGET_PPC64)
-/* SPR specific to PowerPC 620 */
-static void gen_spr_620 (CPUPPCState *env)
-{
- /* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- spr_register(env, SPR_ASR, "ASR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_asr, &spr_write_asr,
- 0x00000000);
- /* Breakpoints */
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_SIAR, "SIAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_SDA, "SDA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMC1R, "PMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_620_PMC1W, "PMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMC2R, "PMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_620_PMC2W, "PMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_MMCR0R, "MMCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_620_MMCR0W, "MMCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#if 0 // XXX: check this
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR0, "PMR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR1, "PMR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR2, "PMR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR3, "PMR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR4, "PMR4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR5, "PMR5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR6, "PMR6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR7, "PMR7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR8, "PMR8",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMR9, "PMR9",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMRA, "PMR10",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMRB, "PMR11",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMRC, "PMR12",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMRD, "PMR13",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMRE, "PMR14",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_PMRF, "PMR15",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
- /* XXX : not implemented */
- spr_register(env, SPR_620_BUSCSR, "BUSCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_620_L2SR, "L2SR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-#endif /* defined (TARGET_PPC64) */
-
static void gen_spr_5xx_8xx (CPUPPCState *env)
{
/* Exception processing */
@@ -2993,31 +2865,6 @@
#endif
}
-#if defined(TARGET_PPC64)
-static void init_excp_620 (CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
- env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
- env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
- env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->hreset_excp_prefix = 0xFFF00000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0x0000000000000100ULL;
-#endif
-}
-#endif /* defined(TARGET_PPC64) */
-
static void init_excp_7x0 (CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -4951,6 +4798,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000000FD70ULL;
pcc->mmu_model = POWERPC_MMU_601;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_601;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_601;
@@ -4985,7 +4835,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000000FD70ULL;
pcc->mmu_model = POWERPC_MMU_601;
- pcc->excp_model = POWERPC_EXCP_601;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_601;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
@@ -5192,6 +5044,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_604;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_604;
@@ -5258,6 +5113,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_604;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_604;
@@ -5311,6 +5169,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_7x0;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
@@ -5372,6 +5233,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_7x0;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
@@ -5556,6 +5420,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_7x0;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
@@ -5621,6 +5488,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_7x0;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
@@ -5691,6 +5561,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_7x0;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
@@ -5761,6 +5634,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_7x0;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_750;
@@ -5953,6 +5829,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6019,6 +5898,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6725,6 +6607,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x900000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
pcc->bfd_mach = bfd_mach_ppc64;
@@ -6835,6 +6720,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
pcc->bfd_mach = bfd_mach_ppc64;
@@ -6933,6 +6821,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
pcc->bfd_mach = bfd_mach_ppc64;
@@ -7031,6 +6922,9 @@
pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x900000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
pcc->bfd_mach = bfd_mach_ppc64;
@@ -7075,6 +6969,7 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000); /* TOFIX */
+ gen_spr_amr(env);
/* XXX : not implemented */
spr_register(env, SPR_CTRL, "SPR_CTRLT",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7122,6 +7017,9 @@
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
+#if defined(CONFIG_SOFTMMU)
+ pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
pcc->bfd_mach = bfd_mach_ppc64;
@@ -7129,55 +7027,6 @@
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
}
-
-static void init_proc_620 (CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_620(env);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- gen_low_BATs(env);
- init_excp_620(env);
- env->dcache_line_size = 64;
- env->icache_line_size = 64;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env);
-}
-
-POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 620";
- pcc->init_proc = init_proc_620;
- pcc->check_pow = check_pow_nocheck; /* Check this */
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_SEGMENT | PPC_EXTERN |
- PPC_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC_NONE;
- pcc->msr_mask = 0x800000000005FF77ULL;
- pcc->mmu_model = POWERPC_MMU_620;
- pcc->excp_model = POWERPC_EXCP_970;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
- POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
-}
-
#endif /* defined (TARGET_PPC64) */
@@ -7693,7 +7542,7 @@
return 8;
}
if (n == 32) {
- /* FPSCR not implemented */
+ helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
return 4;
}
return 0;
@@ -7915,9 +7764,6 @@
case POWERPC_MMU_64B:
mmu_model = "PowerPC 64";
break;
- case POWERPC_MMU_620:
- mmu_model = "PowerPC 620";
- break;
#endif
default:
mmu_model = "Unknown or invalid";
diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c
new file mode 100644
index 0000000..56e686e
--- /dev/null
+++ b/target-ppc/user_only_helper.c
@@ -0,0 +1,44 @@
+/*
+ * PowerPC MMU stub handling for user mode emulation
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright (c) 2013 David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+
+int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+ int mmu_idx)
+{
+ int exception, error_code;
+
+ if (rw == 2) {
+ exception = POWERPC_EXCP_ISI;
+ error_code = 0x40000000;
+ } else {
+ exception = POWERPC_EXCP_DSI;
+ error_code = 0x40000000;
+ if (rw) {
+ error_code |= 0x02000000;
+ }
+ env->spr[SPR_DAR] = address;
+ env->spr[SPR_DSISR] = error_code;
+ }
+ env->exception_index = exception;
+ env->error_code = error_code;
+
+ return 1;
+}
diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c
index 8f111ae..644f484 100644
--- a/target-s390x/kvm.c
+++ b/target-s390x/kvm.c
@@ -315,8 +315,7 @@
int kvm_arch_process_async_events(CPUState *cs)
{
- S390CPU *cpu = S390_CPU(cs);
- return cpu->env.halted;
+ return cs->halted;
}
void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 88e481c..a4f2194 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1142,7 +1142,7 @@
};
/* ====================================================================== */
-/* Miscelaneous helpers, used by several operations. */
+/* Miscellaneous helpers, used by several operations. */
static void help_l2_shift(DisasContext *s, DisasFields *f,
DisasOps *o, int mask)
diff --git a/tcg/README b/tcg/README
index 934e7af..063aeb9 100644
--- a/tcg/README
+++ b/tcg/README
@@ -14,6 +14,10 @@
for cross compiling, it is assumed that the TCG target is different
from the host, although it is never the case for QEMU.
+In this document, we use "guest" to specify what architecture we are
+emulating; "target" always means the TCG target, the machine on which
+we are running QEMU.
+
A TCG "function" corresponds to a QEMU Translated Block (TB).
A TCG "temporary" is a variable only live in a basic
@@ -379,7 +383,7 @@
Similar to mulu2, except the two inputs T1 and T2 are signed.
-********* 64-bit target on 32-bit host support
+********* 64-bit guest on 32-bit host support
The following opcodes are internal to TCG. Thus they are to be implemented by
32-bit host code generators, but are not to be emitted by guest translators.
@@ -521,9 +525,9 @@
a better generated code, but it reduces the memory usage of TCG and
the speed of the translation.
-- Don't hesitate to use helpers for complicated or seldom used target
+- Don't hesitate to use helpers for complicated or seldom used guest
instructions. There is little performance advantage in using TCG to
- implement target instructions taking more than about twenty TCG
+ implement guest instructions taking more than about twenty TCG
instructions. Note that this rule of thumb is more applicable to
helpers doing complex logic or arithmetic, where the C compiler has
scope to do a good job of optimisation; it is less relevant where
@@ -531,9 +535,9 @@
inline TCG may still be faster for longer sequences.
- The hard limit on the number of TCG instructions you can generate
- per target instruction is set by MAX_OP_PER_INSTR in exec-all.h --
+ per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h --
you cannot exceed this without risking a buffer overrun.
- Use the 'discard' instruction if you know that TCG won't be able to
prove that a given global is "dead" at a given program point. The
- x86 target uses it to improve the condition codes optimisation.
+ x86 guest uses it to improve the condition codes optimisation.
diff --git a/tcg/optimize.c b/tcg/optimize.c
index bc6e5c1..1b6644c 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -576,7 +576,8 @@
break;
}
- /* Simplify expressions for "shift/rot r, 0, a => movi r, 0" */
+ /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
+ and "sub r, 0, a => neg r, a" case. */
switch (op) {
CASE_OP_32_64(shl):
CASE_OP_32_64(shr):
@@ -592,6 +593,37 @@
continue;
}
break;
+ CASE_OP_32_64(sub):
+ {
+ TCGOpcode neg_op;
+ bool have_neg;
+
+ if (temps[args[2]].state == TCG_TEMP_CONST) {
+ /* Proceed with possible constant folding. */
+ break;
+ }
+ if (op == INDEX_op_sub_i32) {
+ neg_op = INDEX_op_neg_i32;
+ have_neg = TCG_TARGET_HAS_neg_i32;
+ } else {
+ neg_op = INDEX_op_neg_i64;
+ have_neg = TCG_TARGET_HAS_neg_i64;
+ }
+ if (!have_neg) {
+ break;
+ }
+ if (temps[args[1]].state == TCG_TEMP_CONST
+ && temps[args[1]].val == 0) {
+ s->gen_opc_buf[op_index] = neg_op;
+ reset_temp(args[0]);
+ gen_args[0] = args[0];
+ gen_args[1] = args[2];
+ args += 3;
+ gen_args += 2;
+ continue;
+ }
+ }
+ break;
default:
break;
}
diff --git a/tests/qemu-iotests/052 b/tests/qemu-iotests/052
new file mode 100755
index 0000000..14a5126
--- /dev/null
+++ b/tests/qemu-iotests/052
@@ -0,0 +1,61 @@
+#!/bin/bash
+#
+# Test bdrv_read/bdrv_write using BDRV_O_SNAPSHOT
+#
+# Copyright (C) 2013 Red Hat, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+# creator
+owner=stefanha@redhat.com
+
+seq=`basename $0`
+echo "QA output created by $seq"
+
+here=`pwd`
+tmp=/tmp/$$
+status=1 # failure is the default!
+
+_cleanup()
+{
+ _cleanup_test_img
+}
+trap "_cleanup; exit \$status" 0 1 2 3 15
+
+# get standard environment, filters and checks
+. ./common.rc
+. ./common.filter
+
+_supported_fmt generic
+_supported_proto generic
+_supported_os Linux
+
+
+size=128M
+_make_test_img $size
+
+echo
+echo "== reading whole image =="
+$QEMU_IO -s -c "read 0 $size" $TEST_IMG | _filter_qemu_io
+
+echo
+echo "== writing whole image does not modify image =="
+$QEMU_IO -s -c "write -P 0xa 0 $size" $TEST_IMG | _filter_qemu_io
+$QEMU_IO -c "read -P 0 0 $size" $TEST_IMG | _filter_qemu_io
+
+# success, all done
+echo "*** done"
+rm -f $seq.full
+status=0
diff --git a/tests/qemu-iotests/052.out b/tests/qemu-iotests/052.out
new file mode 100644
index 0000000..8617aa2
--- /dev/null
+++ b/tests/qemu-iotests/052.out
@@ -0,0 +1,13 @@
+QA output created by 052
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728
+
+== reading whole image ==
+read 134217728/134217728 bytes at offset 0
+128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+
+== writing whole image does not modify image ==
+wrote 134217728/134217728 bytes at offset 0
+128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+read 134217728/134217728 bytes at offset 0
+128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+*** done
diff --git a/tests/qemu-iotests/group b/tests/qemu-iotests/group
index 1d7e4f3..73c5966 100644
--- a/tests/qemu-iotests/group
+++ b/tests/qemu-iotests/group
@@ -57,3 +57,4 @@
048 img auto quick
049 rw auto
050 rw auto backing quick
+052 rw auto backing
diff --git a/tests/tcg/lm32/test_cmpgei.S b/tests/tcg/lm32/test_cmpgei.S
index 6a8870f..6e388a2 100644
--- a/tests/tcg/lm32/test_cmpgei.S
+++ b/tests/tcg/lm32/test_cmpgei.S
@@ -52,4 +52,19 @@
cmpgei r3, r3, 0
check_r3 1
+test_name CMPGEI_11
+mvi r1, 0
+cmpgei r3, r1, -32768
+check_r3 1
+
+test_name CMPGEI_12
+mvi r1, -1
+cmpgei r3, r1, -32768
+check_r3 1
+
+test_name CMPGEI_13
+mvi r1, -32768
+cmpgei r3, r1, -32768
+check_r3 1
+
end
diff --git a/tests/tcg/lm32/test_cmpgeui.S b/tests/tcg/lm32/test_cmpgeui.S
index b9d1755..3866d96 100644
--- a/tests/tcg/lm32/test_cmpgeui.S
+++ b/tests/tcg/lm32/test_cmpgeui.S
@@ -52,4 +52,19 @@
cmpgeui r3, r3, 0
check_r3 1
+test_name CMPGEUI_11
+mvi r1, 0
+cmpgeui r3, r1, 0x8000
+check_r3 0
+
+test_name CMPGEUI_12
+mvi r1, -1
+cmpgeui r3, r1, 0x8000
+check_r3 1
+
+test_name CMPGEUI_13
+ori r1, r0, 0x8000
+cmpgeui r3, r1, 0x8000
+check_r3 1
+
end
diff --git a/tests/tcg/lm32/test_cmpgi.S b/tests/tcg/lm32/test_cmpgi.S
index 1f622d2..21695f9 100644
--- a/tests/tcg/lm32/test_cmpgi.S
+++ b/tests/tcg/lm32/test_cmpgi.S
@@ -52,4 +52,19 @@
cmpgi r3, r3, 0
check_r3 0
+test_name CMPGI_11
+mvi r1, 0
+cmpgi r3, r1, -32768
+check_r3 1
+
+test_name CMPGI_12
+mvi r1, -1
+cmpgi r3, r1, -32768
+check_r3 1
+
+test_name CMPGI_13
+mvi r1, -32768
+cmpgi r3, r1, -32768
+check_r3 0
+
end
diff --git a/tests/tcg/lm32/test_cmpgui.S b/tests/tcg/lm32/test_cmpgui.S
index 759bb64..dd94001 100644
--- a/tests/tcg/lm32/test_cmpgui.S
+++ b/tests/tcg/lm32/test_cmpgui.S
@@ -35,7 +35,7 @@
test_name CMPGUI_7
mvi r1, -1
cmpgui r3, r1, 0xffff
-check_r3 0
+check_r3 1
test_name CMPGUI_8
mvi r3, 0
@@ -52,4 +52,19 @@
cmpgui r3, r3, 0
check_r3 0
+test_name CMPGUI_11
+mvi r1, 0
+cmpgui r3, r1, 0x8000
+check_r3 0
+
+test_name CMPGUI_12
+mvi r1, -1
+cmpgui r3, r1, 0x8000
+check_r3 1
+
+test_name CMPGUI_13
+ori r1, r0, 0x8000
+cmpgui r3, r1, 0x8000
+check_r3 0
+
end
diff --git a/tests/tcg/mips/mips32-dsp/extr_r_w.c b/tests/tcg/mips/mips32-dsp/extr_r_w.c
index 02e0224..489c193 100644
--- a/tests/tcg/mips/mips32-dsp/extr_r_w.c
+++ b/tests/tcg/mips/mips32-dsp/extr_r_w.c
@@ -67,5 +67,28 @@
assert(dsp == 0);
assert(result == rt);
+ /* Clear dspcontrol */
+ dsp = 0;
+ __asm
+ ("wrdsp %0\n\t"
+ :
+ : "r"(dsp)
+ );
+
+ ach = 0xFFFFFFFF;
+ acl = 0xFFFFFFFF;
+ result = 0;
+ __asm
+ ("mthi %2, $ac1\n\t"
+ "mtlo %3, $ac1\n\t"
+ "extr_r.w %0, $ac1, 0x1F\n\t"
+ "rddsp %1\n\t"
+ : "=r"(rt), "=r"(dsp)
+ : "r"(ach), "r"(acl)
+ );
+ dsp = (dsp >> 23) & 0x01;
+ assert(dsp == 0);
+ assert(result == rt);
+
return 0;
}
diff --git a/tests/tcg/mips/mips32-dsp/extr_rs_w.c b/tests/tcg/mips/mips32-dsp/extr_rs_w.c
index c3a22ee..f9d2ed6 100644
--- a/tests/tcg/mips/mips32-dsp/extr_rs_w.c
+++ b/tests/tcg/mips/mips32-dsp/extr_rs_w.c
@@ -67,5 +67,51 @@
assert(dsp == 0);
assert(result == rt);
+ /* Clear dspcontrol */
+ dsp = 0;
+ __asm
+ ("wrdsp %0\n\t"
+ :
+ : "r"(dsp)
+ );
+
+ ach = 0x80000000;
+ acl = 0x00000000;
+ result = 0x80000000;
+ __asm
+ ("mthi %2, $ac1\n\t"
+ "mtlo %3, $ac1\n\t"
+ "extr_rs.w %0, $ac1, 0x1F\n\t"
+ "rddsp %1\n\t"
+ : "=r"(rt), "=r"(dsp)
+ : "r"(ach), "r"(acl)
+ );
+ dsp = (dsp >> 23) & 0x01;
+ assert(dsp == 1);
+ assert(result == rt);
+
+ /* Clear dspcontrol */
+ dsp = 0;
+ __asm
+ ("wrdsp %0\n\t"
+ :
+ : "r"(dsp)
+ );
+
+ ach = 0xFFFFFFFF;
+ acl = 0xFFFFFFFF;
+ result = 0;
+ __asm
+ ("mthi %2, $ac1\n\t"
+ "mtlo %3, $ac1\n\t"
+ "extr_rs.w %0, $ac1, 0x1F\n\t"
+ "rddsp %1\n\t"
+ : "=r"(rt), "=r"(dsp)
+ : "r"(ach), "r"(acl)
+ );
+ dsp = (dsp >> 23) & 0x01;
+ assert(dsp == 0);
+ assert(result == rt);
+
return 0;
}
diff --git a/tests/tcg/mips/mips32-dsp/extr_w.c b/tests/tcg/mips/mips32-dsp/extr_w.c
index bd6b0b9..cf92614 100644
--- a/tests/tcg/mips/mips32-dsp/extr_w.c
+++ b/tests/tcg/mips/mips32-dsp/extr_w.c
@@ -67,5 +67,28 @@
assert(dsp == 0);
assert(result == rt);
+ /* Clear dspcontrol */
+ dsp = 0;
+ __asm
+ ("wrdsp %0\n\t"
+ :
+ : "r"(dsp)
+ );
+
+ ach = 0xFFFFFFFF;
+ acl = 0xFFFFFFFF;
+ result = 0xFFFFFFFF;
+ __asm
+ ("mthi %2, $ac1\n\t"
+ "mtlo %3, $ac1\n\t"
+ "extr.w %0, $ac1, 0x1F\n\t"
+ "rddsp %1\n\t"
+ : "=r"(rt), "=r"(dsp)
+ : "r"(ach), "r"(acl)
+ );
+ dsp = (dsp >> 23) & 0x01;
+ assert(dsp == 0);
+ assert(result == rt);
+
return 0;
}
diff --git a/tpm/tpm.c b/tpm/tpm.c
index ffd2495..ae00eae 100644
--- a/tpm/tpm.c
+++ b/tpm/tpm.c
@@ -257,14 +257,13 @@
res->id = g_strdup(drv->id);
res->model = drv->fe_model;
- res->type = drv->ops->type;
- res->tpm_options = g_new0(TpmTypeOptions, 1);
+ res->options = g_new0(TpmTypeOptions, 1);
- switch (res->type) {
+ switch (drv->ops->type) {
case TPM_TYPE_PASSTHROUGH:
- res->tpm_options->kind = TPM_TYPE_OPTIONS_KIND_TPM_PASSTHROUGH_OPTIONS;
+ res->options->kind = TPM_TYPE_OPTIONS_KIND_PASSTHROUGH;
tpo = g_new0(TPMPassthroughOptions, 1);
- res->tpm_options->tpm_passthrough_options = tpo;
+ res->options->passthrough = tpo;
if (drv->path) {
tpo->path = g_strdup(drv->path);
tpo->has_path = true;
diff --git a/trace-events b/trace-events
index cd73b7f..406fe5f 100644
--- a/trace-events
+++ b/trace-events
@@ -958,8 +958,11 @@
dma_map_wait(void *dbs) "dbs=%p"
# console.h
-displaysurface_free(void *display_state, void *display_surface) "state=%p surface=%p"
-displaysurface_resize(void *display_state, void *display_surface, int width, int height) "state=%p surface=%p %dx%d"
+displaysurface_create(void *display_surface, int w, int h) "surface=%p, %dx%d"
+displaysurface_create_from(void *display_surface, int w, int h, int bpp, int swap) "surface=%p, %dx%d, bpp %d, bswap %d"
+displaysurface_free(void *display_surface) "surface=%p"
+displaychangelistener_register(void *dcl, const char *name) "%p [ %s ]"
+displaychangelistener_unregister(void *dcl, const char *name) "%p [ %s ]"
# vga.c
ppm_save(const char *filename, void *display_surface) "%s surface=%p"
diff --git a/translate-all.c b/translate-all.c
index 1f3237e..a98c646 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1308,11 +1308,11 @@
/* check whether the given addr is in TCG generated code buffer or not */
bool is_tcg_gen_code(uintptr_t tc_ptr)
{
- /* This can be called during code generation, code_gen_buffer_max_size
+ /* This can be called during code generation, code_gen_buffer_size
is used instead of code_gen_ptr for upper boundary checking */
return (tc_ptr >= (uintptr_t)tcg_ctx.code_gen_buffer &&
tc_ptr < (uintptr_t)(tcg_ctx.code_gen_buffer +
- tcg_ctx.code_gen_buffer_max_size));
+ tcg_ctx.code_gen_buffer_size));
}
#endif
diff --git a/ui/cocoa.m b/ui/cocoa.m
index ca42413..048cc97 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -264,8 +264,7 @@
BOOL isAbsoluteEnabled;
BOOL isTabletEnabled;
}
-- (void) resizeContentToWidth:(int)w height:(int)h displayState:(DisplayState *)ds;
-- (void) updateDataOffset:(DisplayState *)ds;
+- (void) switchSurface:(DisplaySurface *)surface;
- (void) grabMouse;
- (void) ungrabMouse;
- (void) toggleFullScreen:(id)sender;
@@ -400,19 +399,22 @@
}
}
-- (void) resizeContentToWidth:(int)w height:(int)h displayState:(DisplayState *)ds
+- (void) switchSurface:(DisplaySurface *)surface
{
- COCOA_DEBUG("QemuCocoaView: resizeContent\n");
+ COCOA_DEBUG("QemuCocoaView: switchSurface\n");
+
+ int w = surface_width(surface);
+ int h = surface_height(surface);
// update screenBuffer
if (dataProviderRef)
CGDataProviderRelease(dataProviderRef);
//sync host window color space with guests
- screen.bitsPerPixel = ds_get_bits_per_pixel(ds);
- screen.bitsPerComponent = ds_get_bytes_per_pixel(ds) * 2;
+ screen.bitsPerPixel = surface_bits_per_pixel(surface);
+ screen.bitsPerComponent = surface_bytes_per_pixel(surface) * 2;
- dataProviderRef = CGDataProviderCreateWithData(NULL, ds_get_data(ds), w * 4 * h, NULL);
+ dataProviderRef = CGDataProviderCreateWithData(NULL, surface_data(surface), w * 4 * h, NULL);
// update windows
if (isFullscreen) {
@@ -430,20 +432,6 @@
[self setFrame:NSMakeRect(cx, cy, cw, ch)];
}
-- (void) updateDataOffset:(DisplayState *)ds
-{
- COCOA_DEBUG("QemuCocoaView: UpdateDataOffset\n");
-
- // update screenBuffer
- if (dataProviderRef) {
- CGDataProviderRelease(dataProviderRef);
- }
-
- size_t size = ds_get_width(ds) * 4 * ds_get_height(ds);
- dataProviderRef = CGDataProviderCreateWithData(NULL, ds_get_data(ds),
- size, NULL);
-}
-
- (void) toggleFullScreen:(id)sender
{
COCOA_DEBUG("QemuCocoaView: toggleFullScreen\n");
@@ -969,7 +957,8 @@
#pragma mark qemu
-static void cocoa_update(DisplayState *ds, int x, int y, int w, int h)
+static void cocoa_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
{
COCOA_DEBUG("qemu_cocoa: cocoa_update\n");
@@ -986,14 +975,15 @@
[cocoaView setNeedsDisplayInRect:rect];
}
-static void cocoa_resize(DisplayState *ds)
+static void cocoa_switch(DisplayChangeListener *dcl,
+ DisplaySurface *surface)
{
COCOA_DEBUG("qemu_cocoa: cocoa_resize\n");
- [cocoaView resizeContentToWidth:(int)(ds_get_width(ds)) height:(int)(ds_get_height(ds)) displayState:ds];
+ [cocoaView switchSurface:surface];
}
-static void cocoa_refresh(DisplayState *ds)
+static void cocoa_refresh(DisplayChangeListener *dcl)
{
COCOA_DEBUG("qemu_cocoa: cocoa_refresh\n");
@@ -1019,17 +1009,19 @@
vga_hw_update();
}
-static void cocoa_setdata(DisplayState *ds)
-{
- [cocoaView updateDataOffset:ds];
-}
-
static void cocoa_cleanup(void)
{
COCOA_DEBUG("qemu_cocoa: cocoa_cleanup\n");
g_free(dcl);
}
+static const DisplayChangeListenerOps dcl_ops = {
+ .dpy_name = "cocoa",
+ .dpy_gfx_update = cocoa_update,
+ .dpy_gfx_switch = cocoa_switch,
+ .dpy_refresh = cocoa_refresh,
+};
+
void cocoa_display_init(DisplayState *ds, int full_screen)
{
COCOA_DEBUG("qemu_cocoa: cocoa_display_init\n");
@@ -1037,12 +1029,8 @@
dcl = g_malloc0(sizeof(DisplayChangeListener));
// register vga output callbacks
- dcl->dpy_gfx_update = cocoa_update;
- dcl->dpy_gfx_resize = cocoa_resize;
- dcl->dpy_refresh = cocoa_refresh;
- dcl->dpy_gfx_setdata = cocoa_setdata;
-
- register_displaychangelistener(ds, dcl);
+ dcl->ops = &dcl_ops;
+ register_displaychangelistener(ds, dcl);
// register cleanup function
atexit(cocoa_cleanup);
diff --git a/ui/console.c b/ui/console.c
index 27e87f8..eb7a2bc 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -208,51 +208,17 @@
active_console->hw_text_update(active_console->hw, chardata);
}
-/* convert a RGBA color to a color index usable in graphic primitives */
-static unsigned int vga_get_color(DisplayState *ds, unsigned int rgba)
+static void vga_fill_rect(QemuConsole *con,
+ int posx, int posy, int width, int height,
+ uint32_t color)
{
- unsigned int r, g, b, color;
-
- switch(ds_get_bits_per_pixel(ds)) {
-#if 0
- case 8:
- r = (rgba >> 16) & 0xff;
- g = (rgba >> 8) & 0xff;
- b = (rgba) & 0xff;
- color = (rgb_to_index[r] * 6 * 6) +
- (rgb_to_index[g] * 6) +
- (rgb_to_index[b]);
- break;
-#endif
- case 15:
- r = (rgba >> 16) & 0xff;
- g = (rgba >> 8) & 0xff;
- b = (rgba) & 0xff;
- color = ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
- break;
- case 16:
- r = (rgba >> 16) & 0xff;
- g = (rgba >> 8) & 0xff;
- b = (rgba) & 0xff;
- color = ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
- break;
- case 32:
- default:
- color = rgba;
- break;
- }
- return color;
-}
-
-static void vga_fill_rect (DisplayState *ds,
- int posx, int posy, int width, int height, uint32_t color)
-{
+ DisplaySurface *surface = qemu_console_surface(con);
uint8_t *d, *d1;
int x, y, bpp;
- bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
- d1 = ds_get_data(ds) +
- ds_get_linesize(ds) * posy + bpp * posx;
+ bpp = surface_bytes_per_pixel(surface);
+ d1 = surface_data(surface) +
+ surface_stride(surface) * posy + bpp * posx;
for (y = 0; y < height; y++) {
d = d1;
switch(bpp) {
@@ -275,38 +241,40 @@
}
break;
}
- d1 += ds_get_linesize(ds);
+ d1 += surface_stride(surface);
}
}
/* copy from (xs, ys) to (xd, yd) a rectangle of size (w, h) */
-static void vga_bitblt(DisplayState *ds, int xs, int ys, int xd, int yd, int w, int h)
+static void vga_bitblt(QemuConsole *con,
+ int xs, int ys, int xd, int yd, int w, int h)
{
+ DisplaySurface *surface = qemu_console_surface(con);
const uint8_t *s;
uint8_t *d;
int wb, y, bpp;
- bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
+ bpp = surface_bytes_per_pixel(surface);
wb = w * bpp;
if (yd <= ys) {
- s = ds_get_data(ds) +
- ds_get_linesize(ds) * ys + bpp * xs;
- d = ds_get_data(ds) +
- ds_get_linesize(ds) * yd + bpp * xd;
+ s = surface_data(surface) +
+ surface_stride(surface) * ys + bpp * xs;
+ d = surface_data(surface) +
+ surface_stride(surface) * yd + bpp * xd;
for (y = 0; y < h; y++) {
memmove(d, s, wb);
- d += ds_get_linesize(ds);
- s += ds_get_linesize(ds);
+ d += surface_stride(surface);
+ s += surface_stride(surface);
}
} else {
- s = ds_get_data(ds) +
- ds_get_linesize(ds) * (ys + h - 1) + bpp * xs;
- d = ds_get_data(ds) +
- ds_get_linesize(ds) * (yd + h - 1) + bpp * xd;
+ s = surface_data(surface) +
+ surface_stride(surface) * (ys + h - 1) + bpp * xs;
+ d = surface_data(surface) +
+ surface_stride(surface) * (yd + h - 1) + bpp * xd;
for (y = 0; y < h; y++) {
memmove(d, s, wb);
- d -= ds_get_linesize(ds);
- s -= ds_get_linesize(ds);
+ d -= surface_stride(surface);
+ s -= surface_stride(surface);
}
}
}
@@ -358,8 +326,6 @@
PAT(0xffffffff),
};
-static uint32_t color_table[2][8];
-
#ifndef CONFIG_CURSES
enum color_names {
COLOR_BLACK = 0,
@@ -396,23 +362,6 @@
}
};
-static inline unsigned int col_expand(DisplayState *ds, unsigned int col)
-{
- switch(ds_get_bits_per_pixel(ds)) {
- case 8:
- col |= col << 8;
- col |= col << 16;
- break;
- case 15:
- case 16:
- col |= col << 16;
- break;
- default:
- break;
- }
-
- return col;
-}
#ifdef DEBUG_CONSOLE
static void console_print_text_attributes(TextAttributes *t_attrib, char ch)
{
@@ -446,9 +395,10 @@
}
#endif
-static void vga_putcharxy(DisplayState *ds, int x, int y, int ch,
+static void vga_putcharxy(QemuConsole *s, int x, int y, int ch,
TextAttributes *t_attrib)
{
+ DisplaySurface *surface = qemu_console_surface(s);
uint8_t *d;
const uint8_t *font_ptr;
unsigned int font_data, linesize, xorcol, bpp;
@@ -461,20 +411,20 @@
#endif
if (t_attrib->invers) {
- bgcol = color_table[t_attrib->bold][t_attrib->fgcol];
- fgcol = color_table[t_attrib->bold][t_attrib->bgcol];
+ bgcol = color_table_rgb[t_attrib->bold][t_attrib->fgcol];
+ fgcol = color_table_rgb[t_attrib->bold][t_attrib->bgcol];
} else {
- fgcol = color_table[t_attrib->bold][t_attrib->fgcol];
- bgcol = color_table[t_attrib->bold][t_attrib->bgcol];
+ fgcol = color_table_rgb[t_attrib->bold][t_attrib->fgcol];
+ bgcol = color_table_rgb[t_attrib->bold][t_attrib->bgcol];
}
- bpp = (ds_get_bits_per_pixel(ds) + 7) >> 3;
- d = ds_get_data(ds) +
- ds_get_linesize(ds) * y * FONT_HEIGHT + bpp * x * FONT_WIDTH;
- linesize = ds_get_linesize(ds);
+ bpp = surface_bytes_per_pixel(surface);
+ d = surface_data(surface) +
+ surface_stride(surface) * y * FONT_HEIGHT + bpp * x * FONT_WIDTH;
+ linesize = surface_stride(surface);
font_ptr = vgafont16 + FONT_HEIGHT * ch;
xorcol = bgcol ^ fgcol;
- switch(ds_get_bits_per_pixel(ds)) {
+ switch (surface_bits_per_pixel(surface)) {
case 8:
for(i = 0; i < FONT_HEIGHT; i++) {
font_data = *font_ptr++;
@@ -579,19 +529,22 @@
TextCell *c;
int y1, y2;
- if (s == active_console) {
- if (!ds_get_bits_per_pixel(s->ds)) {
- text_update_xy(s, x, y);
- return;
- }
+ if (s != active_console) {
+ return;
+ }
+ if (s->ds->have_text) {
+ text_update_xy(s, x, y);
+ }
+
+ if (s->ds->have_gfx) {
y1 = (s->y_base + y) % s->total_height;
y2 = y1 - s->y_displayed;
if (y2 < 0)
y2 += s->total_height;
if (y2 < s->height) {
c = &s->cells[y1 * s->width + x];
- vga_putcharxy(s->ds, x, y2, c->ch,
+ vga_putcharxy(s, x, y2, c->ch,
&(c->t_attrib));
invalidate_xy(s, x, y2);
}
@@ -602,15 +555,17 @@
{
TextCell *c;
int y, y1;
+ int x = s->x;
- if (s == active_console) {
- int x = s->x;
+ if (s != active_console) {
+ return;
+ }
- if (!ds_get_bits_per_pixel(s->ds)) {
- s->cursor_invalidate = 1;
- return;
- }
+ if (s->ds->have_text) {
+ s->cursor_invalidate = 1;
+ }
+ if (s->ds->have_gfx) {
if (x >= s->width) {
x = s->width - 1;
}
@@ -623,9 +578,9 @@
if (show && s->cursor_visible_phase) {
TextAttributes t_attrib = s->t_attrib_default;
t_attrib.invers = !(t_attrib.invers); /* invert fg and bg */
- vga_putcharxy(s->ds, x, y, c->ch, &t_attrib);
+ vga_putcharxy(s, x, y, c->ch, &t_attrib);
} else {
- vga_putcharxy(s->ds, x, y, c->ch, &(c->t_attrib));
+ vga_putcharxy(s, x, y, c->ch, &(c->t_attrib));
}
invalidate_xy(s, x, y);
}
@@ -634,6 +589,7 @@
static void console_refresh(QemuConsole *s)
{
+ DisplaySurface *surface = qemu_console_surface(s);
TextCell *c;
int x, y, y1;
@@ -649,13 +605,13 @@
}
if (s->ds->have_gfx) {
- vga_fill_rect(s->ds, 0, 0, ds_get_width(s->ds), ds_get_height(s->ds),
- color_table[0][COLOR_BLACK]);
+ vga_fill_rect(s, 0, 0, surface_width(surface), surface_height(surface),
+ color_table_rgb[0][COLOR_BLACK]);
y1 = s->y_displayed;
for (y = 0; y < s->height; y++) {
c = s->cells + y1 * s->width;
for (x = 0; x < s->width; x++) {
- vga_putcharxy(s->ds, x, y, c->ch,
+ vga_putcharxy(s, x, y, c->ch,
&(c->t_attrib));
c++;
}
@@ -664,7 +620,8 @@
}
}
console_show_cursor(s, 1);
- dpy_gfx_update(s->ds, 0, 0, ds_get_width(s->ds), ds_get_height(s->ds));
+ dpy_gfx_update(s, 0, 0,
+ surface_width(surface), surface_height(surface));
}
}
@@ -727,24 +684,25 @@
c++;
}
if (s == active_console && s->y_displayed == s->y_base) {
- if (!ds_get_bits_per_pixel(s->ds)) {
+ if (s->ds->have_text) {
s->text_x[0] = 0;
s->text_y[0] = 0;
s->text_x[1] = s->width - 1;
s->text_y[1] = s->height - 1;
- return;
}
- vga_bitblt(s->ds, 0, FONT_HEIGHT, 0, 0,
- s->width * FONT_WIDTH,
- (s->height - 1) * FONT_HEIGHT);
- vga_fill_rect(s->ds, 0, (s->height - 1) * FONT_HEIGHT,
- s->width * FONT_WIDTH, FONT_HEIGHT,
- color_table[0][s->t_attrib_default.bgcol]);
- s->update_x0 = 0;
- s->update_y0 = 0;
- s->update_x1 = s->width * FONT_WIDTH;
- s->update_y1 = s->height * FONT_HEIGHT;
+ if (s->ds->have_gfx) {
+ vga_bitblt(s, 0, FONT_HEIGHT, 0, 0,
+ s->width * FONT_WIDTH,
+ (s->height - 1) * FONT_HEIGHT);
+ vga_fill_rect(s, 0, (s->height - 1) * FONT_HEIGHT,
+ s->width * FONT_WIDTH, FONT_HEIGHT,
+ color_table_rgb[0][s->t_attrib_default.bgcol]);
+ s->update_x0 = 0;
+ s->update_y0 = 0;
+ s->update_x1 = s->width * FONT_WIDTH;
+ s->update_y1 = s->height * FONT_HEIGHT;
+ }
}
}
}
@@ -1082,13 +1040,15 @@
void console_select(unsigned int index)
{
+ DisplaySurface *surface;
QemuConsole *s;
if (index >= MAX_CONSOLES)
return;
if (active_console) {
- active_console->g_width = ds_get_width(active_console->ds);
- active_console->g_height = ds_get_height(active_console->ds);
+ surface = qemu_console_surface(active_console);
+ active_console->g_width = surface_width(surface);
+ active_console->g_height = surface_height(surface);
}
s = consoles[index];
if (s) {
@@ -1099,11 +1059,11 @@
}
active_console = s;
if (ds->have_gfx) {
- ds->surface = qemu_resize_displaysurface(ds, s->g_width, s->g_height);
- dpy_gfx_resize(ds);
+ surface = qemu_create_displaysurface(s->g_width, s->g_height);
+ dpy_gfx_replace_surface(s, surface);
}
if (ds->have_text) {
- dpy_text_resize(ds, s->width, s->height);
+ dpy_text_resize(s, s->width, s->height);
}
if (s->cursor_timer) {
qemu_mod_timer(s->cursor_timer,
@@ -1128,7 +1088,7 @@
}
console_show_cursor(s, 1);
if (s->ds->have_gfx && s->update_x0 < s->update_x1) {
- dpy_gfx_update(s->ds, s->update_x0, s->update_y0,
+ dpy_gfx_update(s, s->update_x0, s->update_y0,
s->update_x1 - s->update_x0,
s->update_y1 - s->update_y0);
}
@@ -1216,9 +1176,11 @@
static void text_console_invalidate(void *opaque)
{
QemuConsole *s = (QemuConsole *) opaque;
- if (!ds_get_bits_per_pixel(s->ds) && s->console_type == TEXT_CONSOLE) {
- s->g_width = ds_get_width(s->ds);
- s->g_height = ds_get_height(s->ds);
+ DisplaySurface *surface = qemu_console_surface(s);
+
+ if (s->ds->have_text && s->console_type == TEXT_CONSOLE) {
+ s->g_width = surface_width(surface);
+ s->g_height = surface_height(surface);
text_console_resize(s);
}
console_refresh(s);
@@ -1238,7 +1200,7 @@
(s->cells[src].t_attrib.fgcol << 12) |
(s->cells[src].t_attrib.bgcol << 8) |
(s->cells[src].t_attrib.bold << 21));
- dpy_text_update(s->ds, s->text_x[0], s->text_y[0],
+ dpy_text_update(s, s->text_x[0], s->text_y[0],
s->text_x[1] - s->text_x[0], i - s->text_y[0]);
s->text_x[0] = s->width;
s->text_y[0] = s->height;
@@ -1246,23 +1208,11 @@
s->text_y[1] = 0;
}
if (s->cursor_invalidate) {
- dpy_text_cursor(s->ds, s->x, s->y);
+ dpy_text_cursor(s, s->x, s->y);
s->cursor_invalidate = 0;
}
}
-static QemuConsole *get_graphic_console(DisplayState *ds)
-{
- int i;
- QemuConsole *s;
- for (i = 0; i < nb_consoles; i++) {
- s = consoles[i];
- if (s->console_type == GRAPHIC_CONSOLE && s->ds == ds)
- return s;
- }
- return NULL;
-}
-
static QemuConsole *new_console(DisplayState *ds, console_type_t console_type)
{
QemuConsole *s;
@@ -1316,34 +1266,24 @@
#endif
}
-DisplaySurface *qemu_create_displaysurface(DisplayState *ds,
- int width, int height)
+DisplaySurface *qemu_create_displaysurface(int width, int height)
{
DisplaySurface *surface = g_new0(DisplaySurface, 1);
-
int linesize = width * 4;
+
+ trace_displaysurface_create(surface, width, height);
qemu_alloc_display(surface, width, height, linesize,
qemu_default_pixelformat(32), 0);
return surface;
}
-DisplaySurface *qemu_resize_displaysurface(DisplayState *ds,
- int width, int height)
-{
- int linesize = width * 4;
-
- trace_displaysurface_resize(ds, ds->surface, width, height);
- qemu_alloc_display(ds->surface, width, height, linesize,
- qemu_default_pixelformat(32), 0);
- return ds->surface;
-}
-
DisplaySurface *qemu_create_displaysurface_from(int width, int height, int bpp,
int linesize, uint8_t *data,
bool byteswap)
{
DisplaySurface *surface = g_new0(DisplaySurface, 1);
+ trace_displaysurface_create_from(surface, width, height, bpp, byteswap);
if (byteswap) {
surface->pf = qemu_different_endianness_pixelformat(bpp);
} else {
@@ -1364,14 +1304,162 @@
return surface;
}
-void qemu_free_displaysurface(DisplayState *ds)
+void qemu_free_displaysurface(DisplaySurface *surface)
{
- trace_displaysurface_free(ds, ds->surface);
- if (ds->surface == NULL) {
+ if (surface == NULL) {
return;
}
- qemu_pixman_image_unref(ds->surface->image);
- g_free(ds->surface);
+ trace_displaysurface_free(surface);
+ qemu_pixman_image_unref(surface->image);
+ g_free(surface);
+}
+
+void register_displaychangelistener(DisplayState *ds,
+ DisplayChangeListener *dcl)
+{
+ trace_displaychangelistener_register(dcl, dcl->ops->dpy_name);
+ dcl->ds = ds;
+ QLIST_INSERT_HEAD(&ds->listeners, dcl, next);
+ gui_setup_refresh(ds);
+ if (dcl->ops->dpy_gfx_switch) {
+ dcl->ops->dpy_gfx_switch(dcl, ds->surface);
+ }
+}
+
+void unregister_displaychangelistener(DisplayChangeListener *dcl)
+{
+ DisplayState *ds = dcl->ds;
+ trace_displaychangelistener_unregister(dcl, dcl->ops->dpy_name);
+ QLIST_REMOVE(dcl, next);
+ gui_setup_refresh(ds);
+}
+
+void dpy_gfx_update(QemuConsole *con, int x, int y, int w, int h)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ int width = pixman_image_get_width(s->surface->image);
+ int height = pixman_image_get_height(s->surface->image);
+
+ x = MAX(x, 0);
+ y = MAX(y, 0);
+ x = MIN(x, width);
+ y = MIN(y, height);
+ w = MIN(w, width - x);
+ h = MIN(h, height - y);
+
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_gfx_update) {
+ dcl->ops->dpy_gfx_update(dcl, x, y, w, h);
+ }
+ }
+}
+
+void dpy_gfx_replace_surface(QemuConsole *con,
+ DisplaySurface *surface)
+{
+ DisplayState *s = con->ds;
+ DisplaySurface *old_surface = s->surface;
+ struct DisplayChangeListener *dcl;
+
+ s->surface = surface;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_gfx_switch) {
+ dcl->ops->dpy_gfx_switch(dcl, surface);
+ }
+ }
+ qemu_free_displaysurface(old_surface);
+}
+
+void dpy_refresh(DisplayState *s)
+{
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_refresh) {
+ dcl->ops->dpy_refresh(dcl);
+ }
+ }
+}
+
+void dpy_gfx_copy(QemuConsole *con, int src_x, int src_y,
+ int dst_x, int dst_y, int w, int h)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_gfx_copy) {
+ dcl->ops->dpy_gfx_copy(dcl, src_x, src_y, dst_x, dst_y, w, h);
+ } else { /* TODO */
+ dcl->ops->dpy_gfx_update(dcl, dst_x, dst_y, w, h);
+ }
+ }
+}
+
+void dpy_text_cursor(QemuConsole *con, int x, int y)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_text_cursor) {
+ dcl->ops->dpy_text_cursor(dcl, x, y);
+ }
+ }
+}
+
+void dpy_text_update(QemuConsole *con, int x, int y, int w, int h)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_text_update) {
+ dcl->ops->dpy_text_update(dcl, x, y, w, h);
+ }
+ }
+}
+
+void dpy_text_resize(QemuConsole *con, int w, int h)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_text_resize) {
+ dcl->ops->dpy_text_resize(dcl, w, h);
+ }
+ }
+}
+
+void dpy_mouse_set(QemuConsole *con, int x, int y, int on)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_mouse_set) {
+ dcl->ops->dpy_mouse_set(dcl, x, y, on);
+ }
+ }
+}
+
+void dpy_cursor_define(QemuConsole *con, QEMUCursor *cursor)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_cursor_define) {
+ dcl->ops->dpy_cursor_define(dcl, cursor);
+ }
+ }
+}
+
+bool dpy_cursor_define_supported(QemuConsole *con)
+{
+ DisplayState *s = con->ds;
+ struct DisplayChangeListener *dcl;
+ QLIST_FOREACH(dcl, &s->listeners, next) {
+ if (dcl->ops->dpy_cursor_define) {
+ return true;
+ }
+ }
+ return false;
}
static void dumb_display_init(void)
@@ -1384,7 +1472,8 @@
width = active_console->g_width;
height = active_console->g_height;
}
- ds->surface = qemu_create_displaysurface(ds, width, height);
+ ds->surface = qemu_create_displaysurface(width, height);
+
register_displaystate(ds);
}
@@ -1409,32 +1498,27 @@
return display_state;
}
-DisplayState *graphic_console_init(vga_hw_update_ptr update,
- vga_hw_invalidate_ptr invalidate,
- vga_hw_screen_dump_ptr screen_dump,
- vga_hw_text_update_ptr text_update,
- void *opaque)
+QemuConsole *graphic_console_init(vga_hw_update_ptr update,
+ vga_hw_invalidate_ptr invalidate,
+ vga_hw_screen_dump_ptr screen_dump,
+ vga_hw_text_update_ptr text_update,
+ void *opaque)
{
QemuConsole *s;
DisplayState *ds;
ds = (DisplayState *) g_malloc0(sizeof(DisplayState));
- ds->surface = qemu_create_displaysurface(ds, 640, 480);
-
s = new_console(ds, GRAPHIC_CONSOLE);
- if (s == NULL) {
- qemu_free_displaysurface(ds);
- g_free(ds);
- return NULL;
- }
s->hw_update = update;
s->hw_invalidate = invalidate;
s->hw_screen_dump = screen_dump;
s->hw_text_update = text_update;
s->hw = opaque;
+ ds->surface = qemu_create_displaysurface(640, 480);
+
register_displaystate(ds);
- return ds;
+ return s;
}
int is_graphic_console(void)
@@ -1447,17 +1531,6 @@
return active_console && active_console->console_type != TEXT_CONSOLE;
}
-void console_color_init(DisplayState *ds)
-{
- int i, j;
- for (j = 0; j < 2; j++) {
- for (i = 0; i < 8; i++) {
- color_table[j][i] = col_expand(ds,
- vga_get_color(ds, color_table_rgb[j][i]));
- }
- }
-}
-
static void text_console_set_echo(CharDriverState *chr, bool echo)
{
QemuConsole *s = chr->opaque;
@@ -1478,7 +1551,6 @@
static void text_console_do_init(CharDriverState *chr, DisplayState *ds)
{
QemuConsole *s;
- static int color_inited;
s = chr->opaque;
@@ -1489,18 +1561,14 @@
s->kbd_timer = qemu_new_timer_ms(rt_clock, kbd_send_chars, s);
s->ds = ds;
- if (!color_inited) {
- color_inited = 1;
- console_color_init(s->ds);
- }
s->y_displayed = 0;
s->y_base = 0;
s->total_height = DEFAULT_BACKSCROLL;
s->x = 0;
s->y = 0;
if (s->console_type == TEXT_CONSOLE) {
- s->g_width = ds_get_width(s->ds);
- s->g_height = ds_get_height(s->ds);
+ s->g_width = surface_width(s->ds->surface);
+ s->g_height = surface_height(s->ds->surface);
}
s->cursor_timer =
@@ -1600,27 +1668,35 @@
}
}
-void qemu_console_resize(DisplayState *ds, int width, int height)
+void qemu_console_resize(QemuConsole *s, int width, int height)
{
- QemuConsole *s = get_graphic_console(ds);
- if (!s) return;
-
s->g_width = width;
s->g_height = height;
if (is_graphic_console()) {
- ds->surface = qemu_resize_displaysurface(ds, width, height);
- dpy_gfx_resize(ds);
+ DisplaySurface *surface;
+ surface = qemu_create_displaysurface(width, height);
+ dpy_gfx_replace_surface(s, surface);
}
}
-void qemu_console_copy(DisplayState *ds, int src_x, int src_y,
+void qemu_console_copy(QemuConsole *con, int src_x, int src_y,
int dst_x, int dst_y, int w, int h)
{
if (is_graphic_console()) {
- dpy_gfx_copy(ds, src_x, src_y, dst_x, dst_y, w, h);
+ dpy_gfx_copy(con, src_x, src_y, dst_x, dst_y, w, h);
}
}
+DisplaySurface *qemu_console_surface(QemuConsole *console)
+{
+ return console->ds->surface;
+}
+
+DisplayState *qemu_console_displaystate(QemuConsole *console)
+{
+ return console->ds;
+}
+
PixelFormat qemu_different_endianness_pixelformat(int bpp)
{
PixelFormat pf;
diff --git a/ui/curses.c b/ui/curses.c
index d78e378..ff82307 100644
--- a/ui/curses.c
+++ b/ui/curses.c
@@ -35,12 +35,14 @@
#define FONT_HEIGHT 16
#define FONT_WIDTH 8
+static DisplayChangeListener *dcl;
static console_ch_t screen[160 * 100];
static WINDOW *screenpad = NULL;
static int width, height, gwidth, gheight, invalidate;
static int px, py, sminx, sminy, smaxx, smaxy;
-static void curses_update(DisplayState *ds, int x, int y, int w, int h)
+static void curses_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
{
chtype *line;
@@ -91,7 +93,8 @@
}
}
-static void curses_resize(DisplayState *ds, int width, int height)
+static void curses_resize(DisplayChangeListener *dcl,
+ int width, int height)
{
if (width == gwidth && height == gheight) {
return;
@@ -128,7 +131,8 @@
#endif
#endif
-static void curses_cursor_position(DisplayState *ds, int x, int y)
+static void curses_cursor_position(DisplayChangeListener *dcl,
+ int x, int y)
{
if (x >= 0) {
x = sminx + x - px;
@@ -154,7 +158,7 @@
static kbd_layout_t *kbd_layout = NULL;
-static void curses_refresh(DisplayState *ds)
+static void curses_refresh(DisplayChangeListener *dcl)
{
int chr, nextchr, keysym, keycode, keycode_alt;
@@ -187,7 +191,7 @@
clear();
refresh();
curses_calc_pad();
- curses_update(ds, 0, 0, width, height);
+ curses_update(dcl, 0, 0, width, height);
continue;
}
#endif
@@ -323,9 +327,16 @@
}
}
+static const DisplayChangeListenerOps dcl_ops = {
+ .dpy_name = "curses",
+ .dpy_text_update = curses_update,
+ .dpy_text_resize = curses_resize,
+ .dpy_refresh = curses_refresh,
+ .dpy_text_cursor = curses_cursor_position,
+};
+
void curses_display_init(DisplayState *ds, int full_screen)
{
- DisplayChangeListener *dcl;
#ifndef _WIN32
if (!isatty(1)) {
fprintf(stderr, "We need a terminal output\n");
@@ -346,10 +357,7 @@
#endif
dcl = (DisplayChangeListener *) g_malloc0(sizeof(DisplayChangeListener));
- dcl->dpy_text_update = curses_update;
- dcl->dpy_text_resize = curses_resize;
- dcl->dpy_refresh = curses_refresh;
- dcl->dpy_text_cursor = curses_cursor_position;
+ dcl->ops = &dcl_ops;
register_displaychangelistener(ds, dcl);
invalidate = 1;
diff --git a/ui/gtk.c b/ui/gtk.c
index 794dab1..1edfaca 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -98,6 +98,11 @@
#define GDK_KEY_minus GDK_minus
#endif
+static const int modifier_keycode[] = {
+ /* shift, control, alt keys, meta keys, both left & right */
+ 0x2a, 0x36, 0x1d, 0x9d, 0x38, 0xb8, 0xdb, 0xdd,
+};
+
typedef struct VirtualConsole
{
GtkWidget *menu_item;
@@ -143,7 +148,7 @@
GtkWidget *drawing_area;
cairo_surface_t *surface;
DisplayChangeListener dcl;
- DisplayState *ds;
+ DisplaySurface *ds;
int button_mask;
int last_x;
int last_y;
@@ -157,6 +162,8 @@
gboolean free_scale;
bool external_pause_update;
+
+ bool modifier_pressed[ARRAY_SIZE(modifier_keycode)];
} GtkDisplayState;
static GtkDisplayState *global_state;
@@ -225,82 +232,8 @@
g_free(title);
}
-/** DisplayState Callbacks **/
-
-static void gd_update(DisplayState *ds, int x, int y, int w, int h)
+static void gd_update_windowsize(GtkDisplayState *s)
{
- GtkDisplayState *s = ds->opaque;
- int x1, x2, y1, y2;
- int mx, my;
- int fbw, fbh;
- int ww, wh;
-
- DPRINTF("update(x=%d, y=%d, w=%d, h=%d)\n", x, y, w, h);
-
- x1 = floor(x * s->scale_x);
- y1 = floor(y * s->scale_y);
-
- x2 = ceil(x * s->scale_x + w * s->scale_x);
- y2 = ceil(y * s->scale_y + h * s->scale_y);
-
- fbw = ds_get_width(s->ds) * s->scale_x;
- fbh = ds_get_height(s->ds) * s->scale_y;
-
- gdk_drawable_get_size(gtk_widget_get_window(s->drawing_area), &ww, &wh);
-
- mx = my = 0;
- if (ww > fbw) {
- mx = (ww - fbw) / 2;
- }
- if (wh > fbh) {
- my = (wh - fbh) / 2;
- }
-
- gtk_widget_queue_draw_area(s->drawing_area, mx + x1, my + y1, (x2 - x1), (y2 - y1));
-}
-
-static void gd_refresh(DisplayState *ds)
-{
- vga_hw_update();
-}
-
-static void gd_resize(DisplayState *ds)
-{
- GtkDisplayState *s = ds->opaque;
- cairo_format_t kind;
- int stride;
-
- DPRINTF("resize(width=%d, height=%d)\n",
- ds_get_width(ds), ds_get_height(ds));
-
- if (s->surface) {
- cairo_surface_destroy(s->surface);
- }
-
- switch (ds->surface->pf.bits_per_pixel) {
- case 8:
- kind = CAIRO_FORMAT_A8;
- break;
- case 16:
- kind = CAIRO_FORMAT_RGB16_565;
- break;
- case 32:
- kind = CAIRO_FORMAT_RGB24;
- break;
- default:
- g_assert_not_reached();
- break;
- }
-
- stride = cairo_format_stride_for_width(kind, ds_get_width(ds));
- g_assert(ds_get_linesize(ds) == stride);
-
- s->surface = cairo_image_surface_create_for_data(ds_get_data(ds),
- kind,
- ds_get_width(ds),
- ds_get_height(ds),
- ds_get_linesize(ds));
-
if (!s->full_screen) {
GtkRequisition req;
double sx, sy;
@@ -317,8 +250,8 @@
}
gtk_widget_set_size_request(s->drawing_area,
- ds_get_width(ds) * s->scale_x,
- ds_get_height(ds) * s->scale_y);
+ surface_width(s->ds) * s->scale_x,
+ surface_height(s->ds) * s->scale_y);
#if GTK_CHECK_VERSION(3, 0, 0)
gtk_widget_get_preferred_size(s->vbox, NULL, &req);
#else
@@ -330,6 +263,125 @@
}
}
+static void gd_update_full_redraw(GtkDisplayState *s)
+{
+ int ww, wh;
+ gdk_drawable_get_size(gtk_widget_get_window(s->drawing_area), &ww, &wh);
+ gtk_widget_queue_draw_area(s->drawing_area, 0, 0, ww, wh);
+}
+
+static void gtk_release_modifiers(GtkDisplayState *s)
+{
+ int i, keycode;
+
+ if (!gd_on_vga(s)) {
+ return;
+ }
+ for (i = 0; i < ARRAY_SIZE(modifier_keycode); i++) {
+ keycode = modifier_keycode[i];
+ if (!s->modifier_pressed[i]) {
+ continue;
+ }
+ if (keycode & SCANCODE_GREY) {
+ kbd_put_keycode(SCANCODE_EMUL0);
+ }
+ kbd_put_keycode(keycode | SCANCODE_UP);
+ s->modifier_pressed[i] = false;
+ }
+}
+
+/** DisplayState Callbacks **/
+
+static void gd_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
+{
+ GtkDisplayState *s = container_of(dcl, GtkDisplayState, dcl);
+ int x1, x2, y1, y2;
+ int mx, my;
+ int fbw, fbh;
+ int ww, wh;
+
+ DPRINTF("update(x=%d, y=%d, w=%d, h=%d)\n", x, y, w, h);
+
+ x1 = floor(x * s->scale_x);
+ y1 = floor(y * s->scale_y);
+
+ x2 = ceil(x * s->scale_x + w * s->scale_x);
+ y2 = ceil(y * s->scale_y + h * s->scale_y);
+
+ fbw = surface_width(s->ds) * s->scale_x;
+ fbh = surface_height(s->ds) * s->scale_y;
+
+ gdk_drawable_get_size(gtk_widget_get_window(s->drawing_area), &ww, &wh);
+
+ mx = my = 0;
+ if (ww > fbw) {
+ mx = (ww - fbw) / 2;
+ }
+ if (wh > fbh) {
+ my = (wh - fbh) / 2;
+ }
+
+ gtk_widget_queue_draw_area(s->drawing_area, mx + x1, my + y1, (x2 - x1), (y2 - y1));
+}
+
+static void gd_refresh(DisplayChangeListener *dcl)
+{
+ vga_hw_update();
+}
+
+static void gd_switch(DisplayChangeListener *dcl,
+ DisplaySurface *surface)
+{
+ GtkDisplayState *s = container_of(dcl, GtkDisplayState, dcl);
+ cairo_format_t kind;
+ bool resized = true;
+ int stride;
+
+ DPRINTF("resize(width=%d, height=%d)\n",
+ surface_width(surface), surface_height(surface));
+
+ if (s->surface) {
+ cairo_surface_destroy(s->surface);
+ }
+
+ if (s->ds &&
+ surface_width(s->ds) == surface_width(surface) &&
+ surface_height(s->ds) == surface_height(surface)) {
+ resized = false;
+ }
+ s->ds = surface;
+ switch (surface_bits_per_pixel(surface)) {
+ case 8:
+ kind = CAIRO_FORMAT_A8;
+ break;
+ case 16:
+ kind = CAIRO_FORMAT_RGB16_565;
+ break;
+ case 32:
+ kind = CAIRO_FORMAT_RGB24;
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+
+ stride = cairo_format_stride_for_width(kind, surface_width(surface));
+ g_assert(surface_stride(surface) == stride);
+
+ s->surface = cairo_image_surface_create_for_data(surface_data(surface),
+ kind,
+ surface_width(surface),
+ surface_height(surface),
+ surface_stride(surface));
+
+ if (resized) {
+ gd_update_windowsize(s);
+ } else {
+ gd_update_full_redraw(s);
+ }
+}
+
/** QEMU Events **/
static void gd_change_runstate(void *opaque, int running, RunState state)
@@ -368,8 +420,9 @@
if (!handled && propagate_accel) {
handled = gtk_window_activate_key(GTK_WINDOW(widget), key);
}
-
- if (!handled) {
+ if (handled) {
+ gtk_release_modifiers(s);
+ } else {
handled = gtk_window_propagate_key_event(GTK_WINDOW(widget), key);
}
@@ -382,7 +435,7 @@
GtkDisplayState *s = opaque;
if (!no_quit) {
- unregister_displaychangelistener(s->ds, &s->dcl);
+ unregister_displaychangelistener(&s->dcl);
qmp_quit(NULL);
return FALSE;
}
@@ -401,8 +454,8 @@
return FALSE;
}
- fbw = ds_get_width(s->ds);
- fbh = ds_get_height(s->ds);
+ fbw = surface_width(s->ds);
+ fbh = surface_height(s->ds);
gdk_drawable_get_size(gtk_widget_get_window(widget), &ww, &wh);
@@ -480,8 +533,8 @@
int fbh, fbw;
int ww, wh;
- fbw = ds_get_width(s->ds) * s->scale_x;
- fbh = ds_get_height(s->ds) * s->scale_y;
+ fbw = surface_width(s->ds) * s->scale_x;
+ fbh = surface_height(s->ds) * s->scale_y;
gdk_drawable_get_size(gtk_widget_get_window(s->drawing_area), &ww, &wh);
@@ -497,14 +550,14 @@
y = (motion->y - my) / s->scale_y;
if (x < 0 || y < 0 ||
- x >= ds_get_width(s->ds) ||
- y >= ds_get_height(s->ds)) {
+ x >= surface_width(s->ds) ||
+ y >= surface_height(s->ds)) {
return TRUE;
}
if (kbd_mouse_is_absolute()) {
- dx = x * 0x7FFF / (ds_get_width(s->ds) - 1);
- dy = y * 0x7FFF / (ds_get_height(s->ds) - 1);
+ dx = x * 0x7FFF / (surface_width(s->ds) - 1);
+ dy = y * 0x7FFF / (surface_height(s->ds) - 1);
} else if (s->last_x == -1 || s->last_y == -1) {
dx = 0;
dy = 0;
@@ -585,8 +638,8 @@
}
if (kbd_mouse_is_absolute()) {
- dx = s->last_x * 0x7FFF / (ds_get_width(s->ds) - 1);
- dy = s->last_y * 0x7FFF / (ds_get_height(s->ds) - 1);
+ dx = s->last_x * 0x7FFF / (surface_width(s->ds) - 1);
+ dy = s->last_y * 0x7FFF / (surface_height(s->ds) - 1);
} else {
dx = 0;
dy = 0;
@@ -599,8 +652,10 @@
static gboolean gd_key_event(GtkWidget *widget, GdkEventKey *key, void *opaque)
{
+ GtkDisplayState *s = opaque;
int gdk_keycode;
int qemu_keycode;
+ int i;
gdk_keycode = key->hardware_keycode;
@@ -622,6 +677,12 @@
gdk_keycode, qemu_keycode,
(key->type == GDK_KEY_PRESS) ? "down" : "up");
+ for (i = 0; i < ARRAY_SIZE(modifier_keycode); i++) {
+ if (qemu_keycode == modifier_keycode[i]) {
+ s->modifier_pressed[i] = (key->type == GDK_KEY_PRESS);
+ }
+ }
+
if (qemu_keycode & SCANCODE_GREY) {
kbd_put_keycode(SCANCODE_EMUL0);
}
@@ -677,6 +738,7 @@
} else {
int i;
+ gtk_release_modifiers(s);
for (i = 0; i < s->nb_vcs; i++) {
if (gtk_check_menu_item_get_active(GTK_CHECK_MENU_ITEM(s->vc[i].menu_item))) {
gtk_notebook_set_current_page(GTK_NOTEBOOK(s->notebook), i + 1);
@@ -715,7 +777,8 @@
gd_menu_show_tabs(GTK_MENU_ITEM(s->show_tabs_item), s);
gtk_widget_set_size_request(s->menu_bar, -1, -1);
gtk_widget_set_size_request(s->drawing_area,
- ds_get_width(s->ds), ds_get_height(s->ds));
+ surface_width(s->ds),
+ surface_height(s->ds));
gtk_check_menu_item_set_active(GTK_CHECK_MENU_ITEM(s->grab_item), FALSE);
s->full_screen = FALSE;
s->scale_x = 1.0;
@@ -735,7 +798,7 @@
s->scale_x += .25;
s->scale_y += .25;
- gd_resize(s->ds);
+ gd_update_windowsize(s);
}
static void gd_menu_zoom_out(GtkMenuItem *item, void *opaque)
@@ -751,7 +814,7 @@
s->scale_x = MAX(s->scale_x, .25);
s->scale_y = MAX(s->scale_y, .25);
- gd_resize(s->ds);
+ gd_update_windowsize(s);
}
static void gd_menu_zoom_fixed(GtkMenuItem *item, void *opaque)
@@ -761,13 +824,12 @@
s->scale_x = 1.0;
s->scale_y = 1.0;
- gd_resize(s->ds);
+ gd_update_windowsize(s);
}
static void gd_menu_zoom_fit(GtkMenuItem *item, void *opaque)
{
GtkDisplayState *s = opaque;
- int ww, wh;
if (gtk_check_menu_item_get_active(GTK_CHECK_MENU_ITEM(s->zoom_fit_item))) {
s->free_scale = TRUE;
@@ -775,10 +837,8 @@
s->free_scale = FALSE;
}
- gd_resize(s->ds);
-
- gdk_drawable_get_size(gtk_widget_get_window(s->drawing_area), &ww, &wh);
- gtk_widget_queue_draw_area(s->drawing_area, 0, 0, ww, wh);
+ gd_update_windowsize(s);
+ gd_update_full_redraw(s);
}
static void gd_grab_keyboard(GtkDisplayState *s)
@@ -979,6 +1039,16 @@
return TRUE;
}
+static gboolean gd_focus_out_event(GtkWidget *widget,
+ GdkEventCrossing *crossing, gpointer data)
+{
+ GtkDisplayState *s = data;
+
+ gtk_release_modifiers(s);
+
+ return TRUE;
+}
+
/** Virtual Console Callbacks **/
static int gd_vc_chr_write(CharDriverState *chr, const uint8_t *buf, int len)
@@ -1162,6 +1232,8 @@
G_CALLBACK(gd_enter_event), s);
g_signal_connect(s->drawing_area, "leave-notify-event",
G_CALLBACK(gd_leave_event), s);
+ g_signal_connect(s->drawing_area, "focus-out-event",
+ G_CALLBACK(gd_focus_out_event), s);
}
static void gd_create_menus(GtkDisplayState *s)
@@ -1281,17 +1353,20 @@
gtk_menu_shell_append(GTK_MENU_SHELL(s->menu_bar), s->view_menu_item);
}
+static const DisplayChangeListenerOps dcl_ops = {
+ .dpy_name = "gtk",
+ .dpy_gfx_update = gd_update,
+ .dpy_gfx_switch = gd_switch,
+ .dpy_refresh = gd_refresh,
+};
+
void gtk_display_init(DisplayState *ds)
{
GtkDisplayState *s = g_malloc0(sizeof(*s));
gtk_init(NULL, NULL);
- ds->opaque = s;
- s->ds = ds;
- s->dcl.dpy_gfx_update = gd_update;
- s->dcl.dpy_gfx_resize = gd_resize;
- s->dcl.dpy_refresh = gd_refresh;
+ s->dcl.ops = &dcl_ops;
s->window = gtk_window_new(GTK_WINDOW_TOPLEVEL);
#if GTK_CHECK_VERSION(3, 2, 0)
diff --git a/ui/sdl.c b/ui/sdl.c
index 1657848..8da0534 100644
--- a/ui/sdl.c
+++ b/ui/sdl.c
@@ -35,6 +35,7 @@
#include "sdl_zoom.h"
static DisplayChangeListener *dcl;
+static DisplaySurface *surface;
static SDL_Surface *real_screen;
static SDL_Surface *guest_screen = NULL;
static int gui_grab; /* if true, all keyboard/mouse events are grabbed */
@@ -59,7 +60,8 @@
static int scaling_active = 0;
static Notifier mouse_mode_notifier;
-static void sdl_update(DisplayState *ds, int x, int y, int w, int h)
+static void sdl_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
{
// printf("updating x=%d y=%d w=%d h=%d\n", x, y, w, h);
SDL_Rect rec;
@@ -81,16 +83,6 @@
SDL_UpdateRect(real_screen, rec.x, rec.y, rec.w, rec.h);
}
-static void sdl_setdata(DisplayState *ds)
-{
- if (guest_screen != NULL) SDL_FreeSurface(guest_screen);
-
- guest_screen = SDL_CreateRGBSurfaceFrom(ds_get_data(ds), ds_get_width(ds), ds_get_height(ds),
- ds_get_bits_per_pixel(ds), ds_get_linesize(ds),
- ds->surface->pf.rmask, ds->surface->pf.gmask,
- ds->surface->pf.bmask, ds->surface->pf.amask);
-}
-
static void do_sdl_resize(int width, int height, int bpp)
{
int flags;
@@ -114,15 +106,32 @@
}
}
-static void sdl_resize(DisplayState *ds)
+static void sdl_switch(DisplayChangeListener *dcl,
+ DisplaySurface *new_surface)
{
- if (!scaling_active) {
- do_sdl_resize(ds_get_width(ds), ds_get_height(ds), 0);
- } else if (real_screen->format->BitsPerPixel != ds_get_bits_per_pixel(ds)) {
- do_sdl_resize(real_screen->w, real_screen->h,
- ds_get_bits_per_pixel(ds));
+
+ /* temporary hack: allows to call sdl_switch to handle scaling changes */
+ if (new_surface) {
+ surface = new_surface;
}
- sdl_setdata(ds);
+
+ if (!scaling_active) {
+ do_sdl_resize(surface_width(surface), surface_height(surface), 0);
+ } else if (real_screen->format->BitsPerPixel !=
+ surface_bits_per_pixel(surface)) {
+ do_sdl_resize(real_screen->w, real_screen->h,
+ surface_bits_per_pixel(surface));
+ }
+
+ if (guest_screen != NULL) {
+ SDL_FreeSurface(guest_screen);
+ }
+ guest_screen = SDL_CreateRGBSurfaceFrom
+ (surface_data(surface),
+ surface_width(surface), surface_height(surface),
+ surface_bits_per_pixel(surface), surface_stride(surface),
+ surface->pf.rmask, surface->pf.gmask,
+ surface->pf.bmask, surface->pf.amask);
}
/* generic keyboard conversion */
@@ -445,7 +454,7 @@
kbd_mouse_event(dx, dy, dz, buttons);
}
-static void sdl_scale(DisplayState *ds, int width, int height)
+static void sdl_scale(int width, int height)
{
int bpp = real_screen->format->BitsPerPixel;
@@ -454,32 +463,30 @@
}
do_sdl_resize(width, height, bpp);
scaling_active = 1;
- if (!is_buffer_shared(ds->surface)) {
- ds->surface = qemu_resize_displaysurface(ds, ds_get_width(ds),
- ds_get_height(ds));
- dpy_gfx_resize(ds);
- }
}
-static void toggle_full_screen(DisplayState *ds)
+static void toggle_full_screen(void)
{
+ int width = surface_width(surface);
+ int height = surface_height(surface);
+ int bpp = surface_bits_per_pixel(surface);
+
gui_fullscreen = !gui_fullscreen;
if (gui_fullscreen) {
gui_saved_width = real_screen->w;
gui_saved_height = real_screen->h;
gui_saved_scaling = scaling_active;
- do_sdl_resize(ds_get_width(ds), ds_get_height(ds),
- ds_get_bits_per_pixel(ds));
+ do_sdl_resize(width, height, bpp);
scaling_active = 0;
gui_saved_grab = gui_grab;
sdl_grab_start();
} else {
if (gui_saved_scaling) {
- sdl_scale(ds, gui_saved_width, gui_saved_height);
+ sdl_scale(gui_saved_width, gui_saved_height);
} else {
- do_sdl_resize(ds_get_width(ds), ds_get_height(ds), 0);
+ do_sdl_resize(width, height, 0);
}
if (!gui_saved_grab || !is_graphic_console()) {
sdl_grab_end();
@@ -489,7 +496,7 @@
vga_hw_update();
}
-static void handle_keydown(DisplayState *ds, SDL_Event *ev)
+static void handle_keydown(SDL_Event *ev)
{
int mod_state;
int keycode;
@@ -508,13 +515,13 @@
keycode = sdl_keyevent_to_keycode(&ev->key);
switch (keycode) {
case 0x21: /* 'f' key on US keyboard */
- toggle_full_screen(ds);
+ toggle_full_screen();
gui_keysym = 1;
break;
case 0x16: /* 'u' key on US keyboard */
if (scaling_active) {
scaling_active = 0;
- sdl_resize(ds);
+ sdl_switch(dcl, NULL);
vga_hw_invalidate();
vga_hw_update();
}
@@ -545,9 +552,10 @@
if (!gui_fullscreen) {
int width = MAX(real_screen->w + (keycode == 0x1b ? 50 : -50),
160);
- int height = (ds_get_height(ds) * width) / ds_get_width(ds);
+ int height = (surface_height(surface) * width) /
+ surface_width(surface);
- sdl_scale(ds, width, height);
+ sdl_scale(width, height);
vga_hw_invalidate();
vga_hw_update();
gui_keysym = 1;
@@ -634,7 +642,7 @@
}
}
-static void handle_keyup(DisplayState *ds, SDL_Event *ev)
+static void handle_keyup(SDL_Event *ev)
{
int mod_state;
@@ -666,7 +674,7 @@
}
}
-static void handle_mousemotion(DisplayState *ds, SDL_Event *ev)
+static void handle_mousemotion(SDL_Event *ev)
{
int max_x, max_y;
@@ -690,7 +698,7 @@
}
}
-static void handle_mousebutton(DisplayState *ds, SDL_Event *ev)
+static void handle_mousebutton(SDL_Event *ev)
{
int buttonstate = SDL_GetMouseState(NULL, NULL);
SDL_MouseButtonEvent *bev;
@@ -726,7 +734,7 @@
}
}
-static void handle_activation(DisplayState *ds, SDL_Event *ev)
+static void handle_activation(SDL_Event *ev)
{
#ifdef _WIN32
/* Disable grab if the window no longer has the focus
@@ -753,7 +761,7 @@
}
}
-static void sdl_refresh(DisplayState *ds)
+static void sdl_refresh(DisplayChangeListener *dcl)
{
SDL_Event ev1, *ev = &ev1;
@@ -768,13 +776,13 @@
while (SDL_PollEvent(ev)) {
switch (ev->type) {
case SDL_VIDEOEXPOSE:
- sdl_update(ds, 0, 0, real_screen->w, real_screen->h);
+ sdl_update(dcl, 0, 0, real_screen->w, real_screen->h);
break;
case SDL_KEYDOWN:
- handle_keydown(ds, ev);
+ handle_keydown(ev);
break;
case SDL_KEYUP:
- handle_keyup(ds, ev);
+ handle_keyup(ev);
break;
case SDL_QUIT:
if (!no_quit) {
@@ -783,17 +791,17 @@
}
break;
case SDL_MOUSEMOTION:
- handle_mousemotion(ds, ev);
+ handle_mousemotion(ev);
break;
case SDL_MOUSEBUTTONDOWN:
case SDL_MOUSEBUTTONUP:
- handle_mousebutton(ds, ev);
+ handle_mousebutton(ev);
break;
case SDL_ACTIVEEVENT:
- handle_activation(ds, ev);
+ handle_activation(ev);
break;
case SDL_VIDEORESIZE:
- sdl_scale(ds, ev->resize.w, ev->resize.h);
+ sdl_scale(ev->resize.w, ev->resize.h);
vga_hw_invalidate();
vga_hw_update();
break;
@@ -803,7 +811,8 @@
}
}
-static void sdl_mouse_warp(DisplayState *ds, int x, int y, int on)
+static void sdl_mouse_warp(DisplayChangeListener *dcl,
+ int x, int y, int on)
{
if (on) {
if (!guest_cursor)
@@ -819,7 +828,8 @@
guest_x = x, guest_y = y;
}
-static void sdl_mouse_define(DisplayState *ds, QEMUCursor *c)
+static void sdl_mouse_define(DisplayChangeListener *dcl,
+ QEMUCursor *c)
{
uint8_t *image, *mask;
int bpl;
@@ -849,6 +859,15 @@
SDL_QuitSubSystem(SDL_INIT_VIDEO);
}
+static const DisplayChangeListenerOps dcl_ops = {
+ .dpy_name = "sdl",
+ .dpy_gfx_update = sdl_update,
+ .dpy_gfx_switch = sdl_switch,
+ .dpy_refresh = sdl_refresh,
+ .dpy_mouse_set = sdl_mouse_warp,
+ .dpy_cursor_define = sdl_mouse_define,
+};
+
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame)
{
int flags;
@@ -917,12 +936,7 @@
}
dcl = g_malloc0(sizeof(DisplayChangeListener));
- dcl->dpy_gfx_update = sdl_update;
- dcl->dpy_gfx_resize = sdl_resize;
- dcl->dpy_refresh = sdl_refresh;
- dcl->dpy_gfx_setdata = sdl_setdata;
- dcl->dpy_mouse_set = sdl_mouse_warp;
- dcl->dpy_cursor_define = sdl_mouse_define;
+ dcl->ops = &dcl_ops;
register_displaychangelistener(ds, dcl);
mouse_mode_notifier.notify = sdl_mouse_mode_change;
diff --git a/ui/spice-display.c b/ui/spice-display.c
index dc7e58d..eaab19d 100644
--- a/ui/spice-display.c
+++ b/ui/spice-display.c
@@ -214,10 +214,10 @@
static void qemu_spice_create_update(SimpleSpiceDisplay *ssd)
{
static const int blksize = 32;
- int blocks = (ds_get_width(ssd->ds) + blksize - 1) / blksize;
+ int blocks = (surface_width(ssd->ds) + blksize - 1) / blksize;
int dirty_top[blocks];
int y, yoff, x, xoff, blk, bw;
- int bpp = ds_get_bytes_per_pixel(ssd->ds);
+ int bpp = surface_bytes_per_pixel(ssd->ds);
uint8_t *guest, *mirror;
if (qemu_spice_rect_is_empty(&ssd->dirty)) {
@@ -225,19 +225,19 @@
};
if (ssd->surface == NULL) {
- ssd->surface = pixman_image_ref(ds_get_image(ssd->ds));
- ssd->mirror = qemu_pixman_mirror_create(ds_get_format(ssd->ds),
- ds_get_image(ssd->ds));
+ ssd->surface = pixman_image_ref(ssd->ds->image);
+ ssd->mirror = qemu_pixman_mirror_create(ssd->ds->format,
+ ssd->ds->image);
}
for (blk = 0; blk < blocks; blk++) {
dirty_top[blk] = -1;
}
- guest = ds_get_data(ssd->ds);
+ guest = surface_data(ssd->ds);
mirror = (void *)pixman_image_get_data(ssd->mirror);
for (y = ssd->dirty.top; y < ssd->dirty.bottom; y++) {
- yoff = y * ds_get_linesize(ssd->ds);
+ yoff = y * surface_stride(ssd->ds);
for (x = ssd->dirty.left; x < ssd->dirty.right; x += blksize) {
xoff = x * bpp;
blk = x / blksize;
@@ -312,11 +312,11 @@
memset(&surface, 0, sizeof(surface));
dprint(1, "%s: %dx%d\n", __FUNCTION__,
- ds_get_width(ssd->ds), ds_get_height(ssd->ds));
+ surface_width(ssd->ds), surface_height(ssd->ds));
surface.format = SPICE_SURFACE_FMT_32_xRGB;
- surface.width = ds_get_width(ssd->ds);
- surface.height = ds_get_height(ssd->ds);
+ surface.width = surface_width(ssd->ds);
+ surface.height = surface_height(ssd->ds);
surface.stride = -surface.width * 4;
surface.mouse_mode = true;
surface.flags = 0;
@@ -334,9 +334,8 @@
qemu_spice_destroy_primary_surface(ssd, 0, QXL_SYNC);
}
-void qemu_spice_display_init_common(SimpleSpiceDisplay *ssd, DisplayState *ds)
+void qemu_spice_display_init_common(SimpleSpiceDisplay *ssd)
{
- ssd->ds = ds;
qemu_mutex_init(&ssd->lock);
QTAILQ_INIT(&ssd->updates);
ssd->mouse_x = -1;
@@ -367,7 +366,8 @@
qemu_spice_rect_union(&ssd->dirty, &update_area);
}
-void qemu_spice_display_resize(SimpleSpiceDisplay *ssd)
+void qemu_spice_display_switch(SimpleSpiceDisplay *ssd,
+ DisplaySurface *surface)
{
SimpleSpiceUpdate *update;
@@ -382,6 +382,7 @@
}
qemu_mutex_lock(&ssd->lock);
+ ssd->ds = surface;
while ((update = QTAILQ_FIRST(&ssd->updates)) != NULL) {
QTAILQ_REMOVE(&ssd->updates, update, next);
qemu_spice_destroy_update(ssd, update);
@@ -397,12 +398,14 @@
void qemu_spice_cursor_refresh_unlocked(SimpleSpiceDisplay *ssd)
{
if (ssd->cursor) {
- dpy_cursor_define(ssd->ds, ssd->cursor);
+ assert(ssd->con);
+ dpy_cursor_define(ssd->con, ssd->cursor);
cursor_put(ssd->cursor);
ssd->cursor = NULL;
}
if (ssd->mouse_x != -1 && ssd->mouse_y != -1) {
- dpy_mouse_set(ssd->ds, ssd->mouse_x, ssd->mouse_y, 1);
+ assert(ssd->con);
+ dpy_mouse_set(ssd->con, ssd->mouse_x, ssd->mouse_y, 1);
ssd->mouse_x = -1;
ssd->mouse_y = -1;
}
@@ -414,7 +417,7 @@
vga_hw_update();
qemu_mutex_lock(&ssd->lock);
- if (QTAILQ_EMPTY(&ssd->updates)) {
+ if (QTAILQ_EMPTY(&ssd->updates) && ssd->ds) {
qemu_spice_create_update(ssd);
ssd->notify++;
}
@@ -581,39 +584,47 @@
.client_monitors_config = interface_client_monitors_config,
};
-static SimpleSpiceDisplay sdpy;
-
-static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
+static void display_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
{
- qemu_spice_display_update(&sdpy, x, y, w, h);
+ SimpleSpiceDisplay *ssd = container_of(dcl, SimpleSpiceDisplay, dcl);
+ qemu_spice_display_update(ssd, x, y, w, h);
}
-static void display_resize(struct DisplayState *ds)
+static void display_switch(DisplayChangeListener *dcl,
+ struct DisplaySurface *surface)
{
- qemu_spice_display_resize(&sdpy);
+ SimpleSpiceDisplay *ssd = container_of(dcl, SimpleSpiceDisplay, dcl);
+ qemu_spice_display_switch(ssd, surface);
}
-static void display_refresh(struct DisplayState *ds)
+static void display_refresh(DisplayChangeListener *dcl)
{
- qemu_spice_display_refresh(&sdpy);
+ SimpleSpiceDisplay *ssd = container_of(dcl, SimpleSpiceDisplay, dcl);
+ qemu_spice_display_refresh(ssd);
}
-static DisplayChangeListener display_listener = {
+static const DisplayChangeListenerOps display_listener_ops = {
+ .dpy_name = "spice",
.dpy_gfx_update = display_update,
- .dpy_gfx_resize = display_resize,
- .dpy_refresh = display_refresh,
+ .dpy_gfx_switch = display_switch,
+ .dpy_refresh = display_refresh,
};
void qemu_spice_display_init(DisplayState *ds)
{
- assert(sdpy.ds == NULL);
- qemu_spice_display_init_common(&sdpy, ds);
+ SimpleSpiceDisplay *ssd = g_new0(SimpleSpiceDisplay, 1);
- sdpy.qxl.base.sif = &dpy_interface.base;
- qemu_spice_add_interface(&sdpy.qxl.base);
- assert(sdpy.worker);
+ qemu_spice_display_init_common(ssd);
- qemu_spice_create_host_memslot(&sdpy);
- qemu_spice_create_host_primary(&sdpy);
- register_displaychangelistener(ds, &display_listener);
+ ssd->qxl.base.sif = &dpy_interface.base;
+ qemu_spice_add_interface(&ssd->qxl.base);
+ assert(ssd->worker);
+
+ qemu_spice_create_host_memslot(ssd);
+
+ ssd->dcl.ops = &display_listener_ops;
+ register_displaychangelistener(ds, &ssd->dcl);
+
+ qemu_spice_create_host_primary(ssd);
}
diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c
index 4ddea7d..e6966ae 100644
--- a/ui/vnc-enc-tight.c
+++ b/ui/vnc-enc-tight.c
@@ -123,7 +123,7 @@
return false;
}
- if (ds_get_bytes_per_pixel(vs->ds) == 1 ||
+ if (surface_bytes_per_pixel(vs->vd->ds) == 1 ||
vs->client_pf.bytes_per_pixel == 1) {
return false;
}
@@ -301,7 +301,7 @@
return 0;
}
- if (ds_get_bytes_per_pixel(vs->ds) == 1 ||
+ if (surface_bytes_per_pixel(vs->vd->ds) == 1 ||
vs->client_pf.bytes_per_pixel == 1 ||
w < VNC_TIGHT_DETECT_MIN_WIDTH || h < VNC_TIGHT_DETECT_MIN_HEIGHT) {
return 0;
@@ -1184,8 +1184,9 @@
uint8_t *buf;
int dy;
- if (ds_get_bytes_per_pixel(vs->ds) == 1)
+ if (surface_bytes_per_pixel(vs->vd->ds) == 1) {
return send_full_color_rect(vs, x, y, w, h);
+ }
buffer_reserve(&vs->tight.jpeg, 2048);
diff --git a/ui/vnc-jobs.c b/ui/vnc-jobs.c
index 0bfc0c5..2d3fce8 100644
--- a/ui/vnc-jobs.c
+++ b/ui/vnc-jobs.c
@@ -183,7 +183,6 @@
{
local->vnc_encoding = orig->vnc_encoding;
local->features = orig->features;
- local->ds = orig->ds;
local->vd = orig->vd;
local->lossy_rect = orig->lossy_rect;
local->write_pixels = orig->write_pixels;
diff --git a/ui/vnc.c b/ui/vnc.c
index ff4e2ae..bbe1e0f 100644
--- a/ui/vnc.c
+++ b/ui/vnc.c
@@ -44,7 +44,6 @@
#include "d3des.h"
static VncDisplay *vnc_display; /* needed for info vnc */
-static DisplayChangeListener *dcl;
static int vnc_cursor_define(VncState *vs);
static void vnc_release_modifiers(VncState *vs);
@@ -430,13 +429,14 @@
static void vnc_refresh(void *opaque);
static int vnc_refresh_server_surface(VncDisplay *vd);
-static void vnc_dpy_update(DisplayState *ds, int x, int y, int w, int h)
+static void vnc_dpy_update(DisplayChangeListener *dcl,
+ int x, int y, int w, int h)
{
int i;
- VncDisplay *vd = ds->opaque;
+ VncDisplay *vd = container_of(dcl, VncDisplay, dcl);
struct VncSurface *s = &vd->guest;
- int width = ds_get_width(ds);
- int height = ds_get_height(ds);
+ int width = surface_width(vd->ds);
+ int height = surface_height(vd->ds);
h += y;
@@ -518,17 +518,17 @@
static void vnc_desktop_resize(VncState *vs)
{
- DisplayState *ds = vs->ds;
+ DisplaySurface *ds = vs->vd->ds;
if (vs->csock == -1 || !vnc_has_feature(vs, VNC_FEATURE_RESIZE)) {
return;
}
- if (vs->client_width == ds_get_width(ds) &&
- vs->client_height == ds_get_height(ds)) {
+ if (vs->client_width == surface_width(ds) &&
+ vs->client_height == surface_height(ds)) {
return;
}
- vs->client_width = ds_get_width(ds);
- vs->client_height = ds_get_height(ds);
+ vs->client_width = surface_width(ds);
+ vs->client_height = surface_height(ds);
vnc_lock_output(vs);
vnc_write_u8(vs, VNC_MSG_SERVER_FRAMEBUFFER_UPDATE);
vnc_write_u8(vs, 0);
@@ -573,18 +573,20 @@
return ptr;
}
-static void vnc_dpy_resize(DisplayState *ds)
+static void vnc_dpy_switch(DisplayChangeListener *dcl,
+ DisplaySurface *surface)
{
- VncDisplay *vd = ds->opaque;
+ VncDisplay *vd = container_of(dcl, VncDisplay, dcl);
VncState *vs;
vnc_abort_display_jobs(vd);
/* server surface */
qemu_pixman_image_unref(vd->server);
+ vd->ds = surface;
vd->server = pixman_image_create_bits(VNC_SERVER_FB_FORMAT,
- ds_get_width(ds),
- ds_get_height(ds),
+ surface_width(vd->ds),
+ surface_height(vd->ds),
NULL, 0);
/* guest surface */
@@ -593,8 +595,8 @@
console_color_init(ds);
#endif
qemu_pixman_image_unref(vd->guest.fb);
- vd->guest.fb = pixman_image_ref(ds->surface->image);
- vd->guest.format = ds->surface->format;
+ vd->guest.fb = pixman_image_ref(surface->image);
+ vd->guest.format = surface->format;
memset(vd->guest.dirty, 0xFF, sizeof(vd->guest.dirty));
QTAILQ_FOREACH(vs, &vd->clients, next) {
@@ -735,9 +737,11 @@
vnc_flush(vs);
}
-static void vnc_dpy_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int dst_y, int w, int h)
+static void vnc_dpy_copy(DisplayChangeListener *dcl,
+ int src_x, int src_y,
+ int dst_x, int dst_y, int w, int h)
{
- VncDisplay *vd = ds->opaque;
+ VncDisplay *vd = container_of(dcl, VncDisplay, dcl);
VncState *vs, *vn;
uint8_t *src_row;
uint8_t *dst_row;
@@ -806,7 +810,8 @@
}
}
-static void vnc_mouse_set(DisplayState *ds, int x, int y, int visible)
+static void vnc_mouse_set(DisplayChangeListener *dcl,
+ int x, int y, int visible)
{
/* can we ask the client(s) to move the pointer ??? */
}
@@ -832,7 +837,8 @@
return -1;
}
-static void vnc_dpy_cursor_define(DisplayState *ds, QEMUCursor *c)
+static void vnc_dpy_cursor_define(DisplayChangeListener *dcl,
+ QEMUCursor *c)
{
VncDisplay *vd = vnc_display;
VncState *vs;
@@ -1059,7 +1065,7 @@
}
if (QTAILQ_EMPTY(&vs->vd->clients)) {
- dcl->idle = 1;
+ vs->vd->dcl.idle = 1;
}
vnc_remove_timer(vs->vd);
@@ -1453,7 +1459,8 @@
vnc_write_u8(vs, 0);
vnc_write_u16(vs, 1);
vnc_framebuffer_update(vs, absolute, 0,
- ds_get_width(vs->ds), ds_get_height(vs->ds),
+ surface_width(vs->vd->ds),
+ surface_height(vs->vd->ds),
VNC_ENCODING_POINTER_TYPE_CHANGE);
vnc_unlock_output(vs);
vnc_flush(vs);
@@ -1465,6 +1472,8 @@
{
int buttons = 0;
int dz = 0;
+ int width = surface_width(vs->vd->ds);
+ int height = surface_height(vs->vd->ds);
if (button_mask & 0x01)
buttons |= MOUSE_EVENT_LBUTTON;
@@ -1478,10 +1487,8 @@
dz = 1;
if (vs->absolute) {
- kbd_mouse_event(ds_get_width(vs->ds) > 1 ?
- x * 0x7FFF / (ds_get_width(vs->ds) - 1) : 0x4000,
- ds_get_height(vs->ds) > 1 ?
- y * 0x7FFF / (ds_get_height(vs->ds) - 1) : 0x4000,
+ kbd_mouse_event(width > 1 ? x * 0x7FFF / (width - 1) : 0x4000,
+ height > 1 ? y * 0x7FFF / (height - 1) : 0x4000,
dz, buttons);
} else if (vnc_has_feature(vs, VNC_FEATURE_POINTER_TYPE_CHANGE)) {
x -= 0x7FFF;
@@ -1771,12 +1778,15 @@
int w, int h)
{
int i;
- const size_t width = ds_get_width(vs->ds) / 16;
+ const size_t width = surface_width(vs->vd->ds) / 16;
+ const size_t height = surface_height(vs->vd->ds);
- if (y_position > ds_get_height(vs->ds))
- y_position = ds_get_height(vs->ds);
- if (y_position + h >= ds_get_height(vs->ds))
- h = ds_get_height(vs->ds) - y_position;
+ if (y_position > height) {
+ y_position = height;
+ }
+ if (y_position + h >= height) {
+ h = height - y_position;
+ }
vs->need_update = 1;
if (!incremental) {
@@ -1795,7 +1805,9 @@
vnc_write_u8(vs, VNC_MSG_SERVER_FRAMEBUFFER_UPDATE);
vnc_write_u8(vs, 0);
vnc_write_u16(vs, 1);
- vnc_framebuffer_update(vs, 0, 0, ds_get_width(vs->ds), ds_get_height(vs->ds),
+ vnc_framebuffer_update(vs, 0, 0,
+ surface_width(vs->vd->ds),
+ surface_height(vs->vd->ds),
VNC_ENCODING_EXT_KEY_EVENT);
vnc_unlock_output(vs);
vnc_flush(vs);
@@ -1807,7 +1819,9 @@
vnc_write_u8(vs, VNC_MSG_SERVER_FRAMEBUFFER_UPDATE);
vnc_write_u8(vs, 0);
vnc_write_u16(vs, 1);
- vnc_framebuffer_update(vs, 0, 0, ds_get_width(vs->ds), ds_get_height(vs->ds),
+ vnc_framebuffer_update(vs, 0, 0,
+ surface_width(vs->vd->ds),
+ surface_height(vs->vd->ds),
VNC_ENCODING_AUDIO);
vnc_unlock_output(vs);
vnc_flush(vs);
@@ -1972,16 +1986,6 @@
vs->write_pixels = vnc_write_pixels_copy;
}
-static void vnc_dpy_setdata(DisplayState *ds)
-{
- VncDisplay *vd = ds->opaque;
-
- qemu_pixman_image_unref(vd->guest.fb);
- vd->guest.fb = pixman_image_ref(ds->surface->image);
- vd->guest.format = ds->surface->format;
- vnc_dpy_update(ds, 0, 0, ds_get_width(ds), ds_get_height(ds));
-}
-
static void vnc_colordepth(VncState *vs)
{
if (vnc_has_feature(vs, VNC_FEATURE_WMVI)) {
@@ -1990,8 +1994,10 @@
vnc_write_u8(vs, VNC_MSG_SERVER_FRAMEBUFFER_UPDATE);
vnc_write_u8(vs, 0);
vnc_write_u16(vs, 1); /* number of rects */
- vnc_framebuffer_update(vs, 0, 0, ds_get_width(vs->ds),
- ds_get_height(vs->ds), VNC_ENCODING_WMVi);
+ vnc_framebuffer_update(vs, 0, 0,
+ surface_width(vs->vd->ds),
+ surface_height(vs->vd->ds),
+ VNC_ENCODING_WMVi);
pixel_format_message(vs);
vnc_unlock_output(vs);
vnc_flush(vs);
@@ -2207,8 +2213,8 @@
}
vnc_set_share_mode(vs, mode);
- vs->client_width = ds_get_width(vs->ds);
- vs->client_height = ds_get_height(vs->ds);
+ vs->client_width = surface_width(vs->vd->ds);
+ vs->client_height = surface_height(vs->vd->ds);
vnc_write_u16(vs, vs->client_width);
vnc_write_u16(vs, vs->client_height);
@@ -2686,7 +2692,7 @@
vd->timer_interval = VNC_REFRESH_INTERVAL_BASE;
if (vd->timer == NULL && !QTAILQ_EMPTY(&vd->clients)) {
vd->timer = qemu_new_timer_ms(rt_clock, vnc_refresh, vd);
- vnc_dpy_resize(vd->ds);
+ vga_hw_update();
vnc_refresh(vd);
}
}
@@ -2725,7 +2731,7 @@
}
VNC_DEBUG("New client on socket %d\n", csock);
- dcl->idle = 0;
+ vd->dcl.idle = 0;
socket_set_nonblock(vs->csock);
#ifdef CONFIG_VNC_WS
if (websocket) {
@@ -2756,7 +2762,6 @@
vs->initialized = true;
VncDisplay *vd = vs->vd;
- vs->ds = vd->ds;
vs->last_x = -1;
vs->last_y = -1;
@@ -2822,14 +2827,20 @@
}
#endif /* CONFIG_VNC_WS */
+static const DisplayChangeListenerOps dcl_ops = {
+ .dpy_name = "vnc",
+ .dpy_gfx_copy = vnc_dpy_copy,
+ .dpy_gfx_update = vnc_dpy_update,
+ .dpy_gfx_switch = vnc_dpy_switch,
+ .dpy_mouse_set = vnc_mouse_set,
+ .dpy_cursor_define = vnc_dpy_cursor_define,
+};
+
void vnc_display_init(DisplayState *ds)
{
VncDisplay *vs = g_malloc0(sizeof(*vs));
- dcl = g_malloc0(sizeof(DisplayChangeListener));
-
- ds->opaque = vs;
- dcl->idle = 1;
+ vs->dcl.idle = 1;
vnc_display = vs;
vs->lsock = -1;
@@ -2837,7 +2848,6 @@
vs->lwebsock = -1;
#endif
- vs->ds = ds;
QTAILQ_INIT(&vs->clients);
vs->expires = TIME_MAX;
@@ -2852,19 +2862,14 @@
qemu_mutex_init(&vs->mutex);
vnc_start_worker_thread();
- dcl->dpy_gfx_copy = vnc_dpy_copy;
- dcl->dpy_gfx_update = vnc_dpy_update;
- dcl->dpy_gfx_resize = vnc_dpy_resize;
- dcl->dpy_gfx_setdata = vnc_dpy_setdata;
- dcl->dpy_mouse_set = vnc_mouse_set;
- dcl->dpy_cursor_define = vnc_dpy_cursor_define;
- register_displaychangelistener(ds, dcl);
+ vs->dcl.ops = &dcl_ops;
+ register_displaychangelistener(ds, &vs->dcl);
}
static void vnc_display_close(DisplayState *ds)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
if (!vs)
return;
@@ -2895,7 +2900,7 @@
static int vnc_display_disable_login(DisplayState *ds)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
if (!vs) {
return -1;
@@ -2915,7 +2920,7 @@
int vnc_display_password(DisplayState *ds, const char *password)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
if (!vs) {
return -EINVAL;
@@ -2941,7 +2946,7 @@
int vnc_display_pw_expire(DisplayState *ds, time_t expires)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
if (!vs) {
return -EINVAL;
@@ -2953,14 +2958,14 @@
char *vnc_display_local_addr(DisplayState *ds)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
return vnc_socket_local_addr("%s:%s", vs->lsock);
}
void vnc_display_open(DisplayState *ds, const char *display, Error **errp)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
const char *options;
int password = 0;
int reverse = 0;
@@ -3266,7 +3271,7 @@
void vnc_display_add_client(DisplayState *ds, int csock, int skipauth)
{
- VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ VncDisplay *vs = vnc_display;
vnc_connect(vs, csock, skipauth, 0);
}
diff --git a/ui/vnc.h b/ui/vnc.h
index 45d7686..58e002e 100644
--- a/ui/vnc.h
+++ b/ui/vnc.h
@@ -150,7 +150,8 @@
bool websocket;
char *ws_display;
#endif
- DisplayState *ds;
+ DisplaySurface *ds;
+ DisplayChangeListener dcl;
kbd_layout_t *kbd_layout;
int lock_key_sync;
QemuMutex mutex;
@@ -247,7 +248,6 @@
{
int csock;
- DisplayState *ds;
DECLARE_BITMAP(dirty[VNC_MAX_HEIGHT], VNC_DIRTY_BITS);
uint8_t **lossy_rect; /* Not an Array to avoid costly memcpy in
* vnc-jobs-async.c */
diff --git a/util/Makefile.objs b/util/Makefile.objs
index cad5ce8..557bda7 100644
--- a/util/Makefile.objs
+++ b/util/Makefile.objs
@@ -9,3 +9,4 @@
util-obj-$(CONFIG_POSIX) += compatfd.o
util-obj-y += iov.o aes.o qemu-config.o qemu-sockets.o uri.o notify.o
util-obj-y += qemu-option.o qemu-progress.o
+util-obj-y += hexdump.o
diff --git a/util/bitops.c b/util/bitops.c
index e72237a..227c38b 100644
--- a/util/bitops.c
+++ b/util/bitops.c
@@ -42,7 +42,23 @@
size -= BITS_PER_LONG;
result += BITS_PER_LONG;
}
- while (size & ~(BITS_PER_LONG-1)) {
+ while (size >= 4*BITS_PER_LONG) {
+ unsigned long d1, d2, d3;
+ tmp = *p;
+ d1 = *(p+1);
+ d2 = *(p+2);
+ d3 = *(p+3);
+ if (tmp) {
+ goto found_middle;
+ }
+ if (d1 | d2 | d3) {
+ break;
+ }
+ p += 4;
+ result += 4*BITS_PER_LONG;
+ size -= 4*BITS_PER_LONG;
+ }
+ while (size >= BITS_PER_LONG) {
if ((tmp = *(p++))) {
goto found_middle;
}
diff --git a/util/cutils.c b/util/cutils.c
index 1439da4..5024253 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -143,6 +143,61 @@
}
/*
+ * Searches for an area with non-zero content in a buffer
+ *
+ * Attention! The len must be a multiple of
+ * BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE)
+ * and addr must be a multiple of sizeof(VECTYPE) due to
+ * restriction of optimizations in this function.
+ *
+ * can_use_buffer_find_nonzero_offset() can be used to check
+ * these requirements.
+ *
+ * The return value is the offset of the non-zero area rounded
+ * down to a multiple of sizeof(VECTYPE) for the first
+ * BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR chunks and down to
+ * BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR * sizeof(VECTYPE)
+ * afterwards.
+ *
+ * If the buffer is all zero the return value is equal to len.
+ */
+
+size_t buffer_find_nonzero_offset(const void *buf, size_t len)
+{
+ const VECTYPE *p = buf;
+ const VECTYPE zero = (VECTYPE){0};
+ size_t i;
+
+ assert(can_use_buffer_find_nonzero_offset(buf, len));
+
+ if (!len) {
+ return 0;
+ }
+
+ for (i = 0; i < BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR; i++) {
+ if (!ALL_EQ(p[i], zero)) {
+ return i * sizeof(VECTYPE);
+ }
+ }
+
+ for (i = BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR;
+ i < len / sizeof(VECTYPE);
+ i += BUFFER_FIND_NONZERO_OFFSET_UNROLL_FACTOR) {
+ VECTYPE tmp0 = p[i + 0] | p[i + 1];
+ VECTYPE tmp1 = p[i + 2] | p[i + 3];
+ VECTYPE tmp2 = p[i + 4] | p[i + 5];
+ VECTYPE tmp3 = p[i + 6] | p[i + 7];
+ VECTYPE tmp01 = tmp0 | tmp1;
+ VECTYPE tmp23 = tmp2 | tmp3;
+ if (!ALL_EQ(tmp01 | tmp23, zero)) {
+ break;
+ }
+ }
+
+ return i * sizeof(VECTYPE);
+}
+
+/*
* Checks if a buffer is all zeroes
*
* Attention! The len must be a multiple of 4 * sizeof(long) due to
@@ -160,6 +215,11 @@
long d0, d1, d2, d3;
const long * const data = buf;
+ /* use vector optimized zero check if possible */
+ if (can_use_buffer_find_nonzero_offset(buf, len)) {
+ return buffer_find_nonzero_offset(buf, len) == len;
+ }
+
assert(len % (4 * sizeof(long)) == 0);
len /= sizeof(long);
diff --git a/util/hexdump.c b/util/hexdump.c
new file mode 100644
index 0000000..0d0efc8
--- /dev/null
+++ b/util/hexdump.c
@@ -0,0 +1,37 @@
+/*
+ * Helper to hexdump a buffer
+ *
+ * Copyright (c) 2013 Red Hat, Inc.
+ * Copyright (c) 2013 Gerd Hoffmann <kraxel@redhat.com>
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ * Copyright (c) 2013 Xilinx, Inc
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#include "qemu-common.h"
+
+void hexdump(const char *buf, FILE *fp, const char *prefix, size_t size)
+{
+ unsigned int b;
+
+ for (b = 0; b < size; b++) {
+ if ((b % 16) == 0) {
+ fprintf(fp, "%s: %04x:", prefix, b);
+ }
+ if ((b % 4) == 0) {
+ fprintf(fp, " ");
+ }
+ fprintf(fp, " %02x", (unsigned char)buf[b]);
+ if ((b % 16) == 15) {
+ fprintf(fp, "\n");
+ }
+ }
+ if ((b % 16) != 0) {
+ fprintf(fp, "\n");
+ }
+}
diff --git a/util/iov.c b/util/iov.c
index fbe675d..9dae318 100644
--- a/util/iov.c
+++ b/util/iov.c
@@ -201,32 +201,18 @@
void iov_hexdump(const struct iovec *iov, const unsigned int iov_cnt,
FILE *fp, const char *prefix, size_t limit)
{
- unsigned int i, v, b;
- uint8_t *c;
+ int v;
+ size_t size = 0;
+ char *buf;
- c = iov[0].iov_base;
- for (i = 0, v = 0, b = 0; b < limit; i++, b++) {
- if (i == iov[v].iov_len) {
- i = 0; v++;
- if (v == iov_cnt) {
- break;
- }
- c = iov[v].iov_base;
- }
- if ((b % 16) == 0) {
- fprintf(fp, "%s: %04x:", prefix, b);
- }
- if ((b % 4) == 0) {
- fprintf(fp, " ");
- }
- fprintf(fp, " %02x", c[i]);
- if ((b % 16) == 15) {
- fprintf(fp, "\n");
- }
+ for (v = 0; v < iov_cnt; v++) {
+ size += iov[v].iov_len;
}
- if ((b % 16) != 0) {
- fprintf(fp, "\n");
- }
+ size = size > limit ? limit : size;
+ buf = g_malloc(size);
+ iov_to_buf(iov, iov_cnt, 0, buf, size);
+ hexdump(buf, fp, prefix, size);
+ g_free(buf);
}
unsigned iov_copy(struct iovec *dst_iov, unsigned int dst_iov_cnt,
diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c
index 83e4e08..b6b78f5 100644
--- a/util/qemu-sockets.c
+++ b/util/qemu-sockets.c
@@ -33,10 +33,10 @@
static const int on=1, off=0;
-/* used temporarely until all users are converted to QemuOpts */
-static QemuOptsList dummy_opts = {
- .name = "dummy",
- .head = QTAILQ_HEAD_INITIALIZER(dummy_opts.head),
+/* used temporarily until all users are converted to QemuOpts */
+QemuOptsList socket_optslist = {
+ .name = "socket",
+ .head = QTAILQ_HEAD_INITIALIZER(socket_optslist.head),
.desc = {
{
.name = "path",
@@ -156,12 +156,12 @@
continue;
}
- setsockopt(slisten,SOL_SOCKET,SO_REUSEADDR,(void*)&on,sizeof(on));
+ qemu_setsockopt(slisten, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on));
#ifdef IPV6_V6ONLY
if (e->ai_family == PF_INET6) {
/* listen on both ipv4 and ipv6 */
- setsockopt(slisten,IPPROTO_IPV6,IPV6_V6ONLY,(void*)&off,
- sizeof(off));
+ qemu_setsockopt(slisten, IPPROTO_IPV6, IPV6_V6ONLY, &off,
+ sizeof(off));
}
#endif
@@ -229,7 +229,7 @@
qemu_set_fd_handler2(s->fd, NULL, NULL, NULL, NULL);
do {
- rc = getsockopt(s->fd, SOL_SOCKET, SO_ERROR, (void *) &val, &valsize);
+ rc = qemu_getsockopt(s->fd, SOL_SOCKET, SO_ERROR, &val, &valsize);
} while (rc == -1 && socket_error() == EINTR);
/* update rc to contain error */
@@ -456,7 +456,7 @@
error_set_errno(errp, errno, QERR_SOCKET_CREATE_FAILED);
goto err;
}
- setsockopt(sock,SOL_SOCKET,SO_REUSEADDR,(void*)&on,sizeof(on));
+ qemu_setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on));
/* bind socket */
if (bind(sock, local->ai_addr, local->ai_addrlen) < 0) {
@@ -485,7 +485,7 @@
}
/* compatibility wrapper */
-static InetSocketAddress *inet_parse(const char *str, Error **errp)
+InetSocketAddress *inet_parse(const char *str, Error **errp)
{
InetSocketAddress *addr;
const char *optstr, *h;
@@ -555,7 +555,7 @@
return NULL;
}
-static void inet_addr_to_opts(QemuOpts *opts, InetSocketAddress *addr)
+static void inet_addr_to_opts(QemuOpts *opts, const InetSocketAddress *addr)
{
bool ipv4 = addr->ipv4 || !addr->has_ipv4;
bool ipv6 = addr->ipv6 || !addr->has_ipv6;
@@ -583,7 +583,7 @@
addr = inet_parse(str, errp);
if (addr != NULL) {
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
inet_addr_to_opts(opts, addr);
qapi_free_InetSocketAddress(addr);
sock = inet_listen_opts(opts, port_offset, errp);
@@ -622,7 +622,7 @@
addr = inet_parse(str, errp);
if (addr != NULL) {
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
inet_addr_to_opts(opts, addr);
qapi_free_InetSocketAddress(addr);
sock = inet_connect_opts(opts, errp, NULL, NULL);
@@ -656,7 +656,7 @@
addr = inet_parse(str, errp);
if (addr != NULL) {
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
inet_addr_to_opts(opts, addr);
qapi_free_InetSocketAddress(addr);
sock = inet_connect_opts(opts, errp, callback, opaque);
@@ -799,7 +799,7 @@
char *path, *optstr;
int sock, len;
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
optstr = strchr(str, ',');
if (optstr) {
@@ -827,7 +827,7 @@
QemuOpts *opts;
int sock;
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
qemu_opt_set(opts, "path", path);
sock = unix_connect_opts(opts, errp, NULL, NULL);
qemu_opts_del(opts);
@@ -844,7 +844,7 @@
g_assert(callback != NULL);
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
qemu_opt_set(opts, "path", path);
sock = unix_connect_opts(opts, errp, callback, opaque);
qemu_opts_del(opts);
@@ -895,7 +895,7 @@
QemuOpts *opts;
int fd;
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
switch (addr->kind) {
case SOCKET_ADDRESS_KIND_INET:
inet_addr_to_opts(opts, addr->inet);
@@ -926,7 +926,7 @@
QemuOpts *opts;
int fd;
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
switch (addr->kind) {
case SOCKET_ADDRESS_KIND_INET:
inet_addr_to_opts(opts, addr->inet);
@@ -954,7 +954,7 @@
QemuOpts *opts;
int fd;
- opts = qemu_opts_create_nofail(&dummy_opts);
+ opts = qemu_opts_create_nofail(&socket_optslist);
switch (remote->kind) {
case SOCKET_ADDRESS_KIND_INET:
qemu_opt_set(opts, "host", remote->inet->host);
diff --git a/vl.c b/vl.c
index a621aec..7643f16 100644
--- a/vl.c
+++ b/vl.c
@@ -234,6 +234,7 @@
unsigned int nb_prom_envs = 0;
const char *prom_envs[MAX_PROM_ENVS];
int boot_menu;
+bool boot_strict;
uint8_t *boot_splash_filedata;
size_t boot_splash_filedata_size;
uint8_t qemu_extra_params_fw[2];
@@ -458,6 +459,9 @@
}, {
.name = "reboot-timeout",
.type = QEMU_OPT_STRING,
+ }, {
+ .name = "strict",
+ .type = QEMU_OPT_STRING,
},
{ /*End of list */ }
},
@@ -658,6 +662,11 @@
return info;
}
+int64_t qmp_query_cpu_max(Error **errp)
+{
+ return current_machine->max_cpus;
+}
+
/***********************************************************/
/* real time host monotonic timer */
@@ -1267,6 +1276,12 @@
*size = total;
+ if (boot_strict && *size > 0) {
+ list[total-1] = '\n';
+ list = g_realloc(list, total + 4);
+ memcpy(&list[total], "HALT", 4);
+ *size = total + 4;
+ }
return list;
}
@@ -1639,13 +1654,13 @@
bool have_text = false;
QLIST_FOREACH(dcl, &ds->listeners, next) {
- if (dcl->dpy_refresh != NULL) {
+ if (dcl->ops->dpy_refresh != NULL) {
need_timer = true;
}
- if (dcl->dpy_gfx_update != NULL) {
+ if (dcl->ops->dpy_gfx_update != NULL) {
have_gfx = true;
}
- if (dcl->dpy_text_update != NULL) {
+ if (dcl->ops->dpy_text_update != NULL) {
have_text = true;
}
}
@@ -3131,7 +3146,7 @@
static const char * const params[] = {
"order", "once", "menu",
"splash", "splash-time",
- "reboot-timeout", NULL
+ "reboot-timeout", "strict", NULL
};
char buf[sizeof(boot_devices)];
char *standard_boot_devices;
@@ -3174,6 +3189,19 @@
exit(1);
}
}
+ if (get_param_value(buf, sizeof(buf),
+ "strict", optarg)) {
+ if (!strcmp(buf, "on")) {
+ boot_strict = true;
+ } else if (!strcmp(buf, "off")) {
+ boot_strict = false;
+ } else {
+ fprintf(stderr,
+ "qemu: invalid option value '%s'\n",
+ buf);
+ exit(1);
+ }
+ }
if (!qemu_opts_parse(qemu_find_opts("boot-opts"),
optarg, 0)) {
exit(1);
