commit 40e76f736d09535bc20e980a06c059229c7b5265
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> Mon May 05 21:39:38 2014 -0700
committer Stefan Hajnoczi <stefanha@redhat.com> Mon Jun 09 15:38:58 2014 +0200
tree bace666bd3a8f317041baf2a9e6279d1f9080486
parent 959e41473f2179850578482052fb73b913bc4e42

net: xilinx_ethlite: Fix Rx-pong interrupt

There is no CTRL_I bit in the pong buffer control register. The
CTRL_I bit from the ping buffer masks both ping and pong buffers.
Fix.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

hw/net/xilinx_ethlite.c

diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 5a434f6..1b177b3 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -196,8 +196,9 @@
     memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
 
     s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
-    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
+    if (s->regs[R_RX_CTRL0] & CTRL_I) {
         eth_pulse_irq(s);
+    }
 
     /* If c_rx_pingpong was set flip buffers.  */
     s->rxbuf ^= s->c_rx_pingpong;