Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Block pull request
# gpg: Signature made Fri 14 Feb 2014 17:26:30 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/block-pull-request:
block: Open by reference will try device then node_name.
block: Relax bdrv_lookup_bs constraints.
blockdev: Fix wrong usage of QDECREF causing snapshoted quorum to crash on close.
block: mirror - use local_err to avoid NULL errp
qemu-iotests: Don't run 005 on vmdk split formats
block: qemu-iotests - add vhdx log replay tests for qemu-img
block: qemu-iotests - fix test 070 (vhdx)
block: Don't throw away errno via error_setg
block: Add notes to iSCSI's .bdrv_open and .bdrv_reopen_prepare
blockdev: Remove 'type' parameter from blockdev_init()
sdhci: Drop unnecessary #include
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 9caf447..60c8061 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -73,6 +73,7 @@
float_status fp_status;
/* fpu implementation/revision register (fir) */
uint32_t fcr0;
+#define FCR0_UFRP 28
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
@@ -368,6 +369,18 @@
#define CP0C3_MT 2
#define CP0C3_SM 1
#define CP0C3_TL 0
+ uint32_t CP0_Config4;
+ uint32_t CP0_Config4_rw_bitmask;
+#define CP0C4_M 31
+ uint32_t CP0_Config5;
+ uint32_t CP0_Config5_rw_bitmask;
+#define CP0C5_M 31
+#define CP0C5_K 30
+#define CP0C5_CV 29
+#define CP0C5_EVA 28
+#define CP0C5_MSAEn 27
+#define CP0C5_UFR 2
+#define CP0C5_NFExists 0
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 1a8b86d..8c7921a 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -134,6 +134,8 @@
DEF_HELPER_2(mttc0_ebase, void, env, tl)
DEF_HELPER_2(mtc0_config0, void, env, tl)
DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_config4, void, env, tl)
+DEF_HELPER_2(mtc0_config5, void, env, tl)
DEF_HELPER_2(mtc0_lladdr, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
@@ -177,7 +179,7 @@
/* CP1 functions */
DEF_HELPER_2(cfc1, tl, env, i32)
-DEF_HELPER_3(ctc1, void, env, tl, i32)
+DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R2 0x00000040
#define ISA_MIPS64 0x00000080
#define ISA_MIPS64R2 0x00000100
+#define ISA_MIPS32R3 0x00000200
+#define ISA_MIPS32R5 0x00000400
/* MIPS ASEs. */
#define ASE_MIPS16 0x00001000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 8e3a6d7..2ef6633 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1489,6 +1489,18 @@
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
}
+void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
+{
+ env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
+ (arg1 & env->CP0_Config4_rw_bitmask);
+}
+
+void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
+{
+ env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
+ (arg1 & env->CP0_Config5_rw_bitmask);
+}
+
void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
{
target_long mask = env->CP0_LLAddr_rw_bitmask;
@@ -2187,12 +2199,23 @@
target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
{
- target_ulong arg1;
+ target_ulong arg1 = 0;
switch (reg) {
case 0:
arg1 = (int32_t)env->active_fpu.fcr0;
break;
+ case 1:
+ /* UFR Support - Read Status FR */
+ if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ arg1 = (int32_t)
+ ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ }
+ break;
case 25:
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
break;
@@ -2210,9 +2233,33 @@
return arg1;
}
-void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
+void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
{
- switch(reg) {
+ switch (fs) {
+ case 1:
+ /* UFR Alias - Reset Status FR */
+ if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
+ return;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ env->CP0_Status &= ~(1 << CP0St_FR);
+ compute_hflags(env);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ break;
+ case 4:
+ /* UNFR Alias - Set Status FR */
+ if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
+ return;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
+ env->CP0_Status |= (1 << CP0St_FR);
+ compute_hflags(env);
+ } else {
+ helper_raise_exception(env, EXCP_RI);
+ }
+ break;
case 25:
if (arg1 & 0xffffff00)
return;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ef0a2c3..083f6ab 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4405,7 +4405,14 @@
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
- /* 4,5 are reserved */
+ case 4:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
+ rn = "Config4";
+ break;
+ case 5:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
+ rn = "Config5";
+ break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4982,7 +4989,17 @@
/* ignored, read only */
rn = "Config3";
break;
- /* 4,5 are reserved */
+ case 4:
+ gen_helper_mtc0_config4(cpu_env, arg);
+ rn = "Config4";
+ ctx->bstate = BS_STOP;
+ break;
+ case 5:
+ gen_helper_mtc0_config5(cpu_env, arg);
+ rn = "Config5";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
+ break;
/* 6,7 are implementation dependent */
case 6:
/* ignored */
@@ -6801,7 +6818,12 @@
break;
case 3:
/* XXX: For now we support only a single FPU context. */
- gen_helper_0e1i(ctc1, t0, rd);
+ {
+ TCGv_i32 fs_tmp = tcg_const_i32(rd);
+
+ gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+ tcg_temp_free_i32(fs_tmp);
+ }
break;
/* COP2: Not implemented. */
case 4:
@@ -7237,7 +7259,12 @@
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
- gen_helper_0e1i(ctc1, t0, fs);
+ {
+ TCGv_i32 fs_tmp = tcg_const_i32(fs);
+
+ gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
+ tcg_temp_free_i32(fs_tmp);
+ }
opn = "ctc1";
break;
#if defined(TARGET_MIPS64)
@@ -15916,6 +15943,10 @@
env->CP0_Config1 = env->cpu_model->CP0_Config1;
env->CP0_Config2 = env->cpu_model->CP0_Config2;
env->CP0_Config3 = env->cpu_model->CP0_Config3;
+ env->CP0_Config4 = env->cpu_model->CP0_Config4;
+ env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
+ env->CP0_Config5 = env->cpu_model->CP0_Config5;
+ env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..29d39e2 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -45,6 +45,12 @@
(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
(0 << CP0C3_SM) | (0 << CP0C3_TL))
+#define MIPS_CONFIG4 \
+((0 << CP0C4_M))
+
+#define MIPS_CONFIG5 \
+((0 << CP0C5_M))
+
/* MMU types, the first four entries have the same layout as the
CP0C0_MT field. */
enum mips_mmu_types {
@@ -64,6 +70,10 @@
int32_t CP0_Config1;
int32_t CP0_Config2;
int32_t CP0_Config3;
+ int32_t CP0_Config4;
+ int32_t CP0_Config4_rw_bitmask;
+ int32_t CP0_Config5;
+ int32_t CP0_Config5_rw_bitmask;
int32_t CP0_Config6;
int32_t CP0_Config7;
target_ulong CP0_LLAddr_rw_bitmask;
@@ -333,6 +343,39 @@
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+ .name = "mips32r5-generic",
+ .CP0_PRid = 0x00019700,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
+ .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
+ (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
+ (0 << CP0C5_NFExists),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
+ (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
+ (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index b381477..776cb6e 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -707,6 +707,8 @@
uint32_t L6, K5;
#endif
uint32_t I16, I5, I11, N26, tmp;
+ TCGMemOp mop;
+
op0 = extract32(insn, 26, 6);
op1 = extract32(insn, 24, 2);
ra = extract32(insn, 16, 5);
@@ -838,72 +840,46 @@
/*#ifdef TARGET_OPENRISC64
case 0x20: l.ld
LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
- {
- check_ob64s(dc);
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld64(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free_i64(t0);
- }
- break;
+ check_ob64s(dc);
+ mop = MO_TEQ;
+ goto do_load;
#endif*/
case 0x21: /* l.lwz */
LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_TEUL;
+ goto do_load;
case 0x22: /* l.lws */
LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_TESL;
+ goto do_load;
case 0x23: /* l.lbz */
LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_UB;
+ goto do_load;
case 0x24: /* l.lbs */
LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_SB;
+ goto do_load;
case 0x25: /* l.lhz */
LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_TEUW;
+ goto do_load;
case 0x26: /* l.lhs */
LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
+ mop = MO_TESW;
+ goto do_load;
+
+ do_load:
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop);
tcg_temp_free(t0);
}
break;
@@ -1042,42 +1018,31 @@
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
- check_ob64s(dc);
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st64(cpu_R[rb], t0, dc->mem_idx);
- tcg_temp_free_i64(t0);
- }
- break;
+ check_ob64s(dc);
+ mop = MO_TEQ;
+ goto do_store;
#endif*/
case 0x35: /* l.sw */
LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st32(cpu_R[rb], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_TEUL;
+ goto do_store;
case 0x36: /* l.sb */
LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st8(cpu_R[rb], t0, dc->mem_idx);
- tcg_temp_free(t0);
- }
- break;
+ mop = MO_UB;
+ goto do_store;
case 0x37: /* l.sh */
LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
+ mop = MO_TEUW;
+ goto do_store;
+
+ do_store:
{
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st16(cpu_R[rb], t0, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
tcg_temp_free(t0);
}
break;
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 781b72f..7af3fe2 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1228,7 +1228,7 @@
#endif
case KVM_EXIT_EPR:
DPRINTF("handle epr\n");
- run->epr.epr = ldl_phys(env->mpic_iack);
+ run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
ret = 0;
break;
case KVM_EXIT_WATCHDOG:
