tree ba165baaf07869b860400db1b1381f3d633e9bfc
parent d60efc6b0d3d4e90cbbb86e21451e55263c29416
author Blue Swirl <blauwirbel@gmail.com> 1251224976 +0000
committer Blue Swirl <blauwirbel@gmail.com> 1251224976 +0000

Sparc32: improve interrupt handling

Level 15 interrupts are broadcast to all CPUs, each CPU can clear the
interrupt using the local Clear Pending register.

Update intbit_to_level table.

Don't try to raise level 0 interrupts.

Calculate pending interrupts based on the separate inputs from master
register. Setting or resetting the pending level isn't correct because of
overlap of levels.

Level 14 is always used for CPU timer interrupts, remove the property.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>