tree 52fc2bf24c522582b9002b0d478b1c70fb37e3b1
parent f46e9a0b9911fcfbc13f85f3a8808067990a0f5c
author Tom Musta <tommusta@gmail.com> 1401372744 -0500
committer Alexander Graf <agraf@suse.de> 1402917880 +0200

target-ppc: Store Quadword Conditional Drops Size Bit

The size and register information are encoded into the reserve_info field
of CPU state in the store conditional translation code.  Specifically, the
size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store).

The user-mode store conditional code erroneously extracts the size by ANDing
with a 4 bit mask; this breaks if size >= 16.

Eliminate the mask to make the extraction of size mirror its encoding.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>