)]}'
{
  "commit": "5204ea79ea739b557f47fc4db96c94edcb33a5d6",
  "tree": "6b439e0077f4624a23b47ec81770e4debda4cf9c",
  "parents": [
    "e117f52636d04502fab28bd3abe93347c29f39a5"
  ],
  "author": {
    "name": "Leon Alrae",
    "email": "leon.alrae@imgtec.com",
    "time": "Thu Sep 11 16:28:17 2014 +0100"
  },
  "committer": {
    "name": "Leon Alrae",
    "email": "leon.alrae@imgtec.com",
    "time": "Fri Jun 12 09:05:31 2015 +0100"
  },
  "message": "target-mips: add MTHC0 and MFHC0 instructions\n\nImplement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access\nupper word of extended to 64-bits CP0 registers.\n\nIn MIPS64, when CP0 destination register specified is the EntryLo0 or\nEntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or\nEntryLo1. This is to compensate for RI and XI, which were shifted to bits\n63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate\nfunctions for EntryLo0 and EntryLo1.\n\nSigned-off-by: Leon Alrae \u003cleon.alrae@imgtec.com\u003e\nReviewed-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "832468c0a706ce5738b429a8a8adf510e697f7d3",
      "old_mode": 33188,
      "old_path": "disas/mips.c",
      "new_id": "32940feb954266421c7832d19471619df26dc211",
      "new_mode": 33188,
      "new_path": "disas/mips.c"
    },
    {
      "type": "modify",
      "old_id": "c266e9ff718d25f22e2a6073bf8a25e39d5cae03",
      "old_mode": 33188,
      "old_path": "target-mips/cpu.h",
      "new_id": "474a0e327dfd61070cee422af28171e4bb7291fe",
      "new_mode": 33188,
      "new_path": "target-mips/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "6a39ef0e5ad20c8d01c9cdb8a69196256186d9c8",
      "old_mode": 33188,
      "old_path": "target-mips/translate.c",
      "new_id": "1d128eef02fcd16a3e1fe3ca178d567ac9668bf1",
      "new_mode": 33188,
      "new_path": "target-mips/translate.c"
    }
  ]
}