)]}'
{
  "commit": "5210977a8511fc0c4a8a1a68c01fa3b65e29edc0",
  "tree": "dd12f3bcc62297f325c30718c6d42764dff0afd6",
  "parents": [
    "49e6637386acb8824114ed10308ed7869472ec0f"
  ],
  "author": {
    "name": "Igor Kovalenko",
    "email": "igor.v.kovalenko@gmail.com",
    "time": "Sun Jul 12 12:35:31 2009 +0400"
  },
  "committer": {
    "name": "Blue Swirl",
    "email": "blauwirbel@gmail.com",
    "time": "Sun Jul 12 08:46:54 2009 +0000"
  },
  "message": "sparc64: trap handling corrections\n\nOn Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl\u003cblauwirbel@gmail.com\u003e wrote:\n\u003e On 7/12/09, Igor Kovalenko \u003cigor.v.kovalenko@gmail.com\u003e wrote:\n\u003e\u003e Good trap handling is required to process interrupts.\n\u003e\u003e  This patch fixes the following:\n\u003e\u003e\n\u003e\u003e  - sparc64 has no wim register\n\u003e\u003e  - sparc64 has no psret register, use IE bit of pstate\n\u003e\u003e   extract IE checking code to cpu_interrupts_enabled\n\u003e\u003e  - alternate globals are not available if cpu has GL feature\n\u003e\u003e   in this case bit AG of pstate is constant zero\n\u003e\u003e  - write to pstate must actually write pstate\n\u003e\u003e   even if cpu has GL feature\n\u003e\u003e\n\u003e\u003e  Also timer interrupt is handled using do_interrupt.\n\u003e\n\u003e A bit too much for one patch. Please also remove the code instead of\n\u003e commenting out.\n\nI now excluded timer interrupt related part.\nTo my mind other changes are essentially tied together.\n\n\u003e PUT_PSR for Sparc64 needs CC_OP \u003d CC_OP_FLAGS; like Sparc32.\n\nFixed, please find attached the updated version.\n\n--\nKind regards,\nIgor V. Kovalenko\n",
  "tree_diff": [
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