tree 5394929d40f7919493a6dc04def85b9d8dffb72a
parent 059ca2bf0d882349aa002e10e3769d25cb923eb4
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1389003397 +0000
committer Peter Maydell <peter.maydell@linaro.org> 1389208041 +0000

char/cadence_uart: Add missing uart_update_state

This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1c250cd61b7b8de492fbc8b79b8370958a56d83b.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>