commit 5b2808bfc06279db6a56942f3f6119c23ae07f42
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Sat May 03 11:06:59 2008 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Sat May 03 11:06:59 2008 +0000
tree d4ff2b1fda588a7e66295131eb34a2f5a78ef4d5
parent 50cfa95cbd6d0ab896530f7af07a4d5e7539ddc0

Fix MIPS MT GPR accesses, thanks Stefan Weil.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4307 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/op.c

diff --git a/target-mips/op.c b/target-mips/op.c
index c5187fe..b19c439 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -2300,7 +2300,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2308,7 +2308,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2316,7 +2316,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2324,7 +2324,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2340,7 +2340,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2348,7 +2348,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2356,7 +2356,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2364,7 +2364,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }
 

target-mips/op_template.c

diff --git a/target-mips/op_template.c b/target-mips/op_template.c
index c683330..e7e3750 100644
--- a/target-mips/op_template.c
+++ b/target-mips/op_template.c
@@ -52,13 +52,13 @@
 
 void glue(op_load_srsgpr_T0_gpr, REG) (void)
 {
-    T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf];
+    T0 = env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG];
     FORCE_RET();
 }
 
 void glue(op_store_T0_srsgpr_gpr, REG) (void)
 {
-    env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0;
+    env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG] = T0;
     FORCE_RET();
 }
 #endif