)]}'
{
  "commit": "62bf3df432d93fa6eb0f355c460d6d784b7cbc1a",
  "tree": "1130e9024e95c5479bca9ca0fd45557978daa82d",
  "parents": [
    "385057cbec9b4a0eb6150330c572e875ed714965",
    "18084b2f71b22b3ec3bf4828b8cb83d1d39e8502"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon May 18 20:23:16 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon May 18 20:23:16 2015 +0100"
  },
  "message": "Merge remote-tracking branch \u0027remotes/pmaydell/tags/pull-target-arm-20150518-3\u0027 into staging\n\ntarget-arm:\n * New board model: xlnx-ep108\n * Some more preparation for AArch64 EL2/EL3\n * Fix bugs in access checking for generic counter registers\n * Remove a stray \u0027+\u0027 sign\n\n# gpg: Signature made Mon May 18 20:13:05 2015 BST using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n\n* remotes/pmaydell/tags/pull-target-arm-20150518-3: (21 commits)\n  target-arm: Remove unneeded \u0027+\u0027\n  target-arm: Correct accessfn for CNTV_TVAL_EL0\n  target-arm: Correct accessfn for CNTP_{CT}VAL_EL0\n  target-arm: Add WFx syndrome function\n  target-arm: Add EL3 and EL2 TCR checking\n  target-arm: Add TTBR regime function and use\n  linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create\n  arm: xlnx-ep108: Add bootloading\n  arm: xlnx-ep108: Add external RAM\n  arm: Add xlnx-ep108 machine\n  arm: xlnx-zynqmp: Add UART support\n  char: cadence_uart: Split state struct and type into header\n  char: cadence_uart: Clean up variable names\n  arm: xlnx-zynqmp: Add GEM support\n  net: cadence_gem: Split state struct and type into header\n  net: cadence_gem: Clean up variable names\n  arm: xlnx-zynqmp: Connect CPU Timers to GIC\n  arm: xlnx-zynqmp: Add GIC\n  arm: Introduce Xilinx ZynqMP SoC\n  target-arm: cpu64: Add support for Cortex-A53\n  ...\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}