)]}'
{
  "commit": "6619bc5c55c1322a89009e2edd530113da95d551",
  "tree": "305b213a8168d24c8df60a3a930b3a800086a827",
  "parents": [
    "103db49a106d1f015a16432eb73cc4046792fbad"
  ],
  "author": {
    "name": "Beniamino Galvani",
    "email": "b.galvani@gmail.com",
    "time": "Tue Mar 25 19:22:10 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Apr 17 21:34:06 2014 +0100"
  },
  "message": "allwinner-emac: update irq status after writes to interrupt registers\n\nThe irq line status must be updated after writes to the INT_CTL and\nINT_STA registers.\n\nSigned-off-by: Beniamino Galvani \u003cb.galvani@gmail.com\u003e\nReviewed-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nMessage-id: 1395771730-16882-8-git-send-email-b.galvani@gmail.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "91931acad6519b0ad27d9742bb5244aadceff867",
      "old_mode": 33188,
      "old_path": "hw/net/allwinner_emac.c",
      "new_id": "d780ba0fcb85efc2d0fb57f09315a92d1ca6f8df",
      "new_mode": 33188,
      "new_path": "hw/net/allwinner_emac.c"
    }
  ]
}