)]}'
{
  "commit": "6825b6c33c5668f0993b03937623d3e891aa540f",
  "tree": "27768a91cf985bf2e43d0521bc9e2b96e0f685c5",
  "parents": [
    "890c6333b28a4dcbf2a26a5a17b0e71304d5a851"
  ],
  "author": {
    "name": "Max Filippov",
    "email": "jcmvbkbc@gmail.com",
    "time": "Mon Oct 10 06:25:40 2011 +0400"
  },
  "committer": {
    "name": "Blue Swirl",
    "email": "blauwirbel@gmail.com",
    "time": "Sat Oct 15 21:03:40 2011 +0000"
  },
  "message": "target-xtensa: implement MAC16 option\n\nSee ISA, 4.3.7 for the details.\n\n- add ACC and MR special registers;\n- implement MAC16 and all inner MAC* opcode groups.\n\nSigned-off-by: Max Filippov \u003cjcmvbkbc@gmail.com\u003e\nSigned-off-by: Blue Swirl \u003cblauwirbel@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "966f5152494440ac520df545f0613ee38dfd9de8",
      "old_mode": 33188,
      "old_path": "target-xtensa/cpu.h",
      "new_id": "b43e565254a3babc6785289c266dcd0c39aed0e4",
      "new_mode": 33188,
      "new_path": "target-xtensa/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "93a807e8c0a58ddfa251e2b7049a0b38d6062eb0",
      "old_mode": 33188,
      "old_path": "target-xtensa/translate.c",
      "new_id": "70bea623966ec425965877d0f5b24dec40d4e197",
      "new_mode": 33188,
      "new_path": "target-xtensa/translate.c"
    }
  ]
}