commit 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf
author Sebastian Huber <sebastian.huber@embedded-brains.de> Wed Feb 05 08:31:55 2014 +0100
committer Peter Maydell <peter.maydell@linaro.org> Sat Feb 08 14:50:48 2014 +0000
tree 097276492e0349e104ab56269ddb29a80ce2c513
parent db7dfd4c7e4450b10048a53ce67bcac6305ad383

arm/zynq: Add software system reset via SCLR

Support software-driven system reset via the register in the SCLR.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

hw/misc/zynq_slcr.c

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index e42a5b0..d1cc233 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -31,6 +31,8 @@
 #define XILINX_LOCK_KEY 0x767b
 #define XILINX_UNLOCK_KEY 0xdf0d
 
+#define R_PSS_RST_CTRL_SOFT_RST 0x1
+
 typedef enum {
   ARM_PLL_CTRL,
   DDR_PLL_CTRL,
@@ -399,6 +401,9 @@
                 goto bad_reg;
             }
             s->reset[(offset - 0x200) / 4] = val;
+            if (offset == 0x200 && (val & R_PSS_RST_CTRL_SOFT_RST)) {
+                qemu_system_reset_request();
+            }
             break;
         case 0x300:
             s->apu_ctrl = val;