commit 69d1a9377453d78ba2279fa56ae9623b3cd98673
author Tom Musta <tommusta@gmail.com> Thu Dec 18 10:34:31 2014 -0600
committer Alexander Graf <agraf@suse.de> Wed Jan 07 16:16:27 2015 +0100
tree 3ee55988add9762fc51e3504e352b0f703b32f2d
parent e43668a7d20e5d2dfe92b2f3426280b2a351333c

target-ppc: Introduce tm_enabled Bit to CPU State

Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other "available" bits in the MSR (FP,
VSX, etc.).

NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

target-ppc/translate.c

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a772382..3b004f3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -203,6 +203,7 @@
     int altivec_enabled;
     int vsx_enabled;
     int spe_enabled;
+    int tm_enabled;
     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
     int singlestep_enabled;
     uint64_t insns_flags;
@@ -11342,6 +11343,13 @@
     } else {
         ctx.vsx_enabled = 0;
     }
+#if defined(TARGET_PPC64)
+    if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
+        ctx.tm_enabled = msr_tm;
+    } else {
+        ctx.tm_enabled = 0;
+    }
+#endif
     if ((env->flags & POWERPC_FLAG_SE) && msr_se)
         ctx.singlestep_enabled = CPU_SINGLE_STEP;
     else