tree 285285860c7d2e441592aea59bc9f777d9b514b4
parent d4f4f0d5d9e74c19614479592c8bc865d92773d0
author Yongbok Kim <yongbok.kim@imgtec.com> 1435678395 +0100
committer Leon Alrae <leon.alrae@imgtec.com> 1436965640 +0100

disas/mips: fix disassembling R6 instructions

In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
and CACHE instructions have 9 bits offsets.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>