commit 6ce0ca1204c0536d071f86ac1309c5b6fd99c351
author blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> Sat Mar 07 20:54:59 2009 +0000
committer blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> Sat Mar 07 20:54:59 2009 +0000
tree 3c6017c308f8a83f77f116c5a96d697336ba4100
parent 4e98d8cf0a7672bb1208e534112f00d7019998a8

Enable 64bit mode on interrupts

Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <alex@csgraf.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc/helper.c

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 5f3199e..60a63b8 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2612,7 +2612,7 @@
             new_msr |= (target_ulong)1 << MSR_CM;
         }
     } else {
-        if (!msr_isf) {
+        if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
             new_msr &= ~((target_ulong)1 << MSR_SF);
             vector = (uint32_t)vector;
         } else {
@@ -2793,6 +2793,10 @@
         ppc_tlb_invalidate_all(env);
 #endif
     env->msr = msr & env->msr_mask;
+#if defined(TARGET_PPC64)
+    if (env->mmu_model & POWERPC_MMU_64)
+        env->msr |= (1ULL << MSR_SF);
+#endif
     hreg_compute_hflags(env);
     env->reserve = (target_ulong)-1ULL;
     /* Be sure no exception or interrupt is pending */