)]}'
{
  "commit": "7162bdea75e9f63afdd2cacfe26ee4b472a59362",
  "tree": "66141574af3bd2dc642e2c4696c1c1ca28099fe8",
  "parents": [
    "c170a23ca0097a95b44fc7cc604018cd3c3b7d44"
  ],
  "author": {
    "name": "Julio Guerra",
    "email": "guerr@julio.in",
    "time": "Mon Jun 24 23:15:54 2013 +0200"
  },
  "committer": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Thu Jul 11 18:51:23 2013 +0200"
  },
  "message": "e600 core for MPC86xx processors\n\nMPC86xx processors are based on the e600 core, which is not the case\nin qemu where it is based on the 7400 processor.\n\nThis patch creates the e600 core and instantiates the MPC86xx\nprocessors based on it. Therefore, adding the high BATs, the SPRG\n4..7 registers, which are e600-specific [1], and a HW MMU model (as 7400).\nThis allows to define the MPC8610 processor too.\n\nTested with a kernel using the HW TLB misses.\n\n[1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf\n\nSigned-off-by: Julio Guerra \u003cguerr@julio.in\u003e\nSigned-off-by: Alexander Graf \u003cagraf@suse.de\u003e\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "target-ppc/cpu-models.c",
      "new_id": "13dd670218d523b1326db103e07bcf9186d7f88a",
      "new_mode": 33188,
      "new_path": "target-ppc/cpu-models.c"
    },
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      "old_mode": 33188,
      "old_path": "target-ppc/cpu-models.h",
      "new_id": "fcd3a151d68ad78d200ffb20fa6d29071fc198dc",
      "new_mode": 33188,
      "new_path": "target-ppc/cpu-models.h"
    },
    {
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      "old_id": "b62f04abef35895224330210b21dd9a1606c98b8",
      "old_mode": 33188,
      "old_path": "target-ppc/translate_init.c",
      "new_id": "76483d9aa2738434c4d37145136dc87c6863522c",
      "new_mode": 33188,
      "new_path": "target-ppc/translate_init.c"
    }
  ]
}