tree 50ea3690a02c798f87e8fb10cf6f2d5d8e91131c
parent 71ca034a0dee69f77c8ac6ea7d21e5b6a0b0d836
author Leon Alrae <leon.alrae@imgtec.com> 1442235504 +0100
committer Leon Alrae <leon.alrae@imgtec.com> 1446135404 +0000

target-mips: implement the CPU wake-up on non-enabled interrupts in R6

In Release 6, the behaviour of WAIT has been modified to make it a
requirement that a processor that has disabled operation as a result of
executing a WAIT will resume operation on arrival of an interrupt even if
interrupts are not enabled.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>