)]}'
{
  "commit": "7624789234cd63b671bce1b49b93b0b1c00ea407",
  "tree": "0b77cd9ab7c23b95eca2202e03215b8c13b5641a",
  "parents": [
    "dbdc13a1ac0bfaa9a2d7069e9e6509721ed795ee"
  ],
  "author": {
    "name": "Madhavan Srinivasan",
    "email": "maddy@linux.vnet.ibm.com",
    "time": "Fri Nov 20 17:01:48 2015 +0530"
  },
  "committer": {
    "name": "David Gibson",
    "email": "david@gibson.dropbear.id.au",
    "time": "Mon Nov 30 19:39:01 2015 +1100"
  },
  "message": "target-ppc/fpu_helper: fix FPSCR_FX bit shift operation\n\nCurrently in TCG mode, updating floating exception\nsummary bit (FPSCR_FX) in fpscr also updates\nthe upper 32bits of fpscr with all 1s.\nModify the bit shift operation statement to use\n1ULL instead.\n\nSigned-off-by: Madhavan Srinivasan \u003cmaddy@linux.vnet.ibm.com\u003e\nSigned-off-by: David Gibson \u003cdavid@gibson.dropbear.id.au\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6cceffc556244bde6a6385c3264efdc26681566c",
      "old_mode": 33188,
      "old_path": "target-ppc/fpu_helper.c",
      "new_id": "9f2d53d7478a230fb83a66275636f3ae9b12748c",
      "new_mode": 33188,
      "new_path": "target-ppc/fpu_helper.c"
    }
  ]
}