tree 0b77cd9ab7c23b95eca2202e03215b8c13b5641a
parent dbdc13a1ac0bfaa9a2d7069e9e6509721ed795ee
author Madhavan Srinivasan <maddy@linux.vnet.ibm.com> 1448019108 +0530
committer David Gibson <david@gibson.dropbear.id.au> 1448872741 +1100

target-ppc/fpu_helper: fix FPSCR_FX bit shift operation

Currently in TCG mode, updating floating exception
summary bit (FPSCR_FX) in fpscr also updates
the upper 32bits of fpscr with all 1s.
Modify the bit shift operation statement to use
1ULL instead.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>