PCI: fix bridge configuration
PCI bridges' qdev info structures must indicate bridge header type,
otherwise critical bridge registers (esp. PCI_PRIMARY_BUS,
PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS) will not be writable.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index a72c656..7f458c6 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -365,6 +365,7 @@
.qdev.name = "pbm",
.qdev.size = sizeof(PCIDevice),
.init = pbm_pci_host_init,
+ .header_type = PCI_HEADER_TYPE_BRIDGE,
};
static void pbm_register_devices(void)
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index ee4fed5..f455c59 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -181,6 +181,7 @@
.qdev.name = "dec-21154",
.qdev.size = sizeof(PCIDevice),
.init = dec_21154_pci_host_init,
+ .header_type = PCI_HEADER_TYPE_BRIDGE,
};
static void grackle_register_devices(void)
diff --git a/hw/pci.c b/hw/pci.c
index b83fd53..023f7b6 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1874,6 +1874,7 @@
.init = pci_bridge_initfn,
.exit = pci_bridge_exitfn,
.config_write = pci_bridge_write_config,
+ .header_type = PCI_HEADER_TYPE_BRIDGE,
.qdev.props = (Property[]) {
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 3ae4e7a..b8a805b 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -269,6 +269,7 @@
.qdev.name = "dec-21154",
.qdev.size = sizeof(PCIDevice),
.init = dec_21154_pci_host_init,
+ .header_type = PCI_HEADER_TYPE_BRIDGE,
};
static PCIDeviceInfo unin_agp_pci_host_info = {