tree 10cfbe17f8fc7f347abac4299f4834ae045a029e
parent 34a4450434f1a5daee06fca223afcbb9c8f1ee24
parent cea66e91212164e02ad1d245c2371f7e8eb59e7f
author Peter Maydell <peter.maydell@linaro.org> 1440516246 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1440516246 +0100
mergetag object cea66e91212164e02ad1d245c2371f7e8eb59e7f
 type commit
 tag pull-target-arm-20150825-1
 tagger Peter Maydell <peter.maydell@linaro.org> 1440516138 +0100
 
 target-arm queue:
  * add missing EL2/EL3 TLBI operations
  * add missing EL2/EL3 ATS operations
  * add missing EL2/EL3 registers
  * update Xilinx MAINTAINERS info
  * Xilinx: connect the four OCM banks
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJV3IhDAAoJEDwlJe0UNgzebLcP+wQZ769gSxaYkwk344bzFtlx
 NKnJ/Khz/h3dyZoVUezusjMOi3tOWuIZcx/mCXtDY+5Vz3SKtLWDTOCNR79pSe86
 gWlGef6b/qLJVNIf1h2xPbdD3u1oSj1qrksR8nNPJTnQBB/3EAQ5mqwr4xlGQjdW
 PoSyFsTic3yOc5vTl7rFBRTP2dMauHEjxLdsO2d29uIv2gBYkRIwf3knTPU5ejjU
 eGJ6I1R4539GeS9hZ+K3GjZ5nYIPfzjoWotNI9rMbsZW/rw97DY/rCeecqal64bd
 dcFtx1jVNWNhbu8ybfpqcqoqyDgJ3TRhY8nt5i5FoDnQ+ALiqMPJA7wA24hBG0wc
 4LhMtAGvILyBpzAr/4Gpni+Yk+xUmu5cauNIDmwkCwGKXolW2c/dPo9w1NqoQizc
 FXNlFYDq0Qri+hahMQ4RNfnLUQfH0BjsYk+eB/Pff6pOZJx4oM0ShVB9EoTWvYKT
 5k6DNG3P3YpBDCBZjQ9JXMdc6hbDIpr6ihoILkxPgwJbG6g4R6QNbGbL0TxuumST
 q2fCg2vRPEprd8nB1KTW5CezXWl9Qwkp0hoPmE96BovjOy+E53Kymo4zudsT9Q7t
 ZCpd3CWWQrPHY1c/9LMJAGjHggZQ2lkI2ozc2U5Q9H7792Y0/6q8wGvhyDG45VPA
 336njiYMoJ69n3Fopeth
 =/T8R
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150825-1' into staging

target-arm queue:
 * add missing EL2/EL3 TLBI operations
 * add missing EL2/EL3 ATS operations
 * add missing EL2/EL3 registers
 * update Xilinx MAINTAINERS info
 * Xilinx: connect the four OCM banks

# gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20150825-1:
  target-arm: Implement AArch64 TLBI operations on IPAs
  target-arm: Implement missing EL3 TLB invalidate operations
  target-arm: Implement missing EL2 TLBI operations
  target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
  target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
  cputlb: Add functions for flushing TLB for a single MMU index
  target-arm: Implement AArch32 ATS1H* operations
  target-arm: Enable the AArch32 ATS12NSO ops
  target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
  target-arm: Wire up AArch64 EL2 and EL3 address translation ops
  target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
  target-arm: Implement missing ACTLR registers
  target-arm: Implement missing AFSR registers
  target-arm: Implement missing AMAIR registers
  target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
  MAINTAINERS: Add ZynqMP to MAINTAINERS file
  MAINTAINERS: Update Xilinx Maintainership
  xlnx-zynqmp: Connect the four OCM banks

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>