)]}'
{
  "commit": "8085ce63c5967d200f1241b6c0a189371993c5df",
  "tree": "bedaaf4ccbc88fdf91e1455c63385a616f2a447d",
  "parents": [
    "62b44f059a84d1ac580a653fc4110dfabaef6b83"
  ],
  "author": {
    "name": "Peter Crosthwaite",
    "email": "peter.crosthwaite@xilinx.com",
    "time": "Mon Jun 15 18:06:10 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jun 15 18:06:10 2015 +0100"
  },
  "message": "arm: Do not define TLBTR in PMSA systems\n\nIf doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP.\nThe def is done separately from VMSA registers group as it is affected\nby both the OMAP/STRONGARM RW errata and the MIDR backgrounding.\n\nSigned-off-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nMessage-id: b03fea3840207edf633f5c9189400c3dd6a28d14.1434066412.git.peter.crosthwaite@xilinx.com\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6a62d798c2d2b6854829b79a63a30a1aace1c877",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "d46db914488f34ec428fb4466a43803ede944e34",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}