)]}'
{
  "commit": "8b3030114a449e66c68450acaac4b66f26d91416",
  "tree": "64e9b9e283a5b77234adf5008e05aab9ae3b62af",
  "parents": [
    "d9aa68855724752a5684c6acfb17d8db15cec2f8",
    "0614601cecc8e5d9c6c5fa606b39fe388a18583a"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Aug 29 15:48:15 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Aug 29 15:48:15 2014 +0100"
  },
  "message": "Merge remote-tracking branch \u0027remotes/pmaydell/tags/pull-target-arm-20140829\u0027 into staging\n\ntarget-arm queue:\n * support PMCCNTR in ARMv8\n * various GIC fixes and cleanups\n * Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values\n * Fix regression that disabled VFP for ARMv5 CPUs\n * Update to upstream VIXL 1.5\n\n# gpg: Signature made Fri 29 Aug 2014 15:34:47 BST using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n\n* remotes/pmaydell/tags/pull-target-arm-20140829:\n  target-arm: Implement pmccfiltr_write function\n  target-arm: Remove old code and replace with new functions\n  target-arm: Implement pmccntr_sync function\n  target-arm: Add arm_ccnt_enabled function\n  target-arm: Implement PMCCNTR_EL0 and related registers\n  arm: Implement PMCCNTR 32b read-modify-write\n  target-arm: Make the ARM PMCCNTR register 64-bit\n  hw/intc/arm_gic: honor target mask in gic_update()\n  aarch64: raise max_cpus to 8\n  arm_gic: Use GIC_NR_SGIS constant\n  arm_gic: Do not force PPIs to edge-triggered mode\n  arm_gic: GICD_ICFGR: Write model only for pre v1 GICs\n  arm_gic: Fix read of GICD_ICFGR\n  target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values\n  target-arm: Fix regression that disabled VFP for ARMv5 CPUs\n  disas/libvixl: Update to upstream VIXL 1.5\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}