tree b1c36d400bf36f68b0d20a29492b9aa383c71d9b
parent ac60cc18711a9786af9844d7e3d002276fbd85f3
author Peter Maydell <peter.maydell@linaro.org> 1300206411 +0000
committer Aurelien Jarno <aurelien@aurel32.net> 1301690027 +0200

target-arm: Fix VLD of single element to all lanes

Fix several bugs in VLD of single element to all lanes:

The "single element to all lanes" form of VLD1 differs from those for
VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element
should be written to one or two Dregs (rather than being a register
stride). Handle this by special-casing VLD1 rather than trying to
have one loop which deals with both VLD1 and 2/3/4.

Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing.

UNDEF for the invalid size and alignment combinations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>