Compile pci_host only once
Convert pci_host_conf_register_mmio_noswap(x) to
pci_host_conf_register_mmio(x, 0).
Convert pci_host_conf_register_mmio(x) to
pci_host_conf_register_mmio(x, 1) for big endian hosts, all cases
happen to be BE.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
diff --git a/Makefile.objs b/Makefile.objs
index 11dbc62..a38a745 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -129,7 +129,7 @@
hw-obj-y =
hw-obj-y += loader.o
hw-obj-y += virtio.o virtio-console.o
-hw-obj-y += fw_cfg.o pci.o pcie_host.o
+hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o
hw-obj-y += watchdog.o
hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
hw-obj-$(CONFIG_ECC) += ecc.o
diff --git a/Makefile.target b/Makefile.target
index b1d6a7f..bf93560 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -161,7 +161,7 @@
# System emulator target
ifdef CONFIG_SOFTMMU
-obj-y = vl.o monitor.o pci_host.o machine.o gdbstub.o
+obj-y = vl.o monitor.o machine.o gdbstub.o
obj-y += qemu-timer.o
# virtio has to be here due to weird dependency between PCI and virtio-net.
# need to fix this properly
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index fb4973b..024c67c 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -69,8 +69,8 @@
s = FROM_SYSBUS(DECState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index c026bf2..aa0c51b 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -108,8 +108,8 @@
s = FROM_SYSBUS(GrackleState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index 05896af..c18cfba 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -78,27 +78,24 @@
return val;
}
-static void pci_host_config_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write_swap(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
__func__, addr, len, val);
-#ifdef TARGET_WORDS_BIGENDIAN
val = qemu_bswap_len(val, len);
-#endif
s->config_reg = val;
}
-static uint32_t pci_host_config_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s->config_reg;
-#ifdef TARGET_WORDS_BIGENDIAN
+
val = qemu_bswap_len(val, len);
-#endif
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
@@ -125,21 +122,20 @@
return val;
}
-static void pci_host_data_write(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write_swap(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-#ifdef TARGET_WORDS_BIGENDIAN
+
val = qemu_bswap_len(val, len);
-#endif
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
uint32_t val;
@@ -148,32 +144,53 @@
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
-#ifdef TARGET_WORDS_BIGENDIAN
val = qemu_bswap_len(val, len);
-#endif
+ return val;
+}
+
+static void pci_host_data_write_noswap(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
+{
+ PCIHostState *s = container_of(handler, PCIHostState, data_handler);
+ PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
+ addr, len, val);
+ if (s->config_reg & (1u << 31))
+ pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
+}
+
+static uint32_t pci_host_data_read_noswap(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
+{
+ PCIHostState *s = container_of(handler, PCIHostState, data_handler);
+ uint32_t val;
+ if (!(s->config_reg & (1 << 31)))
+ return 0xffffffff;
+ val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
+ PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
+ addr, len, val);
return val;
}
static void pci_host_init(PCIHostState *s)
{
- s->conf_handler.write = pci_host_config_write;
- s->conf_handler.read = pci_host_config_read;
+ s->conf_handler.write = pci_host_config_write_swap;
+ s->conf_handler.read = pci_host_config_read_swap;
s->conf_noswap_handler.write = pci_host_config_write_noswap;
s->conf_noswap_handler.read = pci_host_config_read_noswap;
- s->data_handler.write = pci_host_data_write;
- s->data_handler.read = pci_host_data_read;
+ s->data_handler.write = pci_host_data_write_swap;
+ s->data_handler.read = pci_host_data_read_swap;
+ s->data_noswap_handler.write = pci_host_data_write_noswap;
+ s->data_noswap_handler.read = pci_host_data_read_noswap;
}
-int pci_host_conf_register_mmio(PCIHostState *s)
+int pci_host_conf_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
- return cpu_register_io_memory_simple(&s->conf_handler);
-}
-
-int pci_host_conf_register_mmio_noswap(PCIHostState *s)
-{
- pci_host_init(s);
- return cpu_register_io_memory_simple(&s->conf_noswap_handler);
+ if (swap) {
+ return cpu_register_io_memory_simple(&s->conf_handler);
+ } else {
+ return cpu_register_io_memory_simple(&s->conf_noswap_handler);
+ }
}
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
@@ -182,10 +199,14 @@
register_ioport_simple(&s->conf_noswap_handler, ioport, 4, 4);
}
-int pci_host_data_register_mmio(PCIHostState *s)
+int pci_host_data_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
- return cpu_register_io_memory_simple(&s->data_handler);
+ if (swap) {
+ return cpu_register_io_memory_simple(&s->data_handler);
+ } else {
+ return cpu_register_io_memory_simple(&s->data_noswap_handler);
+ }
}
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
diff --git a/hw/pci_host.h b/hw/pci_host.h
index 5ff6443..bd8ede8 100644
--- a/hw/pci_host.h
+++ b/hw/pci_host.h
@@ -35,6 +35,7 @@
SysBusDevice busdev;
ReadWriteHandler conf_noswap_handler;
ReadWriteHandler conf_handler;
+ ReadWriteHandler data_noswap_handler;
ReadWriteHandler data_handler;
uint32_t config_reg;
PCIBus *bus;
@@ -44,9 +45,8 @@
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
/* for mmio */
-int pci_host_conf_register_mmio(PCIHostState *s);
-int pci_host_conf_register_mmio_noswap(PCIHostState *s);
-int pci_host_data_register_mmio(PCIHostState *s);
+int pci_host_conf_register_mmio(PCIHostState *s, int swap);
+int pci_host_data_register_mmio(PCIHostState *s, int swap);
/* for ioio */
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 2d00b61..c9e3279 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -378,7 +378,7 @@
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
/* CFGDATA */
- index = pci_host_data_register_mmio(&controller->pci_state);
+ index = pci_host_data_register_mmio(&controller->pci_state, 1);
if (index < 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index a72fb86..683e657 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -293,13 +293,13 @@
controller->pci_dev = d;
/* CFGADDR */
- index = pci_host_conf_register_mmio_noswap(&controller->pci_state);
+ index = pci_host_conf_register_mmio(&controller->pci_state, 0);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
/* CFGDATA */
- index = pci_host_data_register_mmio(&controller->pci_state);
+ index = pci_host_data_register_mmio(&controller->pci_state, 0);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 7bdf430..a4866f4 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -155,7 +155,7 @@
/* Uninorth main bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
@@ -175,7 +175,7 @@
/* Uninorth U3 AGP bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
@@ -196,8 +196,8 @@
/* Uninorth AGP bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
@@ -211,8 +211,8 @@
/* Uninorth internal bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
