tree eebb5b45905a7c30f1c8c6e6b996e1a415e0c2c8
parent a703eda18a5c3e9b45f2b9a337a3e1e16c836cf9
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1373430141 +1000
committer Peter Maydell <peter.maydell@linaro.org> 1373904831 +0100

target-arm/helper.c: Implement MIDR aliases

Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default
to aliasing the MIDR register. Set all registers in the space to access
MIDR by default.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 6127846712b7ad2727354a4f5e1d809451f1e859.1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>